TEXAS INSTRUMENTS XIO2001 Technical data

XIO2001

XIO2001 PCI Express™ to PCI Bus Translation Bridge

Data Manual

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Literature Number: SCPS212D

May 2009–Revised January 2010

XIO2001

SCPS212D–MAY 2009–REVISED JANUARY 2010

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Contents

1 Introduction ........................................................................................................................ 9

1.1 Features ...................................................................................................................... 9

2 Overview .......................................................................................................................... 10

2.1 Description ................................................................................................................. 10

2.2 Related Documents ....................................................................................................... 10

2.3 Documents Conventions .................................................................................................. 11

2.4 Document History ......................................................................................................... 11

2.5 Terminal Assignments .................................................................................................... 11

2.6 Terminal Descriptions ..................................................................................................... 15

3 Feature/Protocol Descriptions ............................................................................................. 22

3.1 Power-Up/-Down Sequencing ........................................................................................... 22

3.1.1 Power-Up Sequence ........................................................................................... 23

3.1.2 Power-Down Sequence ........................................................................................ 24

3.2 Bridge Reset Features .................................................................................................... 24

3.3 PCI Express Interface ..................................................................................................... 25

3.3.1 External Reference Clock ..................................................................................... 25

3.3.2 Beacon ........................................................................................................... 26

3.3.3 Wake ............................................................................................................. 26

3.3.4 Initial Flow Control Credits .................................................................................... 26

3.3.5 PCI Express Message Transactions ......................................................................... 26

3.4 PCI Bus Interface .......................................................................................................... 27

3.4.1 I/O Characteristics .............................................................................................. 27

3.4.2 Clamping Voltage ............................................................................................... 27

3.4.3 PCI Bus Clock Run ............................................................................................. 28

3.4.4 PCI Bus External Arbiter ....................................................................................... 28

3.4.5 MSI Messages Generated from the Serial IRQ Interface ................................................. 28

3.4.6 PCI Bus Clocks ................................................................................................. 29

3.5 PCI Port Arbitration ........................................................................................................ 30

3.5.1 Classic PCI Arbiter ............................................................................................. 30

3.6 Configuration Register Translation ...................................................................................... 30

3.7 PCI Interrupt Conversion to PCI Express Messages ................................................................. 32

3.8 PME Conversion to PCI Express Messages ........................................................................... 32

3.9 PCI Express to PCI Bus Lock Conversion ............................................................................. 33

3.10 Two-Wire Serial-Bus Interface ........................................................................................... 34

3.10.1 Serial-Bus Interface Implementation ......................................................................... 34

3.10.2 Serial-Bus Interface Protocol .................................................................................. 35

3.10.3 Serial-Bus EEPROM Application ............................................................................. 37

3.10.4 Accessing Serial-Bus Devices Through Software .......................................................... 39

3.11 Advanced Error Reporting Registers ................................................................................... 39

3.12 Data Error Forwarding Capability ....................................................................................... 39

3.13 General-Purpose I/O Interface ........................................................................................... 40

3.14 Set Slot Power Limit Functionality ....................................................................................... 40

3.15 PCI Express and PCI Bus Power Management ....................................................................... 40

3.16 Auto Pre-Fetch Agent ..................................................................................................... 41

4 Classic PCI Configuration Space ......................................................................................... 42

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4.1 Vendor ID Register ........................................................................................................ 43

4.2 Device ID Register ........................................................................................................ 43

4.3 Command Register ........................................................................................................ 44

4.4 Status Register ............................................................................................................ 45

4.5 Class Code and Revision ID Register .................................................................................. 46

4.6 Cache Line Size Register ................................................................................................ 46

4.7 Primary Latency Timer Register ......................................................................................... 47

4.8 Header Type Register .................................................................................................... 47

4.9 BIST Register .............................................................................................................. 47

4.10 Device Control Base Address Register ................................................................................. 47

4.11 Primary Bus Number Register ........................................................................................... 48

4.12 Secondary Bus Number Register ....................................................................................... 48

4.13 Subordinate Bus Number Register ...................................................................................... 48

4.14 Secondary Latency Timer Register ..................................................................................... 49

4.15 I/O Base Register .......................................................................................................... 49

4.16 I/O Limit Register .......................................................................................................... 49

4.17 Secondary Status Register ............................................................................................... 50

4.18 Memory Base Register ................................................................................................... 51

4.19 Memory Limit Register .................................................................................................... 51

4.20 Prefetchable Memory Base Register ................................................................................... 51

4.21 Prefetchable Memory Limit Register .................................................................................... 52

4.22 Prefetchable Base Upper 32-Bit Register .............................................................................. 52

4.23 Prefetchable Limit Upper 32-Bit Register .............................................................................. 53

4.24 I/O Base Upper 16-Bit Register .......................................................................................... 53

4.25 I/O Limit Upper 16-Bit Register .......................................................................................... 53

4.26 Capabilities Pointer Register ............................................................................................. 54

4.27 Interrupt Line Register .................................................................................................... 54

4.28 Interrupt Pin Register ..................................................................................................... 54

4.29 Bridge Control Register ................................................................................................... 55

4.30 Capability ID Register ..................................................................................................... 57

4.31 Next Item Pointer Register ............................................................................................... 57

4.32 Subsystem Vendor ID Register .......................................................................................... 57

4.33 Subsystem ID Register ................................................................................................... 58

4.34 Capability ID Register ..................................................................................................... 58

4.35 Next Item Pointer Register ............................................................................................... 58

4.36 Power Management Capabilities Register ............................................................................. 58

4.37 Power Management Control/Status Register .......................................................................... 59

4.38 Power Management Bridge Support Extension Register ............................................................ 60

4.39 Power Management Data Register ..................................................................................... 60

4.40 MSI Capability ID Register ............................................................................................... 60

4.41 Next Item Pointer Register ............................................................................................... 61

4.42 MSI Message Control Register .......................................................................................... 61

4.43 MSI Message Lower Address Register ................................................................................. 61

4.44 MSI Message Upper Address Register ................................................................................. 62

4.45 MSI Message Data Register ............................................................................................. 62

SCPS212D–MAY 2009–REVISED JANUARY 2010

XIO2001

SCPS212D–MAY 2009–REVISED JANUARY 2010

4.46 PCI Express Capability ID Register ..................................................................................... 63

4.47 Next Item Pointer Register ............................................................................................... 63

4.48 PCI Express Capabilities Register ...................................................................................... 63

4.49 Device Capabilities Register ............................................................................................. 64

4.50 Device Control Register .................................................................................................. 65

4.51 Device Status Register ................................................................................................... 66

4.52 Link Capabilities Register ................................................................................................ 66

4.53 Link Control Register ...................................................................................................... 67

4.54 Link Status Register ....................................................................................................... 68

4.55 Serial-Bus Data Register ................................................................................................. 69

4.56 Serial-Bus Word Address Register ...................................................................................... 69

4.57 Serial-Bus Slave Address Register ..................................................................................... 70

4.58 Serial-Bus Control and Status Register ................................................................................ 70

4.59 GPIO Control Register .................................................................................................... 71

4.60 GPIO Data Register ....................................................................................................... 72

4.61 TL Control and Diagnostic Register 0 .................................................................................. 72

4.62 Control and Diagnostic Register 1 ...................................................................................... 73

4.63 Control and Diagnostic Register 2 ...................................................................................... 74

4.64 Subsystem Access Register ............................................................................................. 74

4.65 General Control Register ................................................................................................. 76

4.66 Clock Control Register .................................................................................................... 78

4.67 Clock Mask Register ...................................................................................................... 79

4.68 Clock Run Status Register ............................................................................................... 80

4.69 Arbiter Control Register ................................................................................................... 81

4.70 Arbiter Request Mask Register .......................................................................................... 83

4.71 Arbiter Time-Out Status Register ........................................................................................ 84

4.72 Serial IRQ Mode Control Register ....................................................................................... 84

4.73 Serial IRQ Edge Control Register ....................................................................................... 85

4.74 Serial IRQ Status Register ............................................................................................... 87

4.75 Pre-Fetch Agent Request Limits Register .............................................................................. 88

4.76 Cache Timer Transfer Limit Register ................................................................................... 89

4.77 Cache Timer Lower Limit Register ...................................................................................... 90

4.78 Cache Timer Upper Limit Register ...................................................................................... 90

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5 PCI Express Extended Configuration Space ......................................................................... 91

5.1 Advanced Error Reporting Capability ID Register ..................................................................... 91

5.2 Next Capability Offset/Capability Version Register ................................................................... 92

5.3 Uncorrectable Error Status Register .................................................................................... 92

5.4 Uncorrectable Error Mask Register ..................................................................................... 93

5.5 Uncorrectable Error Severity Register .................................................................................. 94

5.6 Correctable Error Status Register ....................................................................................... 95

5.7 Correctable Error Mask Register ........................................................................................ 96

5.8 Advanced Error Capabilities and Control Register .................................................................... 97

5.9 Header Log Register ...................................................................................................... 97

5.10 Secondary Uncorrectable Error Status Register ...................................................................... 98

5.11 Secondary Uncorrectable Error Mask Register ........................................................................ 99

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5.12 Secondary Uncorrectable Error Severity .............................................................................. 100

5.13 Secondary Error Capabilities and Control Register ................................................................. 101

5.14 Secondary Header Log Register ....................................................................................... 102

SCPS212D–MAY 2009–REVISED JANUARY 2010

6 Memory-Mapped TI Proprietary Register Space ................................................................... 103

6.1 Device Control Map ID Register ....................................................................................... 103

6.2 Revision ID Register ..................................................................................................... 104

6.3 GPIO Control Register .................................................................................................. 104

6.4 GPIO Data Register ..................................................................................................... 105

6.5 Serial-Bus Data Register ................................................................................................ 106

6.6 Serial-Bus Word Address Register .................................................................................... 106

6.7 Serial-Bus Slave Address Register .................................................................................... 106

6.8 Serial-Bus Control and Status Register ............................................................................... 107

6.9 Serial IRQ Mode Control Register ..................................................................................... 108

6.10 Serial IRQ Edge Control Register ..................................................................................... 108

6.11 Serial IRQ Status Register .............................................................................................. 110

6.12 Pre-Fetch Agent Request Limits Register ............................................................................ 112

6.13 Cache Timer Transfer Limit Register .................................................................................. 113

6.14 Cache Timer Lower Limit Register .................................................................................... 113

6.15 Cache Timer Upper Limit Register .................................................................................... 114

7 Electrical Characteristics .................................................................................................. 115

7.1 Absolute Maximum Ratings ............................................................................................. 115

7.2 Recommended Operating Conditions ................................................................................. 115

7.3 Nominal Power Consumption .......................................................................................... 116

7.4 PCI Express Differential Transmitter Output Ranges ............................................................... 116

7.5 PCI Express Differential Receiver Input Ranges .................................................................... 117

7.6 PCI Express Differential Reference Clock Input Ranges ........................................................... 118

7.7 PCI Bus Electrical Characteristics ..................................................................................... 119

7.8 3.3-V I/O Electrical Characteristics .................................................................................... 119

7.9 PCI Bus Timing Requirements ......................................................................................... 120

7.10 PNP Thermal Characteristics ........................................................................................... 120

7.11 ZAJ Thermal Characteristics ........................................................................................... 120

7.12 ZGU Thermal Characteristics .......................................................................................... 121

7.13 Parameter Measurement Information ................................................................................. 122

PCI Bus ................................................................................................................... 122

8 Glossary ......................................................................................................................... 123

XIO2001

SCPS212D–MAY 2009–REVISED JANUARY 2010

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List of Figures

2-1 XIO2001 ZGU MicroStar BGA Package (Bottom View)..................................................................... 13

2-2 XIO2001 ZAJ MicroStar BGA Package (Bottom View)...................................................................... 14

2-3 XIO2001 PNP PowerPad™ HTQFP Package (Top View).................................................................. 14

3-1 XIO2001 Block Diagram......................................................................................................... 22

3-2 Power-Up Sequence............................................................................................................. 23

3-3 Power-Down Sequence ......................................................................................................... 24

3-4 3-State Bidirectional Buffer...................................................................................................... 27

3-5 Type 0 Configuration Transaction Address Phase Encoding............................................................... 30

3-6 Type 1 Configuration Transaction Address Phase Encoding............................................................... 31

3-7 PCI Express ASSERT_INTX Message........................................................................................ 32

3-8 PCI Express DEASSERT_INTX Message.................................................................................... 32

3-9 PCI Express PME Message .................................................................................................... 33

3-10 Starting a Locked Sequence.................................................................................................... 33

3-11 Continuing a Locked Sequence ................................................................................................ 34

3-12 Terminating a Locked Sequence............................................................................................... 34

3-13 Serial EEPROM Application .................................................................................................... 35

3-14 Serial-Bus Start/Stop Conditions and Bit Transfers.......................................................................... 36

3-15 Serial-Bus Protocol Acknowledge.............................................................................................. 36

3-16 Serial-Bus Protocol – Byte Write ............................................................................................... 36

3-17 Serial-Bus Protocol – Byte Read............................................................................................... 37

3-18 Serial-Bus Protocol – Multibyte Read ......................................................................................... 37

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SCPS212D–MAY 2009–REVISED JANUARY 2010

List of Tables

2-1 Power Supply Terminals ........................................................................................................ 15

2-2 Ground Terminals ................................................................................................................ 16

2-3 Combined Power Output Terminals ........................................................................................... 16

2-4 PCI Express Terminals .......................................................................................................... 16

2-5 PCI System Terminals........................................................................................................... 17

2-6 JTAG Terminals .................................................................................................................. 19

2-7 Miscellaneous Terminals ........................................................................................................ 20

3-1 XIO2001 Reset Options ......................................................................................................... 24

3-2 Initial Flow Control Credit Advertisements.................................................................................... 26

3-3 Messages Supported by the Bridge ........................................................................................... 26

3-4 IRQ Interrupt to MSI Message Mapping....................................................................................... 29

3-5 Classic PCI Arbiter Registers................................................................................................... 30

3-6 Type 0 Configuration Transaction

IDSEL Mapping................................................................................................................... 31

3-7 Interrupt Mapping In The Code Field.......................................................................................... 32

3-8 EEPROM Register Loading Map............................................................................................... 37

3-9 Registers Used To Program Serial-Bus Devices............................................................................. 39

3-10 Clocking In Low Power States.................................................................................................. 41

4-1 Classic PCI Configuration Register Map...................................................................................... 42

4-2 Command Register Description ............................................................................................... 44

4-3 Status Register Description .................................................................................................... 45

4-4 Class Code and Revision ID Register Description .......................................................................... 46

4-5 Device Control Base Address Register Description ........................................................................ 48

4-6 I/O Base Register Description ................................................................................................. 49

4-7 I/O Limit Register Description .................................................................................................. 49

4-8 Secondary Status Register Description ...................................................................................... 50

4-9 Memory Base Register Description ........................................................................................... 51

4-10 Memory Limit Register Description ............................................................................................ 51

4-11 Prefetchable Memory Base Register Description ........................................................................... 52

4-12 Prefetchable Memory Limit Register Description ............................................................................ 52

4-13 Prefetchable Base Upper 32-Bit Register Description ...................................................................... 52

4-14 Prefetchable Limit Upper 32-Bit Register Description ...................................................................... 53

4-15 I/O Base Upper 16-Bit Register Description ................................................................................. 53

4-16 I/O Limit Upper 16-Bit Register Description .................................................................................. 54

4-17 Bridge Control Register Description ........................................................................................... 55

4-18 Power Management Capabilities Register Description ..................................................................... 59

4-19 Power Management Control/Status Register Description .................................................................. 59

4-20 PM Bridge Support Extension Register Description ........................................................................ 60

4-21 MSI Message Control Register Description .................................................................................. 61

4-22 MSI Message Lower Address Register Description ........................................................................ 62

4-23 MSI Message Data Register Description ..................................................................................... 62

4-24 PCI Express Capabilities Register Description .............................................................................. 63

4-25 Device Capabilities Register Description ..................................................................................... 64

4-26 Device Control Register Description .......................................................................................... 65

4-27 Device Status Register Description ........................................................................................... 66

4-28 Link Capabilities Register Description ........................................................................................ 67

4-29 Link Control Register Description ............................................................................................. 67

XIO2001

SCPS212D–MAY 2009–REVISED JANUARY 2010

4-30 Link Status Register Description .............................................................................................. 68

4-31 Serial-Bus Slave Address Register Descriptions ............................................................................ 70

4-32 Serial-Bus Control and Status Register Description ........................................................................ 70

4-33 GPIO Control Register Description ............................................................................................ 71

4-34 GPIO Data Register Description ............................................................................................... 72

4-35 Control and Diagnostic Register 0 Description .............................................................................. 72

4-36 Control and Diagnostic Register 1 Description .............................................................................. 73

4-37 Control and Diagnostic Register 2 Description .............................................................................. 74

4-38 Subsystem Access Register Description ..................................................................................... 75

4-39 General Control Register Description ......................................................................................... 76

4-40 Clock Control Register Description ............................................................................................ 78

4-41 Clock Mask Register Description .............................................................................................. 79

4-42 Clock Run Status Register Description ....................................................................................... 80

4-43 Clock Control Register Description ............................................................................................ 81

4-44 Arbiter Request Mask Register Description .................................................................................. 83

4-45 Arbiter Time-Out Status Register Description ............................................................................... 84

4-46 Serial IRQ Mode Control Register Description .............................................................................. 85

4-47 Serial IRQ Edge Control Register Description ............................................................................... 85

4-48 Serial IRQ Status Register Description ....................................................................................... 87

4-49 Pre-Fetch Agent Request Limits Register Description ..................................................................... 89

4-50 Cache Timer Transfer Limit Register Description ........................................................................... 90

4-51 Cache Timer Lower Limit Register Description .............................................................................. 90

4-52 Cache Timer Upper Limit Register Description .............................................................................. 90

5-1 PCI Express Extended Configuration Register Map......................................................................... 91

5-2 Uncorrectable Error Status Register Description ............................................................................ 92

5-3 Uncorrectable Error Mask Register Description ............................................................................. 93

5-4 Uncorrectable Error Severity Register Description .......................................................................... 94

5-5 Correctable Error Status Register Description ............................................................................... 95

5-6 Correctable Error Mask Register Description ................................................................................ 96

5-7 Advanced Error Capabilities and Control Register Description ........................................................... 97

5-8 Secondary Uncorrectable Error Status Register Description .............................................................. 98

5-9 Secondary Uncorrectable Error Mask Register Description ............................................................... 99

5-10 Secondary Uncorrectable Error Severity Register Description .......................................................... 100

5-11 Secondary Error Capabilities and Control Register Description ......................................................... 101

5-12 Secondary Header Log Register Description .............................................................................. 102

6-1 Device Control Memory Window Register Map............................................................................. 103

6-2 GPIO Control Register Description .......................................................................................... 104

6-3 GPIO Data Register Description ............................................................................................. 105

6-4 Serial-Bus Slave Address Register Descriptions .......................................................................... 106

6-5 Serial-Bus Control and Status Register Description ....................................................................... 107

6-6 Serial IRQ Mode Control Register Description ............................................................................. 108

6-7 Serial IRQ Edge Control Register Description ............................................................................. 109

6-8 Serial IRQ Status Register Description ..................................................................................... 110

6-9 Pre-Fetch Agent Request Limits Register Description .................................................................... 112

6-10 Cache Timer Transfer Limit Register Description ......................................................................... 113

6-11 Cache Timer Lower Limit Register Description ............................................................................ 114

6-12 Cache Timer Upper Limit Register Description ............................................................................ 114

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XIO2001

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SCPS212D–MAY 2009–REVISED JANUARY 2010

XIO2001 PCI Express™ to PCI Bus Translation Bridge

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1 Introduction

1.1 Features

1 234

• Full ×1 PCI Express Throughput

• Fully Compliant with PCI Express to PCI/PCI-X

Bridge Specification, Revision 1.0

• Fully Compliant with PCI Express Base

Specification, Revision 2.0

• Fully Compliant with PCI Local Bus

Specification, Revision 2.3

• PCI Express Advanced Error Reporting

Capability Including ECRC Support • PCI Bus LOCK Support

• Support for D1, D2, D3

, and D3

hot

cold

• Active-State Link Power Management Saves • PCI-Express CLKREQ Support

Power When Packet Activity on the PCI Express Link is Idle, Using Both L0s and L1 States

• Wake Event and Beacon Support

• Error Forwarding Including PCI Express Data

Poisoning and PCI Bus Parity Errors

• Utilizes 100-MHz Differential PCI Express

Common Reference Clock or 125-MHz Single-Ended, Reference Clock

• Optional Spread Spectrum Reference Clock is

Supported

• Robust Pipeline Architecture To Minimize

Transaction Latency

• Full PCI Local Bus 66-MHz/32-Bit Throughput

• Support for Six Subordinate PCI Bus Masters MicroStar BGA, and PowerPad™ HTQFP

with Internal Configurable, 2-Level 128-Pin PNP Package

Prioritization Scheme

• Two Package Options: 12 mm × 12 mm and 7 mm × 7 mm

• Internal PCI Arbiter Supporting Up to 6 External PCI Masters

• Advanced PCI Express Message Signaled Interrupt Generation for Serial IRQ Interrupts

• External PCI Bus Arbiter Option

• JTAG/BS for Production Test

• Clock Run and Power Override Support

• Six Buffered PCI Clock Outputs (25 MHz, 33 MHz, 50 MHz, or 66 MHz)

• PCI Bus Interface 3.3-V and 5.0-V (25 MHz or 33 MHz only at 5.0 V) Tolerance Options

• Integrated AUX Power Switch Drains V

AUX

Power Only When Main Power Is Off

• Five 3.3-V, Multifunction, General-Purpose I/O Terminals

• Memory-Mapped EEPROM Serial-Bus Controller Supporting PCI Express Power Budget/Limit Extensions for Add-In Cards

• Compact Footprint, Lead-Free 144-Ball, ZAJ MicroStar™ BGA, Lead-Free 169-Ball ZGU

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPad, MicroStar are trademarks of Texas Instruments. 3PCI Express is a trademark of PCI-SIG. 4All other trademarks are the property of their respective owners.

XIO2001

SCPS212D–MAY 2009–REVISED JANUARY 2010

2 Overview

The Texas Instruments XIO2001 is a PCI Express to PCI local bus translation bridge that provides full PCI Express and PCI local bus functionality and performance.

2.1 Description

The XIO2001 is a single-function PCI Express to PCI translation bridge that is fully compliant to the PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0. For downstream traffic, the bridge

simultaneously supports up to eight posted and four non-posted transactions. For upstream traffic, up to six posted and and four non-posted transactions are simultaneously supported.

The PCI Express interface is fully compliant to the PCI Express Base Specification, Revision 2.0. The PCI Express interface supports a ×1 link operating at full 250 MB/s packet throughput in each

direction simultaneously. Also, the bridge supports the advanced error reporting including extended CRC (ECRC) as defined in the PCI Express Base Specification. Supplemental firmware or software is required to fully utilize both of these features.

Robust pipeline architecture is implemented to minimize system latency across the bridge. If parity errors are detected, then packet poisoning is supported for both upstream and downstream operations.

The PCI local bus is fully compliant with the PCI Local Bus Specification (Revision 2.3) and associated programming model. Also, the bridge supports the standard PCI-to-PCI bridge programming model. The PCI bus interface is 32-bit and can operate at either 25 MHz, 33 MHz, 50 MHz, or 66 MHz. Also, the PCI interface provides fair arbitration and buffered clock outputs for up to 6 subordinate devices.

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Power management (PM) features include active state link PM, PME mechanisms, the beacon and wake protocols, and all conventional PCI D-states. If the active state link PM is enabled, then the link automatically saves power when idle using the L0s and L1 states. PM active state NAK, PM PME, and PME-to-ACK messages are supported. Standard PCI bus power management features provide several low power modes, which enable the host system to further reduce power consumption.

The bridge has additional capabilities including, but not limited to, serial IRQ with MSI messages, serial EEPROM, power override, clock run, PCI Express clock request and PCI bus LOCK. Also, five general-purpose inputs and outputs (GPIOs) are provided for further system control and customization.

2.2 Related Documents

• PCI Express to PCI/PCI-X Bridge Specification, Revision 1.0

• PCI Express Base Specification, Revision 2.0

• PCI Express Card Electromechanical Specification, Revision 2.0

• PCI Local Bus Specification, Revision 2.3

• PCI-to-PCI Bridge Architecture Specification, Revision 1.2

• PCI Bus Power Management Interface Specification, Revision 1.2

• PCI Mobile Design Guide, Revision 1.1

• Serialized IRQ Support for PCI Systems, Revision 6.0

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2.3 Documents Conventions

Throughout this data manual, several conventions are used to convey information. These conventions are listed below:

1. To identify a binary number or field, a lower case b follows the numbers. For example: 000b is a 3-bit binary field.

2. To identify a hexadecimal number or field, a lower case h follows the numbers. For example: 8AFh is a 12-bit hexadecimal field.

3. All other numbers that appear in this document that do not have either a b or h following the number are assumed to be decimal format.

4. If the signal or terminal name has a bar above the name (for example, GRST), then this indicates the logical NOT function. When asserted, this signal is a logic low, 0, or 0b.

5. Differential signal names end with P, N, +, or – designators. The P or + designators signify the positive signal associated with the differential pair. The N or – designators signify the negative signal associated with the differential pair.

6. RSVD indicates that the referenced item is reserved.

7. In Sections 4 through 6, the configuration space for the bridge is defined. For each register bit, the software access method is identified in an access column. The legend for this access column includes the following entries:

– r – read access by software – u – updates by the bridge internal hardware – w – write access by software – c – clear an asserted bit with a write-back of 1b by software. Write of zero to the field has no effect – s – the field may be set by a write of one. Write of zero to the field has no effect – na – not accessible or not applicable

SCPS212D–MAY 2009–REVISED JANUARY 2010

2.4 Document History

REVISION REVISION

DATE NUMBER

5/2009 – Initial release 5/2009 A Corrected typos 9/2009 B

10/2009 C

1/2010 D Corrected PNP pinout, replaced Ordering Information with Package Option Addendum

Added PNP package and ESD ratings Removed terminal assignment tables for all packages

REVISION COMMENTS

2.5 Terminal Assignments

The XIO2001 is available in either a 169-ball ZGU MicroStar BGA or a 144−ball ZAJ MicroStar BGA package.

Figure 2-1 shows a terminal diagram of the ZGU package. Figure 2-2 shows a terminal diagram of the ZAJ package. Figure 2-3 shows a terminal diagram of the PNP package.

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1 2 3 4 5 6 7 8 9 10 11 12 13

N N

M M

L L

K K

J J

H H

G G

F F

AD15 AD14 AD13 VDD_33 VSS VSS VSS VSS VSS VSSA VSSA RXN RXP

D D

C C

B B

A A

1 2 3 4 5 6 7 8 9 10 11 12 13

/BE[3] AD25 AD27 AD30 AD31 INTB PRST SERIRQ GPIO0// GPIO2 GPIO3//SDA JTAG_TDI GRST

AD20 AD22 AD24 AD26 AD28 I

NTA INTC LOCK GPIO1// GP IO4// JTAG_TDO JTAG_TCK WAKE

TOP PERR SERR# VDD_15 VSS VSS VSS VSS VSS VDD_15 VSSA TXN TXP

PAR C

/BE[1] CLK VSS VSS VSS VSS VSS VSS VDD_15 VSS VSS VDDA_15

AD12 AD11 AD8 VSS VDD_33 VSS VDD_15 VSS VDD_33 VSS C

LKREQ VREG_PD33 VDDA_33

_SEL

PCIR

AD4 AD1 R

EQ0 GNT0 REQ1 CLKOUT2 REQ2 CLKOUT4 CLKOUT5 GNT4 RE Q5 CLKRUN_EN

AD16 AD17

PCIR

VSS VSS VSS VDD_15 VSS VDD_33 VSSA VDD_33_ REF0_PCIE REF1_PCIE

RDY FRAME C/BE[2] VDD _33 VSS VSS VSS VSS VSS VSS VDD_33_ VDD_33 VDD_33_

RDY DEVSEL VDD_33 VSS VSS VSS VSS VSS VSS VDD_15 PERST VSSA VDDA_15

CLKRUN

AD10 AD9 AD7 AD5 AD0 GNT1 VDD_33 REQ3 REQ4 EXT_ARB_EN VSSA REFCLK– REFCLK+

C/BE[0] AD6 AD3 AD2 CLKOUT0 CLKOUT1 CLKOUT3 GNT2 GNT3 GNT5 CLKOUT6 PCLK66_SEL REFCLK125

AUX COMB

COMB_IO

AD18 AD19 AD21 AD23 AD29 M66EN INTD VDD_33 JTAG_ JTAG_TMS VSS PME VDD_15_

TRST# COMB

PWR_OVRD SCL

XIO2001

SCPS212D–MAY 2009–REVISED JANUARY 2010

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Figure 2-1. XIO2001 ZGU MicroStar BGA Package (Bottom View)

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1 2 3 4 5 6 7 8 9 10 11 12 13

N N

M M

L L

K K

J J

H H

G G

F F

AD13 AD12 AD14 VDD_33 VSS VSS VSS VSS VREG_PD33 VDDA_15 RXP

D D

C C

B B

A A

1 2 3 4 5 6 7 8 9 10 11 12 13

AD21 AD24 AD27 AD28 AD31 I

NTA INTD LOCK GPIO0// GPIO2 JTAG_TDO JTAG_TCK VDD_15_

AD18 AD22 C

/BE[3] AD25 AD29 M66EN INTC SERIRQ GPIO1// GPIO4_ GRS T PME REF0_PCIE

PAR S

ERR PERR VSS VDD_33 VDD_33 VDD_15 VSSA VDD_15 VSSA TXN

CLK AD15 C/BE[1]

VSS VDD_33 VDD_33 VDD_33 VSS VDD_15 VSS VSSA

AD11 AD9

PCIR

CLKREQ

VSSA RXN

AD7 AD4 AD3 R

EQ0 GNT0 GNT1 CLKOUT3 CLKOUT4 REQ4 CLKOUT5 PCLK66_ EXT_ARB_ REFCLK125

C/BE[2]

AD19 AD17 VDD_33_ VDD_33_ VDD_15

FRAME

TRDY

PCIR

VSS VSS VDD_15 VDD_15 VSS VDD_33 VDD_33_ VSSA

TOP DEVSEL IRDY VSS VDD_33 VDD_33 VDD_15 VSS PERST VDDA_15 TXP

CLKRUN

AD10 C/BE[0] AD5 AD2 AD1 REQ1 REQ2 REQ3 REQ5 CLKOUT6 CLKRUN_EN VDDA_33 REFCLK+

AD8 AD6 AD0 CLKOUT0 CLKOUT1 CLKOUT2 GNT2 GNT3 GNT4 GNT5 VSSA REFCLK-

AD16 AD20 AD23 AD26 AD30 INTB PRST GPIO3//SDA JTAG_ JTAG_TDI JTAG_TMS WAKE REF1_PCIE

RST

PWR_OVRD SCL

COMB

SEL EN _SEL

AUX

COMB_IO COMB

XIO2001

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Figure 2-2. XIO2001 ZAJ MicroStar BGA Package (Bottom View)

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128

121

118

105

124

113

110

100

126

117

114

102

122

109

106

127

119

116

103

123

111

108

125

115

112

101

120

107

104

AD7

VCCP

C/BE[0]

AD8 AD9

AD10

VDD_33

AD11 AD12 AD13 AD14 AD15

CLK

C/BE[1]

SERR PERR STOP

DEVSEL

PAR

VDD_33

VDD_15

TRDY

IRDY

FRAME

C/BE[2]

AD16

VCCP

AD17 AD18 AD19 AD20 AD21

AD26

AD25

AD24

C/BE[3]

AD23

AD22

VDD_33

AD27

AD28

AD29

AD30

AD31

M66EN

VDD_33

INTA

INTB

INTC

INTD

PRST

SERIRQ

VDD_15

LOCK

GPIO0 // CLKRUN

GPIO1 // PWR_OVER

GPIO2

GPIO3 // SDA

GPIO4 // SCL

JTAG_TRST

JTAG_TDO

VDD_33

JTAG_TDI

JTAG_TMS

CLKRUN_EN

JTAG_TCK

GRST

REFCLK125_SEL REFCLK– REFCLK+ VDDA_33_REF_CLK CLKREQ VREG_PD33 VSSA_PCIE RXN

RXP VSSA_PCIE VDDA_15_PCIE_RX VDDPLL_15_PCIE VDD_15_PCIE VSSA_PCIE TXN TXP VSSA_PCIE VDDA_15_PCIE_TX

PERST VDD_15_MAIN VDD_33_COMB VDD_33_MAIN VDD_33_AUX REF1_PCIE REF0_PCIE VDD_33_COM_IO VDD_15_COMB

WAKE PME

AD6

AD5

VDD_33

AD4

AD3

AD2

AD1

AD0

CLKOUT0

REQ0

CLKOUT1

GNT0

REQ1

GNT1

CLKOUT2

VDD_15

CLKOUT3

REQ2

GNT2

REQ3

CLKOUT4

GNT3

REQ4

CLKOUT5

GNT4

REQ5

GNT5

VDD_33

CLKOUT6

PCLK66_SEL

EXT_ARB_EN

XIO2001

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Figure 2-3. XIO2001 PNP PowerPad™ HTQFP Package (Top View)

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2.6 Terminal Descriptions

The following tables give a description of the terminals. These terminals are grouped in tables by functionality. Each table includes the terminal name, terminal number, I/O type, and terminal description.

The following list describes the different input/output cell types that appear in the terminal description tables:

• HS DIFF IN = High speed differential input

• HS DIFF OUT = High speed differential output

• PCI BUS = PCI bus 3-state bidirectional buffer with 3.3-V or 5.0-V clamp rail.

• LV CMOS = 3.3-V low voltage CMOS input or output with 3.3-V clamp rail

• BIAS = Input/output terminals that generate a bias voltage to determine a driver's operating current

• Feed through = these terminals connect directly to macros within the part and not through an input or output cell.

• PWR = Power terminal

• GND = Ground terminal

Table 2-1. Power Supply Terminals

SIGNAL DESCRIPTION

PCIR A01, K03 D03, J03 I/O Resistor PCI Rail. 5.0-V or 3.3-V PCI bus clamp voltage to set

DD_15

DDA_15

DD_33

DD_33_AUX

DDA_33

ZGU ZAJ PNP I/O EXTERNAL

BALL # BALL # PIN # TYPE PARTS

maximum I/O voltage tolerance of the secondary PCI bus signals. Connect this terminal to the secondary PCI bus I/O clamp rail through a 1kΩ resistor.

G04, K07, J08, H08, 21, 53, 113 PWR Bypass 1.5-V digital core power terminals D07, H10, J07, G08, capacitors

G10, F10 N13, K13,

G11, F11

F13, H13 E12, H12 PWR Pi filter 1.5-V analog power terminal

E04, H03, E05, G06, 7, 19, 33, 46, PWR Bypass 3.3-V digital I/O power terminal

J04, L08, H07, G07, 62, 100, 111, capacitors K09, D09, H06, F08, 126 C07, D05, F07, F06,

J12 J11 J11 J12 73 PWR Bypass 3.3-V auxiliary power terminal Note: This terminal is

capacitors connected to VSSthrough a pulldown resistor if no

auxiliary supply is present.

D13 C12 PWR Pi filter 3.3-V analog power terminal

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Table 2-2. Ground Terminals

SIGNAL ZGU BALL # ZAJ BALL # I/O TYPE DESCRIPTION

D04, F04, H04, E06, F05, G05, H05, GND Digital ground terminals K04, K05, K06, J05, J06, J09, H09,

K08, L11, J10, E09, E08, E07, F12 D10, D08, D06, ,F09

F11, F12

E05, E06, E07, GND Ground terminals for thermally-enhanced package

E08, E09, F05,

F06, F07, F08, F09, G05, G06,

G07, G08, G09,

H05, H06, H07,

H08, H09, J05,

J06, J07, J08,

J09

SSA

K10, C11, H12, G09, B12, J13, G12, GND Analog ground terminal

G11, E11, E10 F13, D12

Table 2-3. Combined Power Output Terminals

SIGNAL DESCRIPTION

DD_15_COMB

DD_33_COMB

DD_33_COMBIO

ZGU ZAJ PNP I/O EXTERNAL

BALL # BALL # PIN # TYPE PARTS

L13 N13 69 Internally-combined 1.5-V main and V

Feed Bypass

through capacitors

output for external bypass capacitor filtering. Supplies all internal 1.5-V circuitry powered by V

Caution: Do not use this terminal to supply external power to other devices.

J13 K12 75 Internally-combined 3.3-V main and V

Feed Bypass

through capacitors

output for external bypass capacitor filtering. Supplies all internal 3.3-V circuitry powered by V

Caution: Do not use this terminal to supply external power to other devices.

K11 K11 70 Internally-combined 3.3-V main and V

output for external bypass capacitor filtering.

Feed Bypass

through capacitors

Supplies all internal 3.3-V input/output circuitry powered by V

AUX

Caution: Do not use this terminal to supply external power to other devices.

AUX

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power

AUX

power

AUX

power

Table 2-4. PCI Express Terminals

SIGNAL DESCRIPTION

CLKREQ D11 D11 91 0 LV V

PERST H11 H11 77 I LV V

REFCLK125_SEL B13 A13 95 I LV V

ZGU ZAJ PNP I/O CELL CLAMP EXTERNAL

BALL # BALL # PIN # TYPE TYPE RAIL PARTS

CMOS

CMOS reference clock input.

DD_33_

COMBIO

DD_33_

COMBIO

DD_33

–

Pullup or pulldown 0 = 100-MHz differential common reference clock

resistor used.

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Clock request. When asserted low, requests upstream device start clock in cases where clock may be removed in L1.

Note: Since CLKREQ is an open-drain output buffer, a system side pullup resistor is required.

PCI Express reset input. The PERST signal identifies when the system power is stable and generates an internal power on reset.

Note: The PERST input buffer has hysteresis. Reference clock select. This terminal selects the

1 = 125-MHz single-ended, reference clock used.

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Table 2-4. PCI Express Terminals (continued)

SIGNAL DESCRIPTION

REFCLK+ C13 C13 93 DI HS DIFF V

REFCLK– C12 B13 94 DI HS DIFF V

REF0_PCIE K12 M13 71 I/O BIAS – External reference resistor + and – terminals for REF1_PCIE K13 L13 72 setting TX driver current. An external resistance

RXP E13 E13 87 DI HS DIFF V RXN E12 D13 88 IN – the differential receive pair for the single PCI

TXP G13 H13 80 DO HS DIFF V TXN G12 G13 81 OUT the differential transmit pair for the single PCI

WAKE M13 L12 68 O LV V

ZGU ZAJ PNP I/O CELL CLAMP EXTERNAL

BALL # BALL # PIN # TYPE TYPE RAIL PARTS

IN comprise the differential input pair for the

CMOS

DD_33

DD_15

DD_33_

COMBIO

– 100-MHz system reference clock. For a

Capacitor

for VSSfor

single-

ended node

External

resistor

Series

capacitor

–

Reference clock. REFCLK+ and REFCLK–

single-ended, 125-MHz system reference clock, use the REFCLK+ input.

Reference clock. REFCLK+ and REFCLK– 100-MHz system reference clock. For a

single-ended, 125-MHz system reference clock, attach a capacitor from REFCLK– to VSS.

of 14,532-Ω is connected between REF0_PCIE and REF1_PCIE terminals. To eliminate the need for a custom resistor, two series resistors are recommended: a 14.3-kΩ, 1% resistor and a 232-Ω, 1% resistor.

High-speed receive pair. RXP and RXN comprise Express lane supported.

High-speed transmit pair. TXP and TXN comprise Express lane supported.

Wake is an active low signal that is driven low to reactivate the PCI Express link hierarchy’s main power rails and reference clocks.

Note: Since WAKE is an open-drain output buffer, a system side pullup resistor is required.

Table 2-5. PCI System Terminals

SIGNAL DESCRIPTION

AD31 N05 N05 44 I/O PCI PCIR PCI address data lines AD30 N04 L05 43 Bus AD29 L05 M05 42 AD28 M05 N04 41 AD27 N03 N03 40 AD26 M04 L04 39 AD25 N02 M04 38 AD24 M03 N02 37 AD23 L04 L03 35 AD22 M02 M02 34 AD21 L03 N01 32 AD20 M01 L02 31 AD19 L02 K02 30 AD18 L01 M01 29 AD17 K02 K03 28 AD16 K01 L01 26 AD15 E01 F02 12 AD14 E02 E03 11 AD13 E03 E01 10 AD12 D01 E02 9 AD11 D02 D01 8 AD10 C01 C01 6 AD9 C02 D02 5 AD8 D03 B01 4 AD7 C03 A01 1 AD6 B02 B03 128 AD5 C04 C03 127 AD4 A02 A02 125 AD3 B03 A03 124 AD2 B04 C04 123 AD1 A03 C05 122 AD0 C05 B04 121

ZGU ZAJ PNP I/O CELL CLAMP EXTERNAL

BALL # BALL # PIN # TYPE TYPE RAIL PARTS

–

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Table 2-5. PCI System Terminals (continued)

SIGNAL DESCRIPTION

C/BE[3] N01 M03 36 I/O PCI PCIR PCI command byte enables C/BE[2] J03 K01 25 Bus C/BE[1] F02 F03 14 C/BE[0] B01 C02 3

CLK F03 F01 13 I PCI PCIR PCI clock input. This is the clock input

CLKOUT0 B05 B05 120 O PCI PCIR PCI clock outputs. These clock outputs CLKOUT1 B06 B06 117 Bus are used to clock the PCI bus. If the CLKOUT2 A07 B07 114 bridge PCI bus clock outputs are used, CLKOUT3 B07 A07 112 – then CLKOUT6 must be connected to CLKOUT4 A09 A08 107 the CLK input. CLKOUT5 A10 A10 104 CLKOUT6 B11 C10 99

DEVSEL H02 H02 20 I/O PCI PCIR Pullup PCI device select

FRAME J02 J01 24 I/O PCI PCIR Pullup PCI frame

GNT5 B10 B11 101 O PCI PCIR PCI grant outputs. These signals are GNT4 A11 B10 103 Bus used for arbitration when the PCI bus GNT3 B09 B09 106 is the secondary bus and an external GNT2 B08 B08 109 arbiter is not used. GNT0 is used as GNT1 C06 A06 115 the REQ for the bridge when an GNT0 A05 A05 118 external arbiter is used.

INTA M06 N06 47 I PCI PCIR PCI interrupts A–D. These signals are INTB N06 L06 48 Bus interrupt inputs to the bridge on the INTC M07 M07 49 secondary PCI bus. INTD L07 N07 50

IRDY J01 H03 23 I/O PCI PCIR Pullup PCI initiator ready

LOCK M08 N08 54 I/O PCI PCIR This terminal functions as PCI LOCK

M66EN L06 M06 45 I PCI PCIR 66-MHz mode enable

PAR F01 G01 15 I/O PCI PCIR PCI bus parity

PERR G02 G03 17 I/O PCI PCIR Pullup PCI parity error

PME L12 M12 67 I LV V

ZGU ZAJ PNP I/O CELL CLAMP EXTERNAL

BALL # BALL # PIN # TYPE TYPE RAIL PARTS

–

Bus to the PCI bus core.

Bus resistor per

Bus when bit 12 (LOCK_EN) is set in the

Bus

Bus resistor per

CMOS

DD_33_

COMBIO

–

PCI spec

–

Pullup

resistor per

PCI spec

Pullup

resistor per

PCI spec

Pullup PCLK66_SEL is low then the

resistor per frequency will be 25 MHz.

PCI spec

–

PCI spec

Pullup

resistor per

PCI spec

general control register (see

Section 4.65).

Note: In lock mode, an external pullup resistor is required to prevent the LOCK signal from floating.

0 = Secondary PCI bus and clock outputs operate at 33 MHz. If

1 = Secondary PCI bus and clock outputs operate at 66 MHz. If PCLK66_SEL is low then the frequency will be 50 MHz.

Pullup resistor per PCI spec PCI power management event. This terminal may be used to detect PME events from a PCI device on the secondary bus.

Note: The PME input buffer has hysteresis.

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Table 2-5. PCI System Terminals (continued)

SIGNAL DESCRIPTION

REQ5 A12 C09 102 I PCI PCIR PCI request inputs. These signals are REQ4 C09 A09 105 Bus If unused, a used for arbitration on the secondary REQ3 C08 C08 108 weak pullup PCI bus when an external arbiter is not REQ2 A08 C07 110 resistor per used. REQ0 is used as the GNT for REQ1 A06 C06 116 PCI spec the bridge when an external arbiter is REQ0 A04 A04 119 used.

PRST N07 L07 51 O PCI PCIR PCI reset. This terminal is an output to

SERR G03 G02 16 I/O PCI PCIR Pullup PCI system error

STOP G01 H01 18 I/O PCI PCIR Pullup PCI stop

TRDY H01 J02 22 I/O PCI PCIR Pullup PCI target ready

ZGU ZAJ PNP I/O CELL CLAMP EXTERNAL

BALL # BALL # PIN # TYPE TYPE RAIL PARTS

Bus the secondary PCI bus.

–

Bus resistor per

PCI spec

Bus resistor per

PCI spec

Bus resistor per

PCI spec

Table 2-6. JTAG Terminals

SIGNAL DESCRIPTION

JTAG_TCK M12 N12 65 I LV V

JTAG_TDI N12 L10 63 I LV V

JTAG_TDO M11 N11 61 O LV V

JTAG_TMS L10 L11 64 I LV V

ZGU ZAJ PNP I/O CELL CLAMP EXTERNAL

BALL # BALL # PIN # TYPE TYPE RAIL PARTS

CMOS provides the clock for the internal TAP

DD_33

Optional pullup

resistor

CMOS instructions and data are received on

DD_33

Optional pullup Note: This terminal has an internal

resistor active pullup resistor. The pullup is

CMOS serial output for test instructions and

DD_33

–

CMOS received at JTAG_TMS is decoded by

DD_33

Optional pullup

resistor

JTAG test clock input. This signal controller.

Note: This terminal has an internal active pullup resistor. The pullup is active at all times.

Note: This terminal should be tied to ground or pulled low if JTAG is not required.

JTAG test data input. Serial test this terminal.

active at all times. Note: This terminal can be left

unconnected if JTAG is not required. JTAG test data output. This terminal the

data. Note: This terminal can be left

unconnected if JTAG is not required. JTAG test mode select. The signal

the internal TAP controller to control test operations.

Note: This terminal has an internal active pullup resistor. The pullup is active at all times.

Note: This terminal can be left unconnected if JTAG is not required.

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Table 2-6. JTAG Terminals (continued)

SIGNAL DESCRIPTION

JTAG_TRST L09 L09 60 I LV V

ZGU ZAJ PNP I/O CELL CLAMP EXTERNAL

BALL # BALL # PIN # TYPE TYPE RAIL PARTS

CMOS Optional for asynchronous initialization

DD_33

Optional pullup

resistor

JTAG test reset. This terminal provides of the TAP controller.

Note: This terminal has an internal active pullup resistor. The pullup is active at all times.

Note: This terminal should be tied to ground or pulled low if JTAG is not required.

Table 2-7. Miscellaneous Terminals

SIGNAL DESCRIPTION

CLKRUN_E A13 C11 96 I LV V N CMOS

EXT_ARB_ C10 A12 97 I LV V EN CMOS

GPIO0 // N09 N09 55 I/O LV V CLKRUN CMOS

GPIO1 // M09 M09 56 I/O LV V PWR_OVR CMOS D

GPIO2 N10 N10 57 I/O LV V

ZGU ZAJ PNP I/O CELL CLAMP EXTERNAL

BALL # BALL # PIN # TYPE TYPE RAIL PARTS

DD_33

Optional

pullup

resistor

DD_33

Optional

pullup

resistor

DD_33

Optional

pullup

resistor

DD_33

–

CMOS

DD_33

–

Clock run enable 0 = Clock run support disabled 1 = Clock run support enabled Note: The CLKRUN_EN input buffer has an

internal active pulldown. This pulldown is active at all times.

External arbiter enable 0 = Internal arbiter enabled 1 = External arbiter enabled Note: The EXT_ARB_EN input buffer has an

internal active pulldown. This pulldown is active at all times.

General-purpose I/O 0/clock run. This terminal functions as a GPIO controlled by bit 0 (GPIO0_DIR) in the GPIO control register (see

Section 4.59) or the clock run terminal. This

terminal is used as clock run input when the bridge is placed in clock run mode.

Note: In clock run mode, an external pullup resistor is required to prevent the CLKRUN signal from floating.

Note: This terminal has an internal active pullup resistor. The pullup is only active when reset is asserted or when the GPIO is configured as an input.

General-purpose I/O 1/power override. This terminal functions as a GPIO controlled by bit 1 (GPIO1_DIR) in the GPIO control register (see

Section 4.59) or the power override output

terminal. GPIO1 becomes PWR_OVRD when bits 22:20 (POWER_OVRD) in the general control register are set to 001b or 011b (see

Section 4.65).

Note: This terminal has an internal active pullup resistor. The pullup is only active when reset is asserted or when the GPIO is configured as an input.

General-purpose I/O 2. This terminal functions as a GPIO controlled by bit 2 (GPIO2_DIR) in the GPIO control register (see Section 4.59).

Note: This terminal has an internal active pullup resistor. The pullup is only active when reset is asserted or when the GPIO is configured as an input.

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Table 2-7. Miscellaneous Terminals (continued)

SIGNAL DESCRIPTION

GPIO3 // N11 L08 58 I/O LV V SDA CMOS

GPIO4 // M10 M10 59 I/O LV V SCL CMOS

GRST N13 M11 66 I LV V

PCLK66_SE B12 A11 98 I LV V L CMOS

SERIRQ N08 M08 52 I/O PCI Bus PCIR

VREG_PD3 D12 E11 90 I LV V 3 CMOS

ZGU ZAJ PNP I/O CELL CLAMP EXTERNAL

BALL # BALL # PIN # TYPE TYPE RAIL PARTS

DD_33

Optional set in the Serial Bus Control and Status

pullup Register (see Section 4.58). If no pullup is

resistor detected then this terminal functions as GPIO3.

DD_33

Optional

pullup

resistor

CMOS

DD_33

_COMBIO

–

DD_33

Optional

pulldown

resistor

Pullup or pulldown

resistor

DD_33

_COMBIO

Pulldown terminal should always be tied directly to

resistor ground or an optional pulldown resistor can be

GPIO3 or serial-bus data. This terminal functions as serial-bus data if a pullup resistor is detected on SCL or when the SBDETECT bit is

Note: In serial-bus mode, an external pullup resistor is required to prevent the SDA signal from floating.

GPIO4 or serial-bus clock. This terminal functions as serial-bus clock if a pullup resistor is detected on SCL or when the SBDETECT bit is set in the Serial Bus Control and Status Register (see Section 4.58). If no pullup is detected then this terminal functions as GPIO4.

Note: In serial-bus mode, an external pullup resistor is required to prevent the SCL signal from floating.

Note: This terminal has an internal active pullup resistor. The pullup is only active when reset is asserted or when the GPIO is configured as an input.

Global reset input. Asynchronously resets all logic in device, including sticky bits and power management state machines.

Note: The GRST input buffer has both hysteresis and an internal active pullup. The pullup is active at all times.

PCI clock select. This terminal determines the default PCI clock frequency driven out the CLKOUTx terminals.

0 = 50 MHz PCI Clock 1 = 66 MHz PCI Clock Note: This terminal has an internal active pullup

resistor. This pullup is active at all times. Note: M66EN terminal also has an affect of PCI

clock frequency.

Serial IRQ interface. This terminal functions as a serial IRQ interface if a pullup is detected when PERST is deasserted. If a pulldown is detected, then the serial IRQ interface is disabled.

3.3-V voltage regulator powerdown. This

used.

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PCI Express

Transmitter

PCI Express

Receiver

PCI Bus Interface

Configuration and

Memory Register

GPIO

Serial

EEPROM

Serial

IRQ

Reset

Controller

Clock

Generator

Power Mgmt

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3 Feature/Protocol Descriptions

This chapter provides a high-level overview of all significant device features. Figure 3-1 shows a simplified block diagram of the basic architecture of the PCI-Express to PCI Bridge. The top of the diagram is the PCI Express interface and the PCI bus interface is located at the bottom of the diagram.

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Figure 3-1. XIO2001 Block Diagram

3.1 Power-Up/-Down Sequencing

The bridge contains both 1.5-V and 3.3-V power terminals. The following power-up and power-down sequences describe how power is applied to these terminals.

In addition, the bridge has three resets: PERST, GRST and an internal power-on reset. These resets are fully described in Section 3.2. The following power-up and power-down sequences describe how PERST is applied to the bridge.

The application of the PCI Express reference clock (REFCLK) is important to the power-up/-down sequence and is included in the following power-up and power-down descriptions.

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V and

DD_15

DDA_15

REFCLK

PERST

100 ms

V and

DD_33

DDA_33

PCIR

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3.1.1 Power-Up Sequence

1. Assert PERST to the device.

2. Apply 1.5-V and 3.3-V voltages.

3. Apply PCIR clamp voltage.

4. Apply a stable PCI Express reference clock.

5. To meet PCI Express specification requirements, PERST cannot be deasserted until the following two delay requirements are satisfied:

– Wait a minimum of 100 ms after applying a stable PCI Express reference clock. The 100-ms limit

satisfies the requirement for stable device clocks by the deassertion of PERST.

– Wait a minimum of 100 ms after applying power. The 100-ms limit satisfies the requirement for

stable power by the deassertion of PERST.

See the power-up sequencing diagram in Figure 3-2.

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Figure 3-2. Power-Up Sequence

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V and

DD_15

DDA_15

V and

DD_33

DDA_33

PCIR

REFCLK

PERST

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3.1.2 Power-Down Sequence

1. Assert PERST to the device.

2. Remove the reference clock.

3. Remove PCIR clamp voltage.

4. Remove 3.3-V and 1.5-V voltages.

See the power-down sequencing diagram in Figure 3-3. If the V after a system shutdown, then the bridge power-down sequence is exactly the same as shown in

Figure 3-3.

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terminal is to remain powered

Figure 3-3. Power-Down Sequence

3.2 Bridge Reset Features

There are five bridge reset options that include internally-generated power-on reset, resets generated by asserting input terminals, and software-initiated resets that are controlled by sending a PCI Express hot reset or setting a configuration register bit. Table 3-1 identifies these reset sources and describes how the bridge responds to each reset.

Table 3-1. XIO2001 Reset Options

RESET XIO2001 FEATURE RESET RESPONSE

OPTION

Bridge During a power-on cycle, the bridge asserts an internal reset When the internal power-on reset is asserted, all control internally- and monitors the V generated reaches 90% of the nominal input voltage specification, management state machines are initialized to their default

power-on reset power is considered stable. After stable power, the bridge state.

monitors the PCI Express reference clock (REFCLK) and In addition, the XIO2001 asserts the internal PCI bus reset. waits 10 ms after active clocks are detected. Then, internal power-on reset is deasserted.

Global reset When GRST is asserted low, an internal power-on reset When GRST is asserted low, all control registers, state

input occurs. This reset is asynchronous and functions during machines, sticky register bits, and power management

GRST both normal power states and V

DD_15_COMB

terminal. When this terminal registers, state machines, sticky register bits, and power

power states. state machines are initialized to their default state. In

AUX

addition, the bridge asserts PCI bus reset (PRST). When the rising edge of GRST occurs, the bridge samples the state of all static control inputs and latches the information internally. If an external serial EEPROM is detected, then a download cycle is initiated. Also, the process to configure and initialize the PCI Express link is started. The bridge starts link training within 80 ms after GRST is deasserted.

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Table 3-1. XIO2001 Reset Options (continued)

RESET XIO2001 FEATURE RESET RESPONSE

OPTION

PCI Express This XIO2001 input terminal is used by an upstream PCI When PERST is asserted low, all control register bits that

reset input Express device to generate a PCI Express reset and to are not sticky are reset. Within the configuration register

PERST signal a system power good condition. maps, the sticky bits are indicated by the ┦ symbol. Also,

When PERST is asserted low, the XIO2001 generates an internal PCI Express reset as defined in the PCI Express specification.

When PERST transitions from low to high, a system power In addition, the XIO2001 asserts the internal PCI bus reset. good condition is assumed by the XIO2001.

Note: The system must assert PERST before power is When the rising edge of PERST occurs, the XIO2001 removed, before REFCLK is removed or before REFCLK samples the state of all static control inputs and latches becomes unstable. the information internally. If an external serial EEPROM is

PCI Express The XIO2001 responds to a training control hot reset In the DL_DOWN state, all remaining configuration register

training control received on the PCI Express interface. After a training bits and state machines are reset. All remaining bits

hot reset control hot reset, the PCI Express interface enters the exclude sticky bits and EEPROM loadable bits. All

DL_DOWN state. remaining state machines exclude sticky functionality and

PCI bus reset System software has the ability to assert and deassert the When bit 6 (SRST) in the bridge control register at offset

PRST PRST terminal on the secondary PCI bus interface. This 3Eh (see Section 4.29) is asserted, the bridge asserts the

terminal is the PCI bus reset. PRST terminal. A 0 in the SRST bit deasserts the PRST

all state machines that are not associated with sticky functionality are reset.

detected, then a download cycle is initiated. Also, the process to configure and initialize the PCI Express link is started. The XIO2001 starts link training within 80 ms after PERST is deasserted.

EEPROM functionality. Within the configuration register maps, the sticky bits are

indicated by the ┦ symbol and the EEPROM loadable bits are indicated by the † symbol.

In addition, the XIO2001 asserts the internal PCI bus reset.

terminal.

3.3 PCI Express Interface

3.3.1 External Reference Clock

The bridge requires either a differential, 100-MHz common clock reference or a single-ended, 125-MHz clock reference. The selected clock reference must meet all PCI Express Electrical Specification requirements for frequency tolerance, spread spectrum clocking, and signal electrical characteristics. Spread Spectrum is an optional feature of the PCI Express Electrical Specification that is supported by this bridge.

If the REFCLK125_SEL input is connected to VSS, then a differential, 100-MHz common clock reference is expected by the XIO2001. If the REFCLK125_SEL terminal is connected to V 125-MHz clock reference is expected by the bridge

When the single-ended, 125-MHz clock reference option is enabled, the single-ended clock signal is connected to the REFCLK+ terminal. The REFCLK– terminal is connected to one side of an external capacitor with the other side of the capacitor connected to VSS.

When using a single-ended reference clock, care must be taken to ensure interoperability from a system jitter standpoint. The PCI Express Base Specification does not ensure interoperability when using a differential reference clock commonly used in PC applications along with a single-ended clock in a non-common clock architecture. System jitter budgets will have to be verified to ensure interoperability. See the PCI Express Jitter and BER White Paper from the PCI-SIG.

, then a single-ended,

DD_33

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3.3.2 Beacon

The bridge supports the PCI Express in-band beacon feature. Beacon is driven on the upstream PCI Express link by the bridge to request the reapplication of main power when in the L2 link state. To enable the beacon feature, bit 10 (BEACON_ENABLE) in the general control register at offset D4h is asserted. See Section 4.65, General Control Register, for details.

If the bridge is in the L2 link state and beacon is enabled, when a secondary PCI bus device asserts PME, then the bridge outputs the beacon signal on the upstream PCI Express link. The beacon signal frequency is approximately 500 kHz ± 50% with a differential peak-to-peak amplitude of 500 mV and no de-emphasis. Once the beacon is activated, the bridge continues to send the beacon signal until main power is restored as indicated by PERST going inactive. At this time, the beacon signal is deactivated.

3.3.3 Wake

The bridge supports the PCI Express sideband WAKE feature. WAKE is an active low signal driven by the bridge to request the reapplication of main power when in the L2 link state. Since WAKE is an open-collector output, a system-side pullup resistor is required to prevent the signal from floating.

When the bridge is in the L2 link state and PME is received from a device on the secondary PCI bus, the WAKE signal is asserted low as a wakeup mechanism. Once WAKE is asserted, the bridge drives the signal low until main power is restored as indicated by PERST going inactive. At this time, WAKE is deasserted.

3.3.4 Initial Flow Control Credits

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The bridge flow control credits are initialized using the rules defined in the PCI Express Base Specification. Table 3-2 identifies the initial flow control credit advertisement for the bridge.

Table 3-2. Initial Flow Control Credit Advertisements

CREDIT TYPE INITIAL ADVERTISEMENT

Posted request headers (PH) 8

Posted request data (PD) 128

Non-posted header (NPH) 4

Non-posted data (NPD) 4

Completion header (CPLH) 0 (infinite)

Completion data (CPLD) 0 (infinite)

3.3.5 PCI Express Message Transactions

PCI Express messages are both initiated and received by the bridge. Table 3-3 outlines message support within the bridge.

Table 3-3. Messages Supported by the Bridge

MESSAGE SUPPORTED BRIDGE ACTION

Assert_INTx Yes Transmitted upstream Deassert_INTx Yes Transmitted upstream PM_Active_State_Nak Yes Received and processed PM_PME Yes Transmitted upstream PME_Turn_Off Yes Received and processed PME_TO_Ack Yes Transmitted upstream ERR_COR Yes Transmitted upstream ERR_NONFATAL Yes Transmitted upstream

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Table 3-3. Messages Supported by the Bridge (continued)

MESSAGE SUPPORTED BRIDGE ACTION

ERR_FATAL Yes Transmitted upstream Set_Slot_Power_Limit Yes Received and processed Unlock No Discarded Hot plug messages No Discarded Advanced switching messages No Discarded Vendor defined type 0 No Unsupported request Vendor defined type 1 No Discarded

All supported message transactions are processed per the PCI Express Base Specification.

3.4 PCI Bus Interface

3.4.1 I/O Characteristics

Figure 3-4 shows a 3-state bi-directional buffer that represents the I/O cell design for the PCI bus. Section 7.7, Electrical Characteristics over Recommended Operating Conditions, provides the electrical

characteristics of the PCI bus I/O cell.

NOTE

The PCI bus interface on the bridge meets the ac specifications of the PCI Local Bus Specification. Additionally, PCI bus terminals (input or I/O) must be held high or low to

prevent them from floating.

Figure 3-4. 3-State Bidirectional Buffer

3.4.2 Clamping Voltage

In the bridge, the PCI bus I/O drivers are powered from the V tolerant to input signals with 5-V peak-to-peak amplitudes.

For PCI bus interfaces operating at 50MHz or 66 MHz, all devices are required to output only 3.3-V peak-to-peak signal amplitudes. For PCI bus interfaces operating at 25-MHz or 33-MHz, devices may output either 3.3-V or 5-V peak-to-peak signal amplitudes. The bridge accommodates both signal amplitudes.

Each PCI bus I/O driver cell has a clamping diode connected to the internal V the cell from excessive input voltage. The internal V

rail is connected to two PCIR terminals. If the PCI

CCP

signaling is 3.3-V, then PCIR terminals are connected to a 3.3-V power supply via a 1kΩ resistor. If the PCI signaling is 5-V, then the PCIR terminals are connected to a 5-V power supply via a 1kΩ resistor.

The PCI bus signals attached to the V

clamping voltage are identified as follows

CCP

• Table 2-5, PCI System Terminals, all terminal names except for PME

• Table 2-7, Miscellaneous Terminals, the terminal name SERIRQ.

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power rail. Plus, the I/O driver cell is

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3.4.3 PCI Bus Clock Run

The bridge supports the clock run protocol as specified in the PCI Mobile Design Guide. When the clock run protocol is enabled, the bridge assumes the role of the central resource master.

To enable the clock run function, terminal CLKRUN_EN is asserted high. Then, terminal GPIO0 is enabled as the CLKRUN signal. An external pullup resistor must be provided to prevent the CLKRUN signal from floating To verify the operational status of the PCI bus clocks, bit 0 (SEC_CLK_STATUS) in the clock run status register at offset DAh (see Section 4.68) is read.

Since the bridge has several unique features associated with the PCI bus interface, the system designer must consider the following interdependencies between these features and the CLKRUN feature:

1. If the system designer chooses to generate the PCI bus clock externally, then the CLKRUN mode of the bridge must be disabled. The central resource function within the bridge only operates as a CLKRUN master and does not support the CLKRUN slave mode.

2. If the central resource function has stopped the PCI bus clocks, then the bridge still detects INTx state changes and will generate and send PCI Express messages upstream.

3. If the serial IRQ interface is enabled and the central resource function has stopped the PCI bus clocks, then any PCI bus device that needs to report an IRQ interrupt asserts CLKRUN to start the bus clocks.

4. When a PCI bus device asserts CLKRUN, the central resource function turns on PCI bus clocks for a minimum of 512 cycles.

5. If the serial IRQ function detects an IRQ interrupt, then the central resource function keeps the PCI bus clocks running until the IRQ interrupt is cleared by software.

6. If the central resource function has stopped the PCI bus clocks and the bridge receives a downstream transaction that is forwarded to the PCI bus interface, then the bridge asserts CLKRUN to start the bus clocks.

7. The central resource function is reset by PCI bus reset (PRST) assuring that clocks are present during PCI bus resets.

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3.4.4 PCI Bus External Arbiter

The bridge supports an external arbiter for the PCI bus. Terminal (EXT_ARB_EN), when asserted high, enables the use of an external arbiter.

When an external arbiter is enabled, GNT0 is connected to the external arbiter as the REQ for the bridge. Likewise, REQ0 is connected to the external arbiter as the GNT for the bridge.

3.4.5 MSI Messages Generated from the Serial IRQ Interface

When properly configured, the bridge converts PCI bus serial IRQ interrupts into PCI Express message signaled interrupts (MSI). classic PCI configuration register space is provided to enable this feature. The following list identifies the involved configuration registers:

1. Command register at offset 04h, bit 2 (MASTER_ENB) is asserted (see Table 4-2).

2. MSI message control register at offset 52h, bits 0 (MSI_EN) and 6:4 (MM_EN) enable single and multiple MSI messages, respectively (see Section 4.42).

3. MSI message address register at offsets 54h and 58h specifies the message memory address. A nonzero address value in offset 58h initiates 64-bit addressing (see Section 4.37 and Section 4.44).

4. MSI message data register at offset 5Ch specifies the system interrupt message (see Section 4.45).

5. Serial IRQ mode control register at offset E0h specifies the serial IRQ bus format (see Section 4.72).

6. Serial IRQ edge control register at offset E2h selects either level or edge mode interrupts (see

Section 4.73).

7. Serial IRQ status register at offset E4h reports level mode interrupt status (see Section 4.74).

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A PCI Express MSI is generated based on the settings in the serial IRQ edge control register. If the system is configured for edge mode, then an MSI message is sent when the corresponding serial IRQ interface sample phase transitions from low to high. If the system is configured for level mode, then an MSI message is sent when the corresponding IRQ status bit in the serial IRQ status register changes from low to high.

The bridge has a dedicated SERIRQ terminal for all PCI bus devices that support serialized interrupts. This SERIRQ interface is synchronous to the PCI bus clock input (CLK) frequency. The bridge always generates a 17-phase serial IRQ stream. Internally, the bridge detects only 16 IRQ interrupts, IRQ0 frame through IRQ15 frame. The IOCHCK frame is not monitored by the serial IRQ state machine and never generates an IRQ interrupt or MSI message.

The multiple message enable (MM_EN) field determines the number of unique MSI messages that are sent upstream on the PCI Express link. From 1 message to 16 messages, in powers of 2, are selectable. If fewer than 16 messages are selected, then the mapping from IRQ interrupts to MSI messages is aliased. Table 3-4 illustrates the IRQ interrupt to MSI message mapping based on the number of enabling messages.

Table 3-4. IRQ Interrupt to MSI Message Mapping

IRQ 1 MESSAGE 2 MESSAGES 4 MESSAGES 16 MESSAGES

INTERRUPT ENABLED ENABLED ENABLED ENABLED

IRQ0 MSI MSG #0 MSI MSG #0 MSI MSG #0 MSI MSG #0 MSI MSG #0 IRQ1 MSI MSG #0 MSI MSG #1 MSI MSG #1 MSI MSG #1 MSI MSG #1 IRQ2 MSI MSG #0 MSI MSG #0 MSI MSG #2 MSI MSG #2 MSI MSG #2 IRQ3 MSI MSG #0 MSI MSG #1 MSI MSG #3 MSI MSG #3 MSI MSG #3 IRQ4 MSI MSG #0 MSI MSG #0 MSI MSG #0 MSI MSG #4 MSI MSG #4 IRQ5 MSI MSG #0 MSI MSG #1 MSI MSG #1 MSI MSG #5 MSI MSG #5 IRQ6 MSI MSG #0 MSI MSG #0 MSI MSG #2 MSI MSG #6 MSI MSG #6 IRQ7 MSI MSG #0 MSI MSG #1 MSI MSG #3 MSI MSG #7 MSI MSG #7 IRQ8 MSI MSG #0 MSI MSG #0 MSI MSG #0 MSI MSG #0 MSI MSG #8

IRQ9 MSI MSG #0 MSI MSG #1 MSI MSG #1 MSI MSG #1 MSI MSG #9 IRQ10 MSI MSG #0 MSI MSG #0 MSI MSG #2 MSI MSG #2 MSI MSG #10 IRQ11 MSI MSG #0 MSI MSG #1 MSI MSG #3 MSI MSG #3 MSI MSG #11 IRQ12 MSI MSG #0 MSI MSG #0 MSI MSG #0 MSI MSG #4 MSI MSG #12 IRQ13 MSI MSG #0 MSI MSG #1 MSI MSG #1 MSI MSG #5 MSI MSG #13 IRQ14 MSI MSG #0 MSI MSG #0 MSI MSG #2 MSI MSG #6 MSI MSG #14 IRQ15 MSI MSG #0 MSI MSG #1 MSI MSG #3 MSI MSG #7 MSI MSG #15

8 MESSAGES ENABLED

The MSI message format is compatible with the PCI Express request header format for 32-bit and 64-bit memory write transactions. The system message and message number fields are included in bytes 0 and 1 of the data payload.

3.4.6 PCI Bus Clocks

The bridge has seven PCI bus clock outputs and one PCI bus clock input. Up to six PCI bus devices are supported by the bridge.

Terminal PCLK66_SEL selects the default operating frequency. This signal works in conjunction with terminal M66EN to determine the final output frequency. When PCLK66_SEL is asserted high then the clock frequency will be either 66-MHz or 33-MHz depending on the state of M66EN. When M66EN is asserted high then the clock frequency will be 66-MHz, when M66EN is de-asserted the clock frequency

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will be 33-MHz. When PCLK66_SEL is de-asserted then the clock frequency will be either 50-MHz or 25-MHz. When M66EN is asserted high then the clock frequency will be 50-MHz, when M66EN is de-asserted the clock frequency will be 25-MHz. The clock control register at offset D8h provides 7 control bits to individually enable or disable each PCI bus clock output (see Section 4.66). The register default is enabled for all 7 outputs.

The PCI bus clock (CLK) input provides the clock to the internal PCI bus core and serial IRQ core. When the internal PCI bus clock source is selected, PCI bus clock output 6 (CLKOUT6) is connected to the PCI bus clock input (CLK). When an external PCI bus clock source is selected, the external clock source is connected to the PCI bus clock input (CLK). For external clock mode, all seven CLKOUT6:0 terminals must be disabled using the clock control register at offset D8h (see Section 4.66).

3.5 PCI Port Arbitration

The internal PCI port arbitration logic supports up to six external PCI bus devices plus the bridge. This bridge supports a classic PCI arbiter.

3.5.1 Classic PCI Arbiter

The classic PCI arbiter is configured through the classic PCI configuration space at offset DCh. Table 3-5 identifies and describes the registers associated with classic PCI arbitration mode.

Table 3-5. Classic PCI Arbiter Registers

PCI OFFSET REGISTER NAME DESCRIPTION

Classic PCI configuration Arbiter control

Classic PCI configuration Arbiter request mask status if a PCI device does not respond within 16 PCI bus clocks. Bit 6

Classic PCI configuration Arbiter time-out status When bit 7 (ARB_TIMEOUT) in the arbiter request mask register is asserted,

Contains a two-tier priority scheme for the bridge and six PCI bus devices. The bridge defaults to the high priority tier. The six PCI bus devices default to the low priority tier. A bus parking control bit (bit 7, PARK) is provided.

Six mask bits provide individual control to block each PCI Bus REQ input. Bit 7 (ARB_TIMEOUT) in the arbiter request mask register enables generating timeout

REQ if the device does not respond after GNT is issued. The AUTO_MASK bit is cleared to disable any automatically generated mask.

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3.6 Configuration Register Translation

PCI Express configuration register transactions received by the bridge are decoded based on the transaction’s destination ID. These configuration transactions can be broken into three subcategories: type 0 transactions, type 1 transactions that target the secondary bus, and type 1 transactions that target a downstream bus other than the secondary bus.

PCI Express type 0 configuration register transactions always target the configuration space and are never passed on to the secondary interface.

Type 1 configuration register transactions that target a device on the secondary bus are converted to type 0 configuration register transactions on the PCI bus. Figure 3-5 shows the address phase of a type 0 configuration transaction on the PCI bus as defined by the PCI specification.

Figure 3-5. Type 0 Configuration Transaction Address Phase Encoding

In addition, the bridge converts the destination ID device number to one of the AD[31:16] lines as the IDSEL signal. The implemented IDSEL signal mapping is shown in Table 3-6.

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+ 101 hidden pages

TEXAS INSTRUMENTS XIO2001 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

1 Introduction

1.1 Features

2 Overview

2.1 Description

2.2 Related Documents

2.3 Documents Conventions

2.4 Document History

2.5 Terminal Assignments

2.6 Terminal Descriptions

3 Feature/Protocol Descriptions

3.1 Power-Up/-Down Sequencing

3.1.1 Power-Up Sequence

3.1.2 Power-Down Sequence

3.2 Bridge Reset Features

3.3 PCI Express Interface

3.3.1 External Reference Clock

3.3.2 Beacon

3.3.3 Wake

3.3.4 Initial Flow Control Credits

3.3.5 PCI Express Message Transactions

3.4 PCI Bus Interface

3.4.1 I/O Characteristics

3.4.2 Clamping Voltage

3.4.3 PCI Bus Clock Run

3.4.4 PCI Bus External Arbiter

3.4.5 MSI Messages Generated from the Serial IRQ Interface

3.4.6 PCI Bus Clocks

3.5 PCI Port Arbitration

3.5.1 Classic PCI Arbiter

3.6 Configuration Register Translation