TEXAS INSTRUMENTS XIO1100 Technical data
XIO1100
Data Manual
Literature Number: SLLS690B
June 2006
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Contents
Contents
Section Page
1 XIO1100 Features 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Description 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Ordering Information 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Functional Description 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Power Management 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.1 P0 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.2 P0s 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3.3 P1 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Clock 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Reset 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 Receiver Detection 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 Receiver Clock Tolerance Compensation 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8 Error Detection 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8.1 8B/10B Decode Error 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8.2 Elastic Buffer Overflow Error 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8.3 Elastic Buffer Underflow Error 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8.4 Disparity Error 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.9 Loopback 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.10 Electrical Idle 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.11 Polarity Inversion 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.12 Setting Negative Parity 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.13 Terminal Assignments 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.14 Terminal Descriptions 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Electrical Characteristics 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Absolute Maximum Ratings† 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Recommended Operating Conditions 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 PCI Express Differential Transmitter Output Ranges 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 PCI Express Differential Receiver Input Ranges 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Express Differential Reference Clock Input Ranges 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Electrical Characteristics Over Recommended Operating Conditions (VDD_IO) 19. . . . . . . . . . .
3.7 Implementation−Specific Timing 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Timing Diagrams 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Application Information 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.1 Component Connection 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 XIO1100 Component Placement 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 Power Supply Filtering Recommendations 25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.4 PCIe Layout Guidelines 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5 PIPE Interface Layout Guidelines 28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Mechanical Data 29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
i
List of Figures
Figure Page
Figure 2−1. XIO1100 Functional Block Diagram 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4−1. TI−PIPE Input Timing 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4−2. TI−PIPE Data Output Timing 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4−3. TI−PIPE Output Functional Timing 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 4−4. TI−PIPE Input Functional Timing 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5−1. External Component Connections 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 5−2. Filter Designs 26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ii
List of Tables
Table Page
Table 2−1. Clock Selection 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2−2. RX_STATUS Loopback Detection Code 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2−3. 100-pin GGB Signal Name Sorted by Terminal Number 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2−4. 100-pin GGB Signal Name Sorted Alphabetically 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 2−5. XIO1100 Terminals 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
iii
1 XIO1100 Features
D X1 PCI Expresst Serial Link
− PCI Express 1.1 Compliant
− Selectable Reference Clock (100 MHz,
125 MHz)
− Low-Power Capability
TI and MicroStar BGA are trademarks of Texas Instruments Incorporated
PCI Express is a trademark of PCI−SIG
2 Description
The XIO1100 is a PCI Expresst PHY that is compliant with PCI Express Base Specification Revision 1.1 and
that interfaces the PCI Express Media Access Layer (MAC) to a PCI Express serial link by using a modified
version of the interface described in PHY Interface for the PCI Expresst Architecture (also known as PIPE
interface) by Intel Corporation. This modified version of the PIPE interface is referred to as a TI-PIPE interface
throughout this data manual.
The TI-PIPE interface is a pin-configurable interface that can be configured as either a 16-bit or an 8-bit
interface.
• The 16-bit TI-PIPE interface is a 125 MHz 16-bit parallel interface with a 16-bit output bus (RXDA TA) that
is clocked by the RXCLK output clock and a 16-bit input bus (TXDATA) that is clocked by the TXCLK input
clock. Both buses are clocked using Single Data Rate (SDR) clocking in which the data transitions are
on the rising edge of the associated clock.
• The 8-bit TI-PIPE interface is a 250 MHz 8-bit parallel interface with an 8-bit output bus (RXDATA) that
is clocked by the RXCLK output clock and an 8-bit input bus (TXDATA) that is clocked by the TXCLK input
clock. Both buses are clocked using Double Data Rate (DDR) clocking in which the data transitions are
on both the rising edge and the falling edge of the clock.
Features
D TI-PIPE MAC Interface
− Source-Synchronous TX and RX Ports
− 125 MHz TX/RX Clocks
− Selectable 16-Bit SDR or 8-Bit DDR Mode
D 100-Pin MicroStart BGA Package
D Selectable 1.5−V or 1.8−V LVCMOS Buffers.
The XIO1100 PHY interfaces to a 2.5 Gbps PCI Express serial link with a transmit differential pair (TXP and
TXN) and a receive differential pair (RXP and RXN). Incoming data at the XIO1100 PHY receive differential
pair (RXP and RXN) is forwarded to the MAC on the RXDATA output bus. Data received from the MAC on
the TXDATA input bus is forwarded to the XIO1100 PHY transfer differential pair (TXP and TXN).
The XIO1100 is also responsible for handling the 8B/10B encoding/decoding and scrambling/unscrambling
of the outgoing data. In addition, XIO1100 can recover/interpolate the clock on the receiver side based on the
transitions guaranteed by the use of the 8B/10B mechanism and supply this to the receive side of the data
link layer logic.
In addition to the TI-PIPE interface, the XIO1100 has some TI-proprietary side-band signals that some
customers may wish to use to take advantage of additional XIO1 100 low-power state features (for example,
disabling the PLL during the L1 power state).
2.1 Ordering Information
ORDERING NUMBER VOLTAGE TEMPERATURE PACKAGE
XIO1100 3.3/1.8/1.5 0°C to 70°C 100-terminal GGB
June 2006 SLLS690B
1
Description
2.2 Functional Description
The XIO1100 meets all of the requirements for a PCI−Express PHY as defined by Section 4, Physical Layer
Specifications, of the PCI−SIG document PCI Express Base Specification. The XIO1100 conforms to the
functional behavior described in PHY Interface for the PCI Expresst Architecture by Intel Corporation. There
are only two differences between the XIO1100 TI−PIPE interface and the Intel PIPE interface.
The PIPE interface uses a single SDR clock source to clock both the RXDATA and the TXDA TA. The TI−PIPE
interface uses two source synchronous clocks, RX_CLK and TX_CLK, to clock the RXDATA and TXDATA.
RXDATA uses RX_CLK and TXDATA uses TX_CLK.
In the 8-bit mode, the TI−PIPE interface is a DDR (Double Data Rate) interface. In the 16-bit mode, it is an
SDR (Single Data Rate) interface. The PIPE interface is always an SDR interface.
Figure 2−1 shows a functional block diagram of the XIO1100.
REFCLK/REFCLK−
PLL
TX_DATA 16/8
TX_CLK
TX_DATAK[1:0]
STATUS
COMMAND
RX_CLK
RX_DATAK[1:0]
2.3 Power Management
The three power states are:
TXP/TXN
TX BLOCK
RXP/RXNRX_DATA 16/8
RX BLOCK
Figure 2−1. XIO1100 Functional Block Diagram
• P0
• P0s
• P1
2
June 2006SLLS690B
2.3.1 P0
P0 is the normal operation state for the XIO1100. The POWERDOWN[1:0] input signals define which of the
three power states that an XIO1 10 i s in at any given time. In states P0, P0s, and P1, the XIO1100 is required
to keep P_CLK operational. For all state transitions between these three states, the XIO1100 indicates
successful transition into the designated power state by a single cycle assertion of PHY_STATUS. For all
power state transitions, the MAC must not begin any operational sequence or more power state transitions
until the XIO1100 has indicated that the initial state transition is finished. P2 state and beacon are not
supported.
In the P0 state, all internal clocks in the XIO1100 are operational. P0 is the only state where the XIO1100
transmits and receives PCI Express signaling. P0 is the appropriate PHY power management state for most
states in the Link T raining and Status State Machine (LTSSM). Exceptions are listed as follows for each lower
power XIO1100 state.
2.3.2 P0s
In the P0s state, RX_CLK output stays operational. The MAC moves the XIO1100 to this state only when the
transmit channel is idle. P0s state is used when the transmitter is in state Tx_L0s.Idle. If the receiver detects
an electrical idle while the XIO1100 is in either P0 or P0s power states, the receiver portion of the XIO1100
takes appropriate power saving measures.
2.3.3 P1
In the P1 state, selected internal clocks in the XIO1100 will be turned off. RX_CLK output will stay operational.
The MAC moves the XIO1100 to this state only when both transmit and receive channels are idle. The
XIO1100 does not indicate successful entry into P1 (by asserting PhyStatus) until RX_CLK is stable and the
operating dc common mode voltage is stable and within specification (in accordance with PCI Express Base
Specification). P1 is used for the Disabled state, all Detect states, and L1.Idle state of the Link Training and
Status State Machine (LTSSM). While in P1 state, the optional P1_SLEEP input signal can be used to reduce
even more power consumption by disabling the RX_CLK signal. However, the P1_SLEEP input must not be
asserted when the XIO1100 is in any state other than P1 state, and the XIO1100 must not be transitioned out
of the P1 state as long as P1_SLEEP is asserted.
Description
2.4 Clock
The RX_CLK of XIO1100 is derived from the REFCLK input. A 100 MHz differential clock or a 125 MHz single
ended clock can be used as the source clock. The frequency selection is determined by CLK_SEL. If
CLK_SEL is low during /RESET transitioning from a low state to a high state, the source clock at
REFCLK+/REFCLK− is a 100 MHz differential clock. If CLK_SEL is high during /RESET transitioning from a
low state to a high state, the source clock at REFCLK+ is a 125 MHz single ended clock. In this case, REFCLK−
needs to be tied to VSS.
Table 2−1. Clock Selection
RX_CLK
CLK_SEL = 0 100 MHz differential clock
CLK_SEL = 1 125 MHz single ended clock
2.5 Reset
When the MAC resets the XIO1100 (initial power on), the MAC must hold the XIO1100 in reset until power
and REFCLK to the XIO1100 are stable. The XIO1100 signals that RX_CLK is valid (RX_CLK has been
running at its operational frequency for at least one clock), and the XIO1100 is in the specified power state
by the de−assertion of PhyStatus. While Reset# is asserted, the MAC must have TxDetectRx/Loopback
de−asserted, TxElecIdle asserted, TxCompliance de−asserted, RxPolarity de−asserted, and PowerDown =
P1.
June 2006 SLLS690B
3
Description
2.6 Receiver Detection
While in the P1 power state, XIO1100 can be instructed to perform a receiver detection operation to determine
if there is a receiver at the other end of the link. The MAC requests XIO1100 to do a receiver detect sequence
by asserting TXDETECTRX/LOOPBACK high. Upon completion of the receiver detection operation, the
XIO1100 asserts PHY_ST ATUS high for one RX_CLK cycle. While PHY_STATUS is high, XIO1100 drives the
proper receiver status code onto the RX_STATUS[2:0] signals according to Table 2−2. After the receiver
detection has completed (as signaled by the assertion of PhyStatus), the MAC must de−assert
TxDetectRx/Loopback before initiating another receiver detection or a power state transition.
Table 2−2. RX_STATUS Loopback Detection Code
RX_STATUS[2:0] RECEIVER STATUS
000 Receiver not present
011 Receiver present
NOTE: TX_DET_LOOPBACK must remain asserted until XIO1100 asserts the PHY_STATUS.
2.7 Receiver Clock Tolerance Compensation
The XIO1100 receiver contains an elastic buffer that compensates for differences in frequencies between bit
rates at the two ends of a link. The elastic buffer is capable of holding at least seven symbols to tolerate
worst-case differences (600ppm) in frequency and worst-case intervals between SKP ordered-sets, where
an SKP order-set is a set of symbols transmitted as a group. The first symbol of a SKP ordered-set is a COM
(0xBC) and is followed by three SKP (0x1C) symbols. The purpose of SKP ordered-sets is to allow the
receiving device (in this case, XIO1100) to adjust the data stream that is being received to prevent the elastic
buffer from either overflowing or underflowing due to any differences between the clocking frequencies of the
transmitting device and the receiving device. The XIO1100 monitors the data stream received at the RXP/RXN
differential pair for SKP ordered-sets.
When the XIO1100 detects that an SKP ordered-set is being received, it either adds or removes SKP symbols
from the data stream, depending on the current state of the elastic buffer. If the elastic buffer is in danger of
underflowing, SKP symbols are added to the ordered-set before it is loaded into the buffer. If the elastic buf fer
is in danger of overflowing, SKP symbols are removed from the ordered-set before it is loaded into the buffer.
When the XIO1100 detects a SKP ordered-set, the XIO1100 asserts an Add SKP code (001b) on the
RX_STATUS[2:0] bus in the same RX_CLK cycle that it asserts the COM (0xBC) symbol on the
RX_DATA[15:0] bus, if it is adding a SKP symbol to the data stream. In the case of removing an SKP symbol,
the XIO1100 asserts the Remove SKP code (010b) to the RX_STATUS[2:0] when the COM symbol is
asserted.
2.8 Error Detection
If a detectable receive error occurs, the appropriate error code is asserted on the RX_STATUS[2:0] pins for
one RX_CLK cycle as close as possible to the point in the data stream where the error occurred. There are
four error conditions that can be encoded on the RXSTATUS signals. If more than one error happens to occur
on a received byte (or set of bytes transferred across a 16-bit interface), the errors are signaled with the
following priority:
• 8B/10B decode error
• Elastic buffer overflow
• Elastic buffer underflow
• Disparity error
If an error occurs during a SKP ordered-set, such that the error code and the SKP code occur concurrently,
the error code has priority over the SKP code.
4
June 2006SLLS690B
2.8.1 8B/10B Decode Error
When XIO1100 detects an 8B/10B decode error, it asserts an EDB (0xFE) symbol in the data on the
RX_DATA[15:0] where the bad byte occurred (only the erroneous byte is replaced with the EDB symbol; the
other byte is still valid data). In the same RX_CLK clock cycle that the EDB symbol is asserted on the
RX_DATA[15:0] bus, the 8B/10B decode error code (100b) is asserted on the RX_STATUS[2:0] bus. Since
the 8B/10B decoding error has priority over all other receive error codes, it could mask out a disparity error
occurring on the other byte of data being clocked onto the RX_DATA[15:0] with the EDB symbol.
2.8.2 Elastic Buffer Overflow Error
When the elastic buffer overflows, data is lost during reception. XIO1100 generates an elastic buffer overflow
error when this occurs. The elastic buffer overflow error code (101b) is asserted on the RX_STATUS[2:0] on
the RX_CLK clock cycle that the omitted data would have been asserted. The remaining data asserted on the
RX_DATA[15:0]] bus is still valid data, but the elastic buffer overflow error code on the RX_STATUS[2:0] just
marks a discontinuity point in the data stream being received.
2.8.3 Elastic Buffer Underflow Error
When the elastic buffer underflows, EDB (0xFE) symbols are inserted into the data stream on the
RX_DATA[15:0] bus to fill the holes created by the gaps between valid data. For every RX_CLK clock cycle,
an EDB symbol is asserted on the RX_DATA[15:0] bus, and an elastic buf fer underflow error code (111b) is
asserted on the RX_STATUS[2:0] bus.
2.8.4 Disparity Error
Description
When the XIO1100 detects a disparity error, it asserts a disparity error code (111b) on the RX_STATUS[2:0]
bus in the same RX_CLK clock cycle that it asserts the erroneous data on the RX_DATA[15:0] bus. However,
it is not possible to discern which byte had the disparity error.
2.9 Loopback
The XIO1100 begins a loopback operation when the MAC asserts TX_DET_LOOPBACK while holding
TX_ELECIDLE de−asserted. The XIO1100 stops transmitting data to the TXP/TXN signaling pair from the
TI−PIPE interface and begins transmitting the data received at the RXP/RXN signaling pair on the TXP/TXN
signaling pair. This data is not routed through the 8B/10B coding/encoding paths. While in the loopback
operation, the received data is still sent to the RXDA TA[15:0] bus of the TI−PIPE interface. The data sent to
the RXDA T A[15:0] bus is routed through the 10B/8B decoder. The XIO1100 terminates the loopback operation
and returns to transmitting TXDATA[15:0] over the TXP/TXN signaling pair when the TX_DET_LOOPBACK
signal is de−asserted.
2.10 Electrical Idle
The XIO1100 expects the MAC to issue the required COM (K28.5) symbol and the required number of IDL
symbols (K28.3) on TXDATA[7:0] before asserting the TX_ELECTRICAL signal. The XIO1100 meets the
requirements of the Electrical Requirements of a PCI Express PHY (for these requirements, see Section
4.3.1.9, Electrical Idle, and Table B−2 in Appendix B of PCI Express Base Specification Revision 1.1).
2.11 Polarity Inversion
Polarity inversion can happen in many places in the receive chain, including somewhere in the serial path,
as symbols are placed into the elastic buffer or as symbols are removed from the elastic buffer. The XIO1100
inverts the data received on the RXP/RXN signaling pair when RxPolarity is asserted. The inverted data will
begin showing up on the RXDATA within 20 RX_CLKS of when RxPolarity is asserted.
2.12 Setting Negative Parity
To set the running disparity to negative, TxCompliance is asserted for one clock cycle that matches with the
data that is to be transmitted with negative disparity.
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5
Description
2.13 Terminal Assignments
The XIO1 100 is packaged in a 100-pin GGB BGA package. See Section 6 for GGB-package terminal diagram.
Table 2−3 lists the terminal assignments in terminal-number order with corresponding signal names for the
GGB package.
Table 2−4 lists the terminal assignments arranged in alphanumerical order by signal name with corresponding
terminal numbers for the GGB package.
Table 2−3. 100-pin GGB Signal Name Sorted by Terminal Number
GGB
NUMBER
A3 RX_DATA8 C9 RESERVED G11 VSSA L6 CLK_SEL
A4 RX_DATA9 C10 VSSA G12 TXP L7 VDD_IO
A5 RX_DATA11 C12 RXN G13 TXN L8 VSS
A6 RX_DATA13 C13 RXP H1 TX_DATA13 L9 POWERDOWN1
A7 RX_DATA15 D1 RX_DATA4 H2 TX_DATA14 L10 DDR_EN
A8 RX_DATAK0 D2 RX_DATA5 H3 RX_VALID L12 VDD_15_COMB
A9 RESERVED D3 VSS H11 VDD_33_COMB L13 VDD_33_COM_IO
A10 RESERVED D11 VDDA_33 H12 VDDA_15 M3 TX_DATA6
A11 REFCLK− D12 VSSA H13 VDDA_15 M4 TX_DATA5
B3 RX_ELECIDLE D13 VSSA J1 TX_DATA11 M5 TX_DATA3
B4 RX_DATA10 E1 RX_DATA2 J2 TX_DATA12 M6 TX_DATA1
B5 RX_DATA12 E2 RX_DATA3 J3 VSS M7 TX_DATAK1
B6 RX_DATA14 E3 RX_STATUS0 J11 VSS M8 TX_CLK
B7 RX_DATAK1 E11 VDDA_15 J12 VDDA_33 M9 POWERDOWN0
B8 RX_CLK E12 VSSA J13 VDDA_33 M10 P1_SLEEP
B9 RESERVED E13 VDD_15 K1 TX_DATA9 M11 VREG_PD
B10 RESERVED F1 RX_DATA0 K2 TX_DATA10 N3 TX_DATA7
B11 REFCLK+ F2 RX_DATA1 K3 VDD_IO N4 TX_DATA4
C1 RX_DATA7 F3 VDD_IO K11 VSSA N5 TX_DATA2
C2 RX_DATA6 F11 VDD_15 K12 R0 N6 TX_DATA0
C4 VSS F12 VSS K13 R1 N7 TX_DATAK0
C5 VDD_IO F13 VSSA L1 TX_DATA8 N8 TXCOMPLIANCE
C6 RX_POLARITY G1 RX_STATUS1 L2 VSS N9 TXELECIDLE
C7 VDD_15_CORE G2 TX_DATA15 L4 VDD_15_CORE N10 PHY_STATUS
C8 VSS G3 RX_STATUS2 L5 TXDETECTRX/L
SIGNAL NAME GGB
NUMBER
SIGNAL
NAME
GGB
NUMBER
SIGNAL NAME GGB
NUMBER
N11 RESETN
OOPBACK
SIGNAL NAME
6
June 2006SLLS690B
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