TEXAS INSTRUMENTS VSP3200, VSP3210 Technical data

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VSP3200

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CCD SIGNAL PROCESSOR FOR

SCANNER APPLICATIONS

FEATURES

F INTEGRATED TRIPLE-CORRELATED

DOUBLE SAMPLER

F OPERATION MODE SELECTABLE:

1-Channel, 3-Channel CCD Mode, 8Msps

F PROGRAMMABLE GAIN AMPLIFIER:

0dB to +13dB

F SELECTABLE OUTPUT MODES:

Normal/Demultiplexed

F OFFSET CONTROL RANGE: ±500mV F +3V, +5V Digital Output F LOW POWER: 300mW (typ)

F LQFP-48 SURFACE-MOUNT PACKAGE

VSP3200

VSP3210

DESCRIPTION

The VSP3200 and VSP3210 are complete CCD image processors that operate from single +5V supplies.

This complete image processor includes three Correlated Double Samplers (CDSs) and Programmable Gain Amplifiers (PGAs) to process CCD signals.

The VSP3200 is interface compatible with the VSP3210, which is a 16-bit, one-chip product.

The VSP3210 is pin-to-pin compatible with VSP3100, when in demultiplexed output mode.

The VSP3200 and VSP3210 can be operated from 0°C to +85°C, and are available in LQFP-48 packages.

RINP

AGND

GINP

BINP

Clamp

Register

Offset

R G B

CK1CLP CK2

CDS

10

10-Bit

DAC

CDS

10

10-Bit

DAC

CDS

10

10-Bit

DAC

Configuration

Register

PGA

6

PGA

6

PGA

6

VSP3200

ADCCK

Timing Generator

MUX

Control

Register

Gain

R G B

68

TP0

V

REF

Reference

Circuit

16-Bit

A/D

Converter

Register

Port

CM

REFP REFN

OE V

DRV

Digital Output

Control

16

3

10

B0-B15 (A0-A2, D0-D9)

P/S WRT RD SCLK SD

SPECIFICATIONS

At TA = 25°C, VCC = +5.0V, V otherwise specified.

PARAMETER CONDITIONS MIN TYP MAX UNITS RESOLUTION 16 Bits

CONVERSION CHARACTERISTICS

1-Channel CCD Mode, Max 8 MHz 3-Channel CCD Mode, Max 8 MHz

DIGITAL INPUTS

Logic Family CMOS Convert Command Start Conversion Rising Edge of ADCCK Clock High-Level Input Current (V Low-Level Input Current (VIN = 0V) 20 µA Positive-Going Threshold Voltage 2.20 V Negative-Going Threshold Voltage 0.80 V Input Limit AGND – 0.3 V Input Capacitance 5pF

ANALOG INPUTS

Full-Scale Input Range 0.5 3.5 Vp-p Input Capacitance 10 pF Input Limits AGND – 0.3 V External Reference Voltage Range 0.25 1.75 V Reference Input Resistance 800 W

DYNAMIC CHARACTERISTICS

Integral Non-Linearity (INL) V Differential Non-Linearity (DNL) ±1.5 LSB No Missing Codes Output Noise 8.0 LSBs rms

PSRR V DC ACCURACY

Zero Error 0.8 % FS Gain Error 1.5 % FS Offset Control Range 10-Bit Control DAC

DIGITAL OUTPUTS

Logic Family CMOS Logic Coding Straight Binary Digital Data Output Rate, Max Normal Mode 8 MHz

Supply Range +2.7 +5.3 V

V

DRV

Output Voltage, V

DRV

Low Level I High Level IOH = 50µA +4.6 V Low Level I High Level I

Output Voltage, V

DRV

Low Level I

High Level I Output Enable Time Output Enable = LOW 20 40 ns 3-State Enable Time Output Enable = HIGH 2 10 ns Output Capacitance 5pF Data Latency 8 Clock Cycles

Data Output Delay C

POWER-SUPPLY REQUIREMENTS

Supply Voltage: V

CC

Supply Current: ICC (No Load) 3-Ch CCD Mode 70 mA

Power Dissipation (No Load) 3-Ch CCD Mode 350 mW

TEMPERATURE RANGE

Operation Temperature LQFP-48 0 +85 °C Thermal Resistance

= +3.0V, Conversion Rate (f

DRV

ADCCK

) = 6MHz, f

= 2MHz, f

CK1

= 2MHz, PGA Gain = 1, normal output mode, no output load, unless

CK2

VSP3200Y VSP3210Y

= VCC) 20 µA

IN

+ 0.3 V

CC

+ 0.3 V

CC

= 500mV (V

IN

PGA Gain = 0dB, Input Grounded

= +5V, ±0.25V 0.04 % FSR

CC

= 1.0V) ±8 LSB

REF

Guaranteed

Output Voltage Range ±500 mV

Demultiplexed Mode 8 MHz

= +5V

= 50µA +0.1 V

OL

= 1.6mA +0.4 V

OL

= 0.5mA +2.4 V

OH

= +3V

= 50µA +0.1 V

OL

= 50µA +2.5 V

OH

= 15pF 12 ns

L

4.7 5 5.3 V

1-Ch CCD Mode 60 mA

1-Ch CCD Mode 300 mW

θ

JA

100 °C/W

2

VSP3200, 3210

SBMS012A

ABSOLUTE MAXIMUM RATINGS

, V

Supply Voltage: V Supply Voltage Differences: Among V

GND Voltage Differences: Among GNDA........................................ ±0.1V

Digital Input Voltage ............................................... –0.3V to (V

Analog Input Voltage .............................................. –0.3V to (V

Input Current (Any Pins Except Supplies) .....................................±10mA

Ambient Temperature Under Bias ................................. –40°C to +125°C

Storage Temperature .................................................... –55°C to +125°C

Junction Temperature.................................................................... +150°C

Lead Temperature (soldering, 5s)................................................. +260°C

Package Temperature (IR Reflow, peak, 10s) ............................. +235°C

NOTE: (1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability.

...............................................................+6.5V

CC

DRV

(1)

.........................................±0.1V

CC

CC CC

+ 0.3V) + 0.3V)

ELECTROSTATIC DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Burr-Brown recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION

PACKAGE SPECIFIED

PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER

DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT

VSP3200Y LQFP-48 340 0°C to +85°C VSP3200Y VSP3200Y 250-Piece Tray

"""""VSP3200Y/2K Tape and Reel

VSP3210Y LQFP-48 340 0°C to +85°C VSP3210Y VSP3210Y 250-Piece Tray

"""""VSP3210Y/2K Tape and Reel

NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces of “VSP3200Y/2K” will get a single 2000-piece Tape and Reel.

(1)

MEDIA

DEMO BOARD ORDERING INFORMATION

PRODUCT PACKAGE

VSP3200Y DEM-VSP3200Y

VSP3200, 3210

SBMS012A

3

PIN CONFIGURATION

Top View LQFP

B11 (A1)

B10 (A0)

B9 (D9)

B8 (D8)

B7 (D7)

B6 (D6)

B5 (D5)

B4 (D4)

B3 (D3)

B2 (D2)

B1 (D1)

B0 (D0) LSB

36 35 34 33 32 31 30

29 28 27 26

B13 B14

V

DRV

V V

AGND

TP0

V

REF

V

REFN

37 38 39 40 41 42

CC

43

CC

44 45 46 47

CC

48

B12 (A2)

B15 (MSB)

12345678910112512

CM

REFP

AGND

PIN DESCRIPTIONS (VSP3200Y)

PIN DESIGNATOR TYPE DESCRIPTION

1 CM AO Common-Mode Voltage 2 REFP AO Upper-Level Reference 3 AGND P Analog Ground 4 AGND P Analog Ground 5 RINP AI Red Channel Analog Input 6 AGND P Analog Ground 7 GINP AI Green Channel Analog Input 8 AGND P Analog Ground

9 BINP AI Blue Channel Analog Input 10 AGND P Analog Ground 11 V 12 CLP DI Clamp Enable

13 V 14 ADCCK DI Clock for A/D Converter Digital Data Output

CC

15 CK1 DI Sample Reference Clock 16 CK2 DI Sample Data Clock 17 AGND P Analog Ground 18 RD DI Read Signal for Registers 19 WRT DI Write Signal for Registers 20 P/S DI Parallel/Serial Port Select

21 SD DI Serial Data Input 22 SCLK DI Serial Data Shift Clock 23 V 24 OE DI Output Enable

CC

25 B0 (D0) LSB DIO A/D Output (Bit 0) and Register Data (D0) 26 B1 (D1) DIO A/D Output (Bit 1) and Register Data (D1) 27 B2 (D2) DIO A/D Output (Bit 2) and Register Data (D2) 28 B3 (D3) DIO A/D Output (Bit 3) and Register Data (D3)

P Analog Power Supply, +5V

HIGH = Enable, LOW = Disable

P Analog Power Supply, +5V

HIGH = Parallel Port, LOW = Serial Port

P Analog Power Supply, +5V

24

OE

23

V

CC

22

SCLK

21

SD

20

P/S

19

WRT

VSP3200Y

RINP

AGND

GINP

AGND

BINP

AGND

18

RD

17

AGND

16

CK2

15

CK1

14

ADCCK

13

V

CC

V

CLP

PIN DESIGNATOR TYPE DESCRIPTION

29 B4 (D4) DIO A/D Output (Bit 4) and Register Data (D4) 30 B5 (D5) DIO A/D Output (Bit 5) and Register Data (D5) 31 B6 (D6) DIO A/D Output (Bit 6) and Register Data (D6) 32 B7 (D7) DIO A/D Output (Bit 7) and Register Data (D7) 33 B8 (D8) DIO A/D Output (Bit 8) and Register Data (D8)

B0 LSB DO A/D Output (Bit 0) when Demultiplexed Output Mode

34 B9 (D9) DIO A/D Output (Bit 9) and Register Data (D9)

B1 DO A/D Output (Bit 1) when Demultiplexed Output Mode

35 B10 (A0) DIO A/D Output (Bit 10) and Register Address (A0)

B2 DO A/D Output (Bit 2) when Demultiplexed Output Mode

36 B11 (A1) DIO A/D Output (Bit 11) and Register Address (A1)

B3 DO A/D Output (Bit 3) when Demultiplexed Output Mode

37 B12 (A2) DIO A/D Output (Bit 12) and Register Address (A2)

B4 DO A/D Output (Bit 4) when Demultiplexed Output Mode

38 B13 DO A/D Output (Bit 13)

B5 DO A/D Output (Bit 5) when Demultiplexed Output Mode

39 B14 DO A/D Output (Bit 14)

B6 DO A/D Output (Bit 6) when Demultiplexed Output Mode

40 B15 MSB DO A/D Output (Bit 15)

B7 MSB DO A/D Output (Bit 7) when Demultiplexed Output Mode 41 V 42 V 43 V 44 AGND P Analog Ground

DRV

CC CC

P Digital Output Driver Power Supply P Analog Power Supply, +5V P Analog Power Supply, +5V

45 TP0 AO A/D Converter Input Monitor Pin (single-ended output) 46 V

REF

AIO Reference Voltage Input/Output

INT Ref: Bypass to GND with 0.1µF

EXT Ref: Input Pin for Ref Voltage 47 V 48 REFN AO Lower-Level Reference

CC

P Analog Power Supply, +5V

4

VSP3200, 3210

SBMS012A

PIN CONFIGURATION

Top View LQFP

B5, B13

B4, B12

B3, B11

B2, B10

B1, B9

B0, B8 (LSB)NCNC

36 35 34 33 32 31 30

NC

29 28 27 26

NC

NC NC

V

DRV

V V

AGND

TP0

V

REF

V

REFN

37 38 39 40 41 42

CC

43

CC

44 45 46 47

CC

48

B6, B14

B7, B15 (MSB)

12345678910112512

CM

REFP

AGND

PIN DESCRIPTIONS (VSP3210Y)

PIN DESIGNATOR TYPE DESCRIPTION

1 CM AO Common-Mode Voltage 2 REFP AO Upper-Level Reference 3 AGND P Analog Ground 4 AGND P Analog Ground 5 RINP AI Red Channel Analog Input 6 AGND P Analog Ground 7 GINP AI Green Channel Analog Input 8 AGND P Analog Ground

9 BINP AI Blue Channel Analog Input 10 AGND P Analog Ground 11 V 12 CLP DI Clamp Enable

13 V 14 ADCCK DI Clock for A/D Converter Digital Data Output

CC

15 CK1 DI Sample Reference Clock 16 CK2 DI Sample Data Clock 17 AGND P Analog Ground 18 AGND P Analog Ground 19 WRT DI Write Signal for Registers 20 AGND P Analog Ground 21 SD DI Serial Data Input 22 SCLK DI Serial Data Shift Clock 23 V 24 OE DI Output Enable

CC

25 NC – Should Be Left OPEN 26 NC – Should Be Left OPEN 27 NC – Should Be Left OPEN 28 NC – Should Be Left OPEN 29 NC – Should Be Left OPEN

P Analog Power Supply, +5V

HIGH = Enable, LOW = Disable

P Analog Power Supply, +5V

24

OE

23

V

CC

22

SCLK

21

SD

20

AGND

19

WRT

VSP3210Y

RINP

AGND

GINP

AGND

BINP

V

AGND

18

AGND

17

AGND

16

CK2

15

CK1

14

ADCCK

13

V

CC

CLP

PIN DESIGNATOR TYPE DESCRIPTION

30 NC – Should Be Left OPEN 31 B0 LSB DO A/D Output (Bit 0) LSB

B8 DO A/D Output (Bit 8)

32 B1 DO A/D Output (Bit 1)

B9 DO A/D Output (Bit 9)

33 B2 DO A/D Output (Bit 2)

B10 DO A/D Output (Bit 10)

34 B3 DO A/D Output (Bit 3)

B11 DO A/D Output (Bit 11)

35 B4 DO A/D Output (Bit 4)

B12 DO A/D Output (Bit 12)

36 B5 DO A/D Output (Bit 5)

B13 DO A/D Output (Bit 13)

37 B6 DO A/D Output (Bit 6)

B14 DO A/D Output (Bit 14)

38 B7 DO A/D Output (Bit 7)

B15 MSB DO A/D Output (Bit 15) MSB 39 NC – Should Be Left OPEN 40 NC – Should Be Left OPEN 41 V 42 V 43 V 44 AGND P Analog Ground

DRV

CC CC

P Digital Output Driver Power Supply P Analog Power Supply, +5V P Analog Power Supply, +5V

45 TP0 AO A/D Converter Input Monitor Pin (single-ended output) 46 V

REF

AIO Reference Voltage Input/Output

INT Ref: Bypass to GND with 0.1µF

EXT Ref: Input Pin for Ref Voltage 47 V 48 REFN AO Lower-Level Reference

CC

P Analog Power Supply, +5V

VSP3200, 3210

SBMS012A

5