TEXAS INSTRUMENTS VSP2262 Technical data
查询DEM-VSP2262Y供应商
www.ti.com
CCD SIGNAL PROCESSOR for
VSP2262
VSP2262
DIGITAL CAMERAS
FEATURES
● CCD SIGNAL PROCESSING:
Correlated Double Sampling (CDS)
Programmable Black Level Clamping
● PROGRAMMABLE GAIN AMPLIFIER (PGA):
–6dB to +42dB Gain Ranging
● 12-BIT DIGITAL DATA OUTPUT:
Up to 20MHz Conversion Rate
No Missing Codes
● 79dB SIGNAL-TO-NOISE RATIO
● PORTABLE OPERATION:
Low Voltage: 2.7V to 3.6V
Low Power: 83mW (typ) at 3.0V
Stand-By Mode: 6mW
SHPCLPDM SHD SLOAD SCLK SDATA
Serial Interface
Input
Clamp
DESCRIPTION
The VSP2262 is a complete mixed-signal processing
IC for digital cameras, providing signal conditioning
and Analog-to-Digital (A/D) conversion for the output
of a CCD array. The primary CCD channel provides
Correlated Double Sampling (CDS) to extract video
information from the pixels, –6dB to +42dB gain
range with digital control for varying illumination
conditions, and black level clamping for an accurate
black level reference. Input signal clamping and offset
correction of the input CDS are also performed. The
stable gain control is linear in dB. Additionally, the
black level is quickly recovered after gain change. The
VSP2262Y is available in an LQFP-48 package and
operates from a single +3V/+3.3V supply.
RESET
Timing
Control
ADCCK
DRV
V
DD
CC
PBLK
Correlated
Double
Sampling
(CDS)
Optical Black (OB)
Level Clamping
COB
CCDIN
CCD
Output
Signal
Copyright © 2000, Texas Instruments Incorporated SBMS011 Printed in U.S.A. November, 2000
Preblanking
Programmable
Amplifier
CLPOB
Gain
(PGA)
–6dB
to
+42dB
Reference Voltage Generator
BYPP2 BYP BYPM REFN CM REFP DRVGND GNDA
Analog-
to-
Digital
Converter
Output
Latch
12-Bit
Digital
Output
B[11:0]
SPECIFICATIONS
At TA = +25°C, VCC = +3.0V, DRVDD = +3.0V, Conversion Rate (f
PARAMETER CONDITIONS MIN TYP MAX UNITS
RESOLUTION 12 Bits
CONVERSION RATE 20 MHz
DIGITAL INPUT
Logic Family TTL
Input Voltage LOW to HIGH Threshold Voltage (VT+) 1.7 V
HIGH to LOW Threshold Voltage (VT–) 1.0 V
Input Current Logic HIGH (I
Logic LOW (I
DIGITAL OUTPUT
Logic Family CMOS
Logic Coding Straight Binary
Output Voltage Logic HIGH (V
Logic LOW (V
ADCCK Clock Duty Cycle 50 %
Input Capacitance 5pF
Maximum Input Voltage –0.3 5.3 V
ANALOG INPUT (CCDIN)
Input Signal Level for Full-Scale Out
PGA Gain = 0dB 900 mV
Input Capitance 15 pF
Input Limit –0.3 3.3 V
TRANSFER CHARACTERISTICS
Differential Non-Linearity (DNL) PGA Gain = 0dB ±0.5 LSB
Integral Non-Linearity (INL) PGA Gain = 0dB ±1 LSB
No Missing Codes Guaranteed
Step Response Settling Time Full-Scale Step Input 1 Pixel
Overload Recovery Time Step Input from 1.8V to 0V 2 Pixels
Data Latency 9 (Fixed) Clock Cycles
Signal-to-Noise Ratio
(1)
Grounded Input Cap, PGA Gain = 0dB 79 dB
Grounded Input Cap, Gain = +24dB 55 dB
CCD Offset Correction Range –180 200 mV
CDS
Reference Sample Settling Time Within 1LSB, Driver Impedance = 50Ω 11 ns
Data Sample Settling Time Within 1LSB, Driver Impedance = 50Ω 11 ns
INPUT CLAMP
Clamp-On Resistance 400 Ω
Clamp Level 1.5 V
PROGRAMMABLE GAIN AMP (PGA)
Gain-Control Resolution 10 Bits
Maximum Gain Gain Code = 1111111111 42 dB
High Gain Gain Code = 1101001000 34 dB
Medium Gain Gain Code = 1000100000 20 dB
Low Gain Gain Code = 0010000000 0 dB
Minimum Gain Gain Code = 0000000000 –6dB
Gain Control Error ±0.5 dB
OPTICAL BLACK CLAMP LOOP
Control DAC Resolution 10 Bits
Optical Black Clamp Level Programmable Range of Clamp Level 2 60 LSB
OBCLP Level at CODE = 1000 130 LSB
Min Output Current for Control DAC
Max Output Current for Control DAC
Loop Time Constant C
Slew Rate C
= 0.1µF, Output Current from Control DAC is Saturated 1530 V/s
COB
COB Pin ±0.15 µA
COB Pin ±153 µA
COB
REFERENCE
Positive Reference Voltage 1.75 V
Negative Reference Voltage 1.25 V
POWER SUPPLY
Supply Voltage V
Power Dissipation Normal Operation Mode: No Load, DAC0 and DAC1 are Suspended 86 mW
CC
Stand-By Mode: f
TEMPERATURE RANGE
Operating Temperature –25 +85 °C
Thermal Resistance
θ
JA
LQFP-48 100 °C/W
NOTE: (1) SNR = 20 log(full-scale voltage/rms noise).
) = 20MHz, unless otherwise noted.
ADCCK
VSP2262Y
) VIN = +3V ±20 µA
IH
) VIN = 0V ±20 µA
IL
) IOH = –2mA 2.4 V
OH
) IOL = 2mA 0.4 V
OL
= 0.1µF µs
, DRV
DD
= Not Apply 6 mW
ADCCK
2.7 3.0 3.6 V
2
VSP2262
SBMS011
ABSOLUTE MAXIMUM RATINGS
Supply Voltage: VCC, DRVDD...........................................................+4.0V
Supply-Voltage Differences: Among V
Ground-Voltage Differences: Among GNDA .................................... ±0.1V
Digital Input Voltage ............................................................ –0.3 to +5.3V
Analog Input Voltage .................................................. –0.3 to V
Input Current (Any Pins Except Supplies) ..................................... ±10mA
Ambient Temperature Under Bias .....................................–40 to +125°C
Storage Temperature .........................................................–55 to +125°C
Junction Temperature .................................................................... +150°C
Lead Temperature (Soldering, 5s) ................................................ +260°C
Package Temperature (IR Reflow, Peak, 10s) ............................. +235°C
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may
degrade device reliability.
(1)
......................................... ±0.1V
CC
CC
+ 0.3V
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Burr-Brown
recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling
and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
PACKAGE/ORDERING INFORMATION
PACKAGE SPECIFIED
PRODUCT PACKAGE NUMBER RANGE MARKING NUMBER
DRAWING TEMPERATURE PACKAGE ORDERING TRANSPORT
VSP2262Y LQFP-48 340 0 to +85°C VSP2262Y VSP2262Y 250-Piece Tray
(1)
MEDIA
"""""VSP2262Y/2K Tape and Reel
NOTE: (1) Models with a slash (/) are available only in Tape and Reel in the quantities indicated (e.g., /2K indicates 2000 devices per reel). Ordering 2000 pieces
of “VSP2262Y/2K” will get a single 2000 piece Tape and Reel.
DEMO BOARD ORDERING INFORMATION
PRODUCT ORDERING NUMBER
VSP2262Y DEM-VSP2262Y
VSP2262
SBMS011
3
PIN CONFIGURATION
Top View LQFP
GNDA
GNDA
VCCVCCBYPM
36 35 34 33 32 31 30
BYP
CCDIN
BYPP2
COB
VCCGNDA
29 28 27 26
GNDA
CM
REFP
REFN
V
CC
GNDA
GNDA
NC
NC
RESET
SLOAD
SDATA
SCLK
37
38
39
40
41
42
43
VSP2262
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
CLPDM
SHD
SHP
CLPOB
PBLK
V
CC
GNDA
ADCCK
GNDA
DRVGND
DRV
DD
12345678910112512
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
B0 (LSB)
B11 (MSB)
PIN DESCRIPTIONS
(1)
PIN NAME TYPE
1 B0 (LSB) DO Bit 0 (LSB), A/D Converter Output
2 B1 DO Bit 1, A/D Converter Output
3 B2 DO Bit 2, A/D Converter Output
4 B3 DO Bit 3, A/D Converter Output
5 B4 DO Bit 4, A/D Converter Output
6 B5 DO Bit 5, A/D Converter Output
7 B6 DO Bit 6, A/D Converter Output
8 B7 DO Bit 7, A/D Converter Output
9 B8 DO Bit 8, A/D Converter Output
10 B9 DO Bit 9, A/D Converter Output
11 B10 DO Bit 10, A/D Converter Output
12
B11 (MSB)
13 DRV
14 DRVGND P Digital Ground, Exclusively for Digital Output
DD
15 GNDA P Analog Ground
16 ADCCK DI Clock for Digital Output Buffer
17 GNDA P Analog Ground
18 V
CC
19 PBLK DI Preblanking:
20 CLPOB DI Optical Black Clamp Pulse (Default = Active LOW)
21 SHP DI
22 SHD DI CDS Data Level Sampling Pulse (Default = Active LOW)
23 CLPDM DI Dummy Pixel Clamp Pulse (Default = Active LOW)
DESCRIPTION
DO Bit 11 (MSB), A/D Converter Output
P Power Supply, Exclusively for Digital Output
P Analog Power Supply
HIGH = Normal Operation Mode
LOW = Preblanking Mode: Digital Output “All Zero”
CDS Reference Level Sampling Pulse (Default = Active LOW)
PIN NAME
24 V
CC
25 GNDA P Analog Ground
26 GNDA P Analog Ground
27 V
CC
28 COB AO Optical Black Clamp Loop Reference
29 BYPP2 AO Internal Reference P
30 CCDIN AI CCD Signal Input
31 BYP AO Internal Reference C
32 BYPM AO Internal Reference N
33 V
CC
34 V
CC
35 GNDA P Analog Ground
36 GNDA P Analog Ground
37 CM AO A/D Converter Common-Mode Voltage
38 REFP AO A/D Converter Positive Reference
39 REFN AO A/D Converter Negative Reference
40 V
CC
41 GNDA P Analog Ground
42 GNDA P Analog Ground
43
NC
44
(5)
(5)
(5)
(5)
NC
45 RESET DI Asynchronous System Reset (Active LOW)
46 SLOAD DI Serial Data Latch Signal (Triggered at the Rising Edge)
47 SDATA DI Serial Data Input
48 SCLK DI Clock for Serial Data Shift (Triggered at the Rising Edge)
NOTES: (1) Type designators: P = Power Supply and Ground; DI = Digital Input; DO = Digital Output; AI = Analog Input; AO = Analog Output. (2) Should be
connected to ground with a bypass capacitor. We recommend the value of 0.1µF to 0.22 µF, however, it depends on the application environment. Refer to the “Optical
Black Level Clamp Loop” section for more detail. (3) Should be connected to ground with a bypass capacitor. We recommend the value of 400pF to 9000pF, however,
it depends on the application environment. Refer to the “Voltage Reference” section for more detail. (4) Should be connected to ground with a bypass capacitor
(0.1µF). Refer to the “Voltage Reference” section for more detail. (5) Refer to “Serial Interface” section for more detail.
(1)
TYPE
DESCRIPTION
P Analog Power Supply
P Analog Power Supply
P Analog Power Supply
P Analog Power Supply
P Analog Power Supply
– Should be Left OPEN
– Should be Left OPEN
(3)
(2)
(4)
(3)
(4)
(4)
(4)
4
VSP2262
SBMS011
Loading...