Texas Instruments UCC28600 User Manual
1
2
3
4
8
7
6
5
VCC
DRV
GND
ZCD
VO_SNS
COMP
MULTIN
CS
UCC28051
C
BULK
1
2
3
4
8
7
6
5
STATUS
OVP
VDD
OUT
SS
FB
CS
GND
UCC28600
C
SS
C
BP
R
PL
R
SU
R
CS
C
VDD
Primary Secondary
TL431
Feedback
R
OVP2
R
OVP1
18 V
C
B
N
P
N
S
N
B
M
1
UCC28600
www.ti.com
SLUS646J –NOVEMBER 2005– REVISED JULY 2011
8-Pin Quasi-Resonant Flyback Green-Mode Controller
Check for Samples: UCC28600
1
FEATURES
2
• Green-Mode Controller With Advanced Energy
Saving Features PDP-TV, and Set Top Boxes
• Quasi-Resonant Mode Operation for Reduced • AC/DC Adapters and Offline Battery Chargers
EMI and Low Switching Losses (Low Voltage
Switching)
• Low Standby Current for System No-Load
Power Consumption
• Low Startup Current: 25 μA Maximum
• Programmable Overvoltage Protection, Line
and Load
• Internal Overtemperature Protection
• Current Limit Protection
– Cycle-by-Cycle Power Limit
– Primary-Side Overcurrent Hiccup Restart
Mode
• 1-A Sink TrueDrive™, -0.75-A Source Gate
Drive Output
• Programmable Soft-Start
• Green-Mode Status Pin (PFC Disable Function)
.
.
APPLICATIONS
• Bias Supplies for LCD-Monitors, LCD-TV,
• Energy Efficient Power Supplies up to 200 W
DESCRIPTION
The UCC28600 is a PWM controller with advanced
energy features to meet stringent world-wide energy
efficiency requirements.
UCC28600 integrates built-in advanced energy
saving features with high level protection features to
provide cost effective solutions for energy efficient
power supplies. UCC28600 incorporates frequency
fold back and green mode operation to reduce the
operation frequency at light load and no load
operations.
UCC28600 is offered in the 8-pin SOIC (D) package.
Operating junction temperature range is -40°C to
105°C.
TYPICAL APPLICATION
1
2TrueDrive is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2005–2011, Texas Instruments Incorporated
UCC28600
SLUS646J –NOVEMBER 2005– REVISED JULY 2011
www.ti.com
DESCRIPTION (CONT.)
The Design Calculator, (Texas Instruments Literature number SLVC104), located in the Tools and Software
section of the UCC28600 product folder, provides a user-interactive iterative process for selecting recommended
component values for an optimal design.
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range unless otherwise noted
VDD Supply voltage range IDD< 20 mA 32 V
I
DD
I
OUT(sink)
I
OUT(source)
V
OVP
I
OVP(source)
V
STATUS
T
J
T
stg
T
LEAD
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages
are with respect to GND. Currents are positive into, negative out of the specified terminal. Consult Packaging Section of the databook
for thermal limitations and considerations of packages.
Supply current 20 mA
Output sink current (peak) 1.2
Output source current (peak) -0.8
Analog inputs FB, CS, SS -0.3 to 6.0
VDD = 0 V to 30 V 30 V
Power dissipation SOIC-8 package, TA= 25°C 650 mW
Operating junction temperature range –55 to 150
Storage temperature –65 to 150 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300
(1)
UCC28600 UNIT
A
-1.0 to 6.0
-1.0 mA
V
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
VDD Input voltage 21 V
I
T
Output sink current 0 A
OUT
Operating junction temperature -40 105 °C
J
ELECTROSTATIC DISCHARGE (ESD) PROTECTION
MIN MAX UNIT
Human body model 2000
CDM 1500
V
2 Copyright © 2005–2011, Texas Instruments Incorporated
UCC28600
www.ti.com
SLUS646J –NOVEMBER 2005– REVISED JULY 2011
ELECTRICAL CHARACTERISTICS
VDD = 15 V, 0.1-μF capacitor from VDD to GND, 3.3-nF capacitor from SS to GND charged over 3.5 V, 500-Ω resistor from
OVP to -0.1 V, FB = 4.8 V, STATUS = not connected, 1-nF capacitor from OUT to GND, CS = GND, TA= -40°C to 105°C,
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Overall
I
STARTUP
I
STANDBY
I
DD
Undervoltage Lockout
VDD
(uvlo)
ΔVDD
(uvlo)
PWM (Ramp)
D
MIN
D
MAX
Oscillator (OSC)
f
QR(max)
f
QR(min)
f
SS
dTS/dFB VCO gain TSfor 1.6 V < VFB< 1.8 V -38 -30 -22 μs/V
Feedback (FB)
R
FB
V
FB
Status
R
DS(on)
I
STATUS(leakage)
(1) R
SCT
and C
Startup current VDD = V
-0.3 V 12 25
UVLO
Standby current VFB= 0 V 350 550
Operating current mA
Not switching 2.5 3.5
130 kHz, QR mode 5.0 7.0
VDD clamp FB = GND, IDD= 10 mA 21 26 32 V
Startup threshold 10.3 13.0 15.3
Stop threshold 6.3 8 9.3 V
Hysteresis 4.0 5.0 6.0
(1)
Minimum duty cycle VSS= GND, VFB= 2 V 0%
Maximum duty cycle QR mode, fS= max, (open loop) 99%
Maximum QR and DCM frequency 117 130 143
Minimum QR and FFM frequency VFB= 1.3 V 32 40 48 kHz
Soft start frequency VSS= 2.0 V 32 40 48
Feedback pullup resistor 12 20 28 kΩ
FB, no load QR mode 3.30 4.87 6.00
Green-mode ON threshold VFBthreshold 0.3 0.5 0.7
Green-mode OFF threshold VFBthreshold 1.2 1.4 1.6
Green-mode hysteresis VFBthreshold 0.7 0.9 1.1 V
FB threshold burst-ON VFBduring green mode 0.3 0.5 0.7
FB threshold burst-OFF VFBduring green mode 0.5 0.7 0.9
Burst Hysteresis VFBduring green mode 0.13 0.25 0.42
STATUS on resistance V
STATUS leakage/off current VFB= 0.44 V, V
are not connected in the circuit for maximum and minimum duty cycle tests, current sense tests and power limit tests.
CST
= 1 V 1.0 2.4 3.8 kΩ
STATUS
= 15 V -0.1 2.0 μA
STATUS
μA
Copyright © 2005–2011, Texas Instruments Incorporated 3
UCC28600
SLUS646J –NOVEMBER 2005– REVISED JULY 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
VDD = 15 V, 0.1-μF capacitor from VDD to GND, 3.3-nF capacitor from SS to GND charged over 3.5 V, 500-Ω resistor from
OVP to -0.1 V, FB = 4.8 V, STATUS = not connected, 1-nF capacitor from OUT to GND, CS = GND, TA= -40°C to 105°C,
(unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Current Sense (CS)
A
CS(FB)
V
CS(os)
Power Limit (PL)
I
PL(cs)
V
PL
Soft Start (SS)
I
SS(chg)
I
SS(dis)
V
SS
Overvoltage Protection (OVP)
I
OVP(line)
V
OVP(on)
V
OVP(load)
Thermal Protection (TSP)
OUT
t
RISE
t
FALL
(2) R
(3) Ensured by design. Not production tested.
SCT
and C
(2)
Gain, FB = ΔVFB/ ΔV
CS
QR mode 2.5 V/V
Shutdown threshold VFB= 2.4 V, VSS= 0 V 1.13 1.25 1.38 V
CS to output delay time (power limit) CS = 1.0 V
CS to output delay time (over current
fault)
CS = 1.45 V
PULSE
PULSE
100 175 300
50 100 150
CS discharge impedance CS = 0.1 V, VSS= 0 V 25 115 250 Ω
CS offset SS mode, VSS≤ 2.0 V, via FB 0.35 0.40 0.45 V
(2)
CS current OVP = -300 μA -165 -150 -135 μA
CS working range QR mode, peak CS voltage 0.70 0.81 0.92
PL threshold Peak CS voltage + CS offset 1.05 1.20 1.37
Softstart charge current VSS= GND -8.3 -6.0 -4.5 μA
Softstart discharge current VSS= 0.5 V 2.0 5.0 10 mA
Switching ON threshold Output switching start 0.8 1.0 1.2 V
Line overvoltage protection I
OVP voltage at OUT = HIGH -125 -25 mV
Load overvoltage protection V
Thermal shutdown (TSP) temperature
(3)
threshold, OUT = HI -512 -450 -370 μA
OVP
VFB= 4.8 V, VSS= 5.0 V, I
μA
threshold, OUT = LO 3.37 3.75 4.13 V
OVP
OVP(on)
, = -300
130 140 150
Thermal shutdown hysteresis 15
Rise time 10% to 90% of 13 V typical out clamp 50 75
Fall time 10 20
are not connected in the circuit for maximum and minimum duty cycle tests, current sense tests and power limit tests.
CST
ns
V
°C
ns
4 Copyright © 2005–2011, Texas Instruments Incorporated
STATUS
GND
V
FB
V
CS
V
OVP
V
OUT
V
DD
I
DD
I
OVP
R
OVP
500 Ω
C
OUT
1.0 nF
R
OUT
10 Ω
C
BIAS
1 µF
CDD 100 nF
I
CS
C
FB
47 pF
C
SS
3.3 nF
C
CST
560 pF
See Note
R
CST
37.4 kΩ
See Note
SS
VDD
GND
OUT
FB
CS
OVP
STATUS
UCC28600
+
1
2
3
4 5
6
7
8
5 V
2
1
6
5.0
VREF
SS
VDD
4
GND
5
OUT
FB
1.5R
8
3
CS
UVLO
+
C
BULK
Feedback
20kW
C
SS
7
OVP
On-Chip
Thermal
Shutdown
REF
26V
R
STATUS
13/8V
R
CS
R
OVP1
R
OVP2
C
VDD
+
400mV
REF
R
SU
+
Q
Q
SET
CLR
D
REF
GAIN=1/2.5
+
Modulation
Comparison
UCC28600
FaultLogic
LINE_OVP
LOAD_OVP
REF_OK
RUN
UVLO
CS
OVR_T
STATUS
SS_DIS
GREENMODE
FB_CLAMP
OSC_CL
FB
QRDETECT
LOAD_OVP
LINE_OVP
QR_DONE
____
OUT
CS
OSCILLATOR
QR_DONE
CLK
RUN
SS_OVR
OSC_CL
R
PL
PL
1.2V
SS_OVR BURST BURST
R
VDD
VDD
UCC28600
www.ti.com
OPEN LOOP TEST CIRCUIT
R
and C
CST
sense tests and power limit tests.
are not connected for maximum and minimum duty cycle tests, current
CST
SLUS646J –NOVEMBER 2005– REVISED JULY 2011
NOTE
BLOCK DIAGRAM/TYPICAL APPLICATION
Copyright © 2005–2011, Texas Instruments Incorporated 5
1
2
3
4
8
7
6
5
SS
FB
CS
GND
STATUS
OVP
VDD
OUT
UCC28600
D PACKAGE
(TOP VIEW)
UCC28600
SLUS646J –NOVEMBER 2005– REVISED JULY 2011
www.ti.com
ORDERING INFORMATION
T
A
-40°C to 105°C SOIC (D)
(1) SOIC (D) package is available taped and reeled by adding “R” to the above part numbers. Reeled quantities for UCC28600DR is 2,500
devices per reel.
PACKAGES PART NUMBER
(1)
UCC28600D
DEVICE INFORMATION
TERMINAL FUNCTIONS
TERMINAL
NAME NO.
CS 3 I protection. The CS voltage input originates across a current sense resistor and ground. Power limit is
FB 2 I Connect the collector of the photo-transistor of the feedback optocoupler directly to this pin; connect the emitter
GND 4 -
OUT 5 O
OVP 7 I Detect line, load and resonant conditions using the primary bias winding of the transformer, adjust sensitivity
SS 1 I be placed as close as possible to the SS pin and GND, keeping trace length to a minimum. All faults discharge
STATUS 8 O disable the PFC control circuit (high impedance = green mode). STATUS pin is high during UVLO, (VDD <
VDD 6 I pin, as described in the GND pin description. Operating energy is usually delivered from auxiliary winding. To
I/O DESCRIPTION
Current sense input. Also programs power limit, and used to control modulation and activate overcurrent
programmed with an effective series resistance between this pin and the current sense resistor.
Feedback input or control input from the optocoupler to the PWM comparator used to control the peak current
in the power MOSFET. An internal 20-kΩ resistor is between this pin and the internal 5-V regulated voltage.
of the photo-transistor to GND. The voltage of this pin controls the mode of operation in one of the three
modes: quasi resonant (QR), frequency foldback mode (FFM) and green mode (GM).
Ground for internal circuitry. Connect a ceramic 0.1-μF bypass capacitor between VDD and GND, with the
capacitor as close to these two pins as possible.
1-A sink (TrueDrive™ ) and 0.75-A source gate drive output. This output drives the power MOSFET and
switches between GND and the lower of VDD or the 13-V internal output clamp.
Over voltage protection (OVP) input senses line-OVP, load-OVP and the resonant trough for QR turn-on.
with resistors connected to this pin.
Soft-start programming pin. Program the soft-start rate with a capacitor to ground; the rate is determined by the
capacitance and the internal soft-start charge current. Placement of the soft-start capacitor is critical and should
the SS pin to GND through an internal MOSFET with an R
comparator reacts to the lowest of the SS voltage, the internal FB voltage and the peak current limit.
ACTIVE HIGH open drain signal that indicates the device has entered standby mode. This pin can be used to
startup threshold), and softstart, (SS < FB).
Provides power to the device. Use a ceramic 0.1-μF by-pass capacitor for high-frequency filtering of the VDD
prevent hiccup operation during start-up, a larger energy storage cap is also needed between VDD and GND.
of approximately 100 Ω. The internal modulator
DS(on)
6 Copyright © 2005–2011, Texas Instruments Incorporated
R
CS
+
ǒ
VPL* V
CS(os)
Ǔǒ
I
CS(2)
* I
CS(1)
Ǔ
I
CS(2)IP(1)
* I
CS(1)IP(2)
R
PL
+
ǒ
VPL* V
CS(os)
Ǔǒ
I
P(2)
* I
P(1)
Ǔ
I
CS(1)IP(2)
* I
CS(2)IP(1)
R
OVP1
+
1
I
OVP(line)
ǒ
N
B
N
P
V
BULK(ov)
Ǔ
R
OVP2
+ R
OVP1
ȧ
ȧ
ȡ
Ȣ
V
OVP(load)
N
B
N
S
ǒ
V
OUT(shutdown)
) V
F
Ǔ
* V
OVP(load)
ȧ
ȧ
ȣ
Ȥ
UCC28600
www.ti.com
TERMINAL COMPONENTS
TERMINAL
NAME NO.
CS 3 I
FB 2 I Opto-isolator collector
GND 4 - Bypass capacitor to VDD, CBP= 0.1 μF
OUT 5 O Power MOSFET gate
I/O DESCRIPTION
where:
• IP1is the peak primary current at low line, full load
• IP2is the peak primary current at high line, full load
• I
CS1
• I
CS2
• VPLis the Power Limit (PL) threshold
• V
CS(os)
(1) (2) (3)
is the power limit current that is sourced at the CS pin at low-line voltage
is the power limit current that is sourced at the CS pin at high-line voltage
is the CS offset voltage
(2)
SLUS646J –NOVEMBER 2005– REVISED JULY 2011
(1)
(3)
(3)
(3)
(3)
(2)
OVP 7 I
(1) Refer to Figure 1 for all reference designators in the Terminal Components Table.
(2) Refer to the Electrical Characteristics Table for constant parameters.
(3) Refer to the UCC28600 Design Calculator (TI Literature Number SLVC104) or laboratory measurements for currents, voltages and times
in the operational circuit.
Copyright © 2005–2011, Texas Instruments Incorporated 7
where:
• I
OVP(line)
• V
BULK(ov)
• V
OVP(load)
• V
OUT(shutdown)
• VFis the forward voltage of the secondary rectifier
• NBis the number of turns on the bias winding
• NSis the number of turns on the secondary windings
• NPis the number of turns on the primary windings
is OVP
is the allowed input over- voltage level
is OVP
current threshold
line
(2)
load
is the allowed output over-voltage level
(2)
(3)
(3)
(3)
(3)
(3)
CSSu I
SS
t
SS(min)
(
due power limit
)
A
CS(FB)
ǒ
VPL* V
CS(os)
Ǔ
t
SS(min)
+
ȧ
ȧ
ȱ
Ȳ
* R
LOAD(ss)COUT
2
ȏn
ȧ
ȡ
Ȣ
1 *
ǒ
V
OUT
* DV
OUT(step)
Ǔ
2
R
LOAD(ss)POUT(max)limit
ȧ
ȣ
Ȥ
ȧ
ȧ
ȳ
ȴ
t
SS(min)
+
ȧ
ȱ
Ȳ
C
OUTVOUT
2
2 P
LIM
ȧ
ȳ
ȴ
R
ST2
+
V
BE(off)
I
STATUS(leakage)
R
ST1
+
R
ST2
ƪ
VDD
(uvlo*on)
* V
BE(sat)
* R
DS(on)
ǒ
I
CC
b
sat
Ǔ
ƫ
* R
DS(on)VBE(sat)
ǒ
ǒ
I
CC
b
sat
Ǔ
R
ST2
Ǔ
) V
BE(sat)
UCC28600
SLUS646J –NOVEMBER 2005– REVISED JULY 2011
TERMINAL COMPONENTS (continued)
TERMINAL
NAME NO.
SS 1 I
I/O DESCRIPTION
where t
or
• R
LOAD(ss)
• ΔV
• P
OUT(max limit)
• A
CS(FB)
• V
CS(os)
• ISSis the soft-start charging current
• VPLis the power limit threshold
(1) (2) (3)
is the greater of:
SS(min)
is the effective load impedance during soft-start
OUT(step)
is the allowed change in V
is the current sense gain
is the CS offset voltage
due to a load step
Programmed power limit level, in W
OUT
(5)
(5)
(5)
(5)
www.ti.com
(2)
(4)
(4)
(4)
STATUS 8 O
where:
• β
• V
• VDD
• ICCis the collector current of Q
• I
• V
• R
(4) Refer to the UCC28600 Design Calculator (TI Literature Number SLVC104) or laboratory measurements for currents, voltages and times
in the operational circuit.
(5) Refer to the Electrical Characteristics Table for constant parameters.
8 Copyright © 2005–2011, Texas Instruments Incorporated
is the gain of transistor QSTin saturation
SAT
BE(sat)
(uvlo-on)
STATUS(leakage)
is the maximum allowable voltage across the base emitter junction that will not turn QSTon
BE(off)
DS(on)
is the base-emitter voltage of transistor QSTin saturation
is the startup threshold
is the maximum leakage/off current of the STATUS pin
is the R
DS(on)
of STATUS
(5)
ST
(5)
(5)
C
VDD
+
ƪ
ǒ
IDD) C
ISSVOUT(hi)fQR(max)
Ǔ
T
BURST
DV
DD(burst)
ƫ
C
VDD
+
ƪ
ǒ
IDD) C
ISSVOUT(hi)fQR(max)
Ǔ
t
SS
DVDD
(uvlo)
ƫ
R
VDD
+
ǒ
p
4
Ǔ
ǒ
N
B
NP
Ǔ
ȧ
ȡ
Ȣ
ǒ
V
DS1(os)fQR(max)LLEAKAGE
ǒ
CD) C
SNUB
Ǔ
Ǹ
IDD) C
ISSVOUT(hi)fQR(max)
ȧ
ȣ
Ȥ
R
SU
+
V
BULK(min)
I
STARTUP
UCC28600
www.ti.com
TERMINAL COMPONENTS (continued)
TERMINAL
NAME NO.
VDD 6 I
(6) Refer to the Electrical Characteristics Table for constant parameters.
(7) Refer to the UCC28600 Design Calculator (TI Literature Number SLVC104) or laboratory measurements for currents, voltages and times
in the operational circuit.
I/O DESCRIPTION
C
is the greater of:
VDD
or
where:
• IDDis the operating current of the UCC28600
• C
ISS
• V
OUT(hi)
• f
QR(max)
• T
BURST
• ΔVDD
• ΔVDD
• V
DS1(os)
• L
LEAKAGE
• CDis the total drain node capacitance of MOSFET M
• I
STARTUP
• C
SNUB
• tSSis the soft start charge time
(1) (2) (3)
(6)
is the input capacitance of MOSFET M
is VOH of the OUT pin, either 13 V (typ) V
is fSat high line, maximum load
is the measured burst mode period
is the allowed VDDripple during burst mode
(burst)
is the UVLO hysteresis
(uvlo)
is the amount of drain-source overshoot voltage
is the leakage inductance of the primary winding
is IDDstart-up current of the UCC28600
is the snubber capacitor value
(6)
(7)
1
(6)
OUT
(6)
SLUS646J –NOVEMBER 2005– REVISED JULY 2011
(3)
clamp or less as measured
1
Copyright © 2005–2011, Texas Instruments Incorporated 9
C
BULK
FEEDBACK
C
SS
R
CS
R
OVP1
R
OVP2
C
VDD
D1
R
SU
R
PL
TL431
2
1
6
SS
VDD
4 GND 5OUT
FB
8
3 CS
7OVP
STATUS
UCC28600
C
BP
100nF
R
ST2
R
ST1
C
OUT
PRIMARY SECONDARY
N
1
N
B
N
2
V
OUT
+
-
+
-
V
BULK
I
CC
R
VDD
Q
ST
R
OUT
R
SNUB
C
SNUB
M
1
PFC OUTPUT
or
BRIDGE RECTIFIER
PFC CONTROLLER BIAS
(if used)
C
BIAS
D2
UCC28600
SLUS646J –NOVEMBER 2005– REVISED JULY 2011
www.ti.com
Figure 1. Pin Termination Schematic
10 Copyright © 2005–2011, Texas Instruments Incorporated
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