TEXAS INSTRUMENTS UCC1807-1, UCC1807-2, UCC1807-3, UCC2807-1, UCC2807-2 Technical data

www.ti.com

PROGRAMMABLE MAXIMUM DUTY CYCLE PWM CONTROLLER

FEATURES DESCRIPTION

• User Programmable Maximum PWM Duty

Cycle

• 100-A Startup Current

• Operation to 1 MHz

• Internal Full Cycle Soft Start

• Internal Leading Edge Blanking of Current

Sense Signal

• 1-A Totem Pole Output

ORDERING INFORMATION

PART TURN-ON TURN-OFF

NUMBER THRESHOLD THRESHOLD

UCCx807-1 7.2 V 6.9 V J
UCCx807-2 12.5 V 8.3 V N, D
UCCx807-3 4.3 V 4.1 V N, D, PW

UCC1807-1/-2/-3
UCC2807-1/-2/-3
UCC3807-1/-2/-3

SLUS163A – JUNE 1997 – REVISED AUGUST 2007

The UCC3807 family of high speed, low power
integrated circuits contains all of the control and
drive circuitry required for off-line and dc-to-dc fixed
frequency current mode switching power supplies
with minimal external parts count.

These devices are similar to the UCC3800 family,
but with the added feature of a user programmable
maximum duty cycle. Oscillator frequency and
maximum duty cycle are programmed with two
resistors and a capacitor. The UCC3807 family also
features internal full cycle soft start and internal
leading edge blanking of the current sense input.

PACKAGES

The UCC3807 family offers a variety of package
options, temperature range options, and choice of
critical voltage levels. The family has UVLO
thresholds and hysteresis levels for off-line and
battery powered systems. Thresholds are shown in
the table below.

BLOCK DIAGRAM

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 1997–2007, Texas Instruments Incorporated

www.ti.com

UCC

UVLOThreshold

Package

TemperatureRange

807

--

OUT

VDD

DISCH

GND

COMP

TRIG

FB

CS

1

2

3

4

8

7

6

5

TRIG

N/C

COMP

N/C

DISCH

N/C

VDD

OUT

14

8

13

12

11

10

9

1

7

2

3

4

56FB

CS

N/C

N/C

GND

GND

UCC1807-1/-2/-3
UCC2807-1/-2/-3
UCC3807-1/-2/-3

SLUS163A – JUNE 1997 – REVISED AUGUST 2007

ORDERING INFORMATION

CONNECTION DIAGRAMS

DIL-8, SOIC-8 (Top View) J, N or D Packages

TSSOP-14 (Top View) PW Package (UCC2807-3

only)

NOTE

Specified thermal
resistance is θ
to lead) on TSSOP-14 pin
8 and 9.

(junction

JL

THERMAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)

PACKAGE θ

DIL-8, J 125-160 28

DIL-8, N 110

SOIC-8, D 84-160

TSSOP-14 132-158

(1) θJCdata values stated were derived from MIL-STD-1835B. MIL-STD-1835B states that "The baseline values shown are worst case

(mean + 2s) for a 60 x 60 mil microcircuit device silicon die and applicable for devices with die sizes up to 14400 square mils. For device
die size greater than 14400 square mils use the following values; dual-in-line, 11 ° C/W; flat pack, 10 ° C/W; pin grid array, 10 ° C/W".

(2) Specified θJC(junction to ambient) is for devices mounted to 5 in2 FR4 PC board with one ounce copper where noted. When resistance

range is given, lower values are for 5 in2 aluminum PC board. Test PWB was 0.062 inch thick and typically used 0.635 mm trace widths
for power packages and 1.3 mm trace widths for non-power packages with 100 x 100 mil probe land area at the end of each trace.

(3) Modeled Data. If value range given for θJA, lower value is for 3 x 3 in., 1 ounce internal copper ground plane, higher value is for 1 x 1

inch ground plane. All model data assumes only one trace for each non-fused lead.

2

Submit Documentation Feedback

JA

(2)

(2)

(3)

θ

50
42

15

JC

(1)

(3)

www.ti.com

A

V

COMP

V

CS

, 0 VCS0.8 V

UCC1807-1/-2/-3
UCC2807-1/-2/-3
UCC3807-1/-2/-3

SLUS163A – JUNE 1997 – REVISED AUGUST 2007

ABSOLUTE MAXIMUM RATINGS

Supply voltage (I
Supply current 30 mA
OUT current ± 1 A
Analog inputs (FB, CS) –0.3 V to (V

Power dissipation

Storage temperature –65 ° C to 150 ° C
Junction temperature –65 ° C to 150 ° C
Lead temperature (soldering, 10 sec.) 300 ° C

(1) All currents are positive into, negative out of the specified terminal.
(2) The UCCx807-2 is designed to be operated in a system that uses as external high voltage source to provide a startup current to a large

capacitor from VDD to GND. The worse case current from this source should be less thanthe current needed to run the device in normal
operation. The capacitor is needed to provide the reservoir of energy to allow the completion of the startup process before the UVLO
voltage is encountered. Once started the converter should be designed so that it is self powered from a controlled voltage source of a
lower voltage, one between 9.5 V and 11.5 V. The device is not designed to have the VDD clamp active during normal operation. The
VDD voltage is always less than the clamp voltage. The upper limit of the input voltage is applicable to the whole family of
UCCx807-1/-2 or -3.

10 mA) 13.5 V

DD

TA+25 ° C (N or J packages) 1 W
TA+25 ° C (D package) 0.65 W

(1) (2)

UNIT

+ 0.3 V)

DD

ELECTRICAL CHARACTERISTICS

Unless otherwise stated these specifications apply for TA= –55 ° C to 125 ° C for UCC1807-1/-2/-3; –40 ° C to 85 ° C for
UCC2807-1/-2/-3; and 0 ° C to 70 ° C for UCC3807-1/-2/-3; V
capacitor from V

Oscillator

Frequency 175 202 228 kHz
Temperature stability See
Amplitude See

Error Amplifier

Input voltage COMP = 2.0 V 1.95 2.00 2.05 V
Input bias current –1 1 A
Open loop voltage gain 60 80 dB
COMP sink current FB = 2.2 V, COMP = 1.0 V 0.3 2.5
COMP source current FB = 1.3 V, COMP = 4.0 V –0.2 –0.5

PWM

Maximum duty cycle 75% 78% 81%
Minimum duty cycle COMP = 0 V 0%

Current Sense

Gain See
Maximum input signal COMP = 5.0 V
Input bias current –200 200 nA
CS blank time 50 100 150 ns
Overcurrent threshold 1.4 1.5 1.6
COMP to CS offset CS = 0 V 0.55 1.1 1.65

to GND, TA= TJ.

DD

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(2)
(3)

(4)

DD

(5)

= 10 V

(1)

, RA= 12 k Ω , RB= 4.7 k Ω , CT= 330 pF, 1.0 μ F

2.5%

1/3VDD V

1.1 1.65 1.8 V/V

0.9 1.0 1.1 V

mA

V

(1) Adjust VDD above the start threshold before setting at 10 V for UCC3807-2.
(2) Ensured by design. Not 100% tested in production.
(3) Measured at TRIG; signal minimum = 1/3 VDD, maximum = 2/3 VDD.

(4) Gain is defined by:
(5) Parameter measured at trip point of latch with FB at 0 V.

Submit Documentation Feedback

3

www.ti.com

UCC1807-1/-2/-3
UCC2807-1/-2/-3
UCC3807-1/-2/-3

SLUS163A – JUNE 1997 – REVISED AUGUST 2007

ELECTRICAL CHARACTERISTICS (continued)

Unless otherwise stated these specifications apply for TA= –55 ° C to 125 ° C for UCC1807-1/-2/-3; –40 ° C to 85 ° C for
UCC2807-1/-2/-3; and 0 ° C to 70 ° C for UCC3807-1/-2/-3; V
capacitor from V

Output

OUT low level I = 100 mA 0.4 1
OUT high level I = 100 mA, VDD – OUT 0.4 1
Rise/fall time 20 100 ns

Undervoltage Lockout

Start threshold UCCx807-2 11.5 12.5 13.5 V

Minimum operating voltage after start UCCx807-2 7.6 8.3 9.0 V

Hysteresis UCCx807-2 3.5 4.2 5.1 V

Soft Start

COMP rise time FB = 1.8 V, From 0.5 V to 4.0 V 4

Overall

Startup current

Operating supply current FB = 0 V, CS = 0 V, No Load
VDD zener shunt voltage IDD= 10 mA 12.0 13.5 15.0 V
Shunt to start difference 0.5 10 V

(6) Start Threshold and Zener Shunt thresholds track one another.
(7) Does not include current in external timing RC network.

to GND, TA= TJ.

DD

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

UCCx807-1

UCCx807-3 4.1 4.3 4.5
UCCx807-1

UCCx807-3 3.9 4.1 4.3
UCCx807-1 0.1 0.3 0.5

UCCx807-3 0.1 0.2 0.3

VDD < Start Threshold (UCCx807-1,-3) 0.1 0.2
VDD < Start Threshold (UCCx807-2) 0.15 0.25 mA

(6)

(6)

= 10 V , RA= 12 k Ω , RB= 4.7 k Ω , CT= 330 pF, 1.0 μ F

DD

6.6 7.2 7.8

6.3 6.9 7.5

(7)

1.3 2.1

V

4

Submit Documentation Feedback

www.ti.com

frequency

1.4

RA2RBC

T

duty cycle

RAR

B

RA2R

B

UCC1807-1/-2/-3
UCC2807-1/-2/-3
UCC3807-1/-2/-3

SLUS163A – JUNE 1997 – REVISED AUGUST 2007

PIN DESCRIPTIONS

COMP: COMP is the output of the error amplifier and the input of the PWM comparator. The error amplifier in

the UCC3807 is a low output impedance, 2 MHz operational amplifier. COMP can both source and sink current.
The error amplifier is internally current limited, which allows zero duty cycle by externally forcing COMP to GND.

The UCC3807 family features built-in full cycle soft start. Soft start is implemented as a clamp on the maximum
COMP voltage.

CS: Current sense input. There are two current sense comparators on the chip, the PWM comparator and an
overcurrent comparator.

The UCC3807 also contains a leading edge blanking circuit, which disconnects the external CS signal from the
current sense comparator during the 100 ns interval immediately following the rising edge of the signal at the
OUT pin. In most applications, no analog filtering is required on CS. Compared to an external RC filtering
technique, leading edge blanking provides a smaller effective CS to OUT propagation delay. Note, however, that
the minimum non-zero on-time of the OUT signal is directly affected by the leading edge blanking and the CS to
OUT propagation delay.

The overcurrent comparator is only intended for fault sensing. Exceeding the overcurrent threshold causes a soft
start cycle.

FB: The inverting input to the error amplifier. For best stability, keep connections to FB as short as possible and
stray capacitance as small as possible.

GND: Reference ground and power ground for all functions of the part.
OUT: The output of a high current power driver capable of driving the gate of a power MOSFET with peak

currents exceeding 1A. OUT is actively held low when VDD is below the UVLO threshold.
The high current power driver consists of MOSFET output devices in a totem pole configuration. This allows the

output to switch from VDD to GND. The output stage also provides a very low impedance which minimizes
overshoot and undershoot. In most cases, external Schottky clamp diodes are not required.

TRIG/DISCH: Oscillator control pins. Trig is the oscillator timing input, which has an RC-type charge/discharge
signal controlling the chip’s internal oscillator. DISCH is the pin which provides the low impedance discharge
path for the external RC network during normal operation. Oscillator frequency and maximum duty cycle are
computed as follows:

as shown in Figure 1 .
For best performance, keep the lead from C

is desirable. The minimum value of R
C

is 47 pF.

T

A

to GND as short as possible. A separate ground connection for C

T

is 10 k Ω , the minimum value of R

is 2.2 k Ω , and the minimum value of

B

VDD: The power input connection for this device. Total VDD current is the sum of quiescent current and the
average OUT current. Knowing the operating frequency and the MOSFET gate charge (Qg), average OUT
current can be calculated from

I

= Qg F, where F is frequency.

OUT

To prevent noise problems, bypass VDD to GND with a ceramic capacitor as close to the chip as possible in
parallel with an electrolytic capacitor. Once started and operating properly the V

voltage should be below the

DD

clamp voltage of the device.

Submit Documentation Feedback

(1)

T

5