Texas Instruments UC5605PWP, UC5605N, UC5605DPTR, UC5605DP, UC5605Z Datasheet

• Reverse Disconnect

• Complies with SCSI, SCSI-2

and SPI-2 Standards

• 5pF Channel Capacitance
during Disconnect

• Hot Plugging Capability

•−400mA Sourcing Current for

Termination

• +100mA Sinking Current for
Active Negation

• 1V Dropout Voltage Regulator

• 100µA Supply Current in

Disconnect Mode

• Trimmed Termination Current
to 5%

• Trimmed Impedance to 5%

• Low Thermal Resistance

Surface Mount Packages

The UC5605 pro vi de s 9 l i ne s of ac t i v e te r min ation for a SCSI (Small Computer
Systems Interface) parallel bus. The SCSI standard recommends ac tive termi­nation at both ends of the cable segment.

The only functional differences between the UC5603 and UC5605 is the ab­sence of the negative clamps on the output lines and the disconnect input must
be at a logic-low for the terminating resistors to be disconnected. Parametri­cally, the UC5605 has a 5% tol erance on impedanc e and current compared to
a 3% toleranc e on the UC5603 . Custom power packages are utilized to allow
normal operation at full power (2 Watts).

The UC5605 provides a disconnect feature which, when driven low, discon­nects all terminating resistors, disables the regulator and greatly reduces
standby power consumption. The output channels remain high impedance even
without Termpwr applied. A low channel capacitance of 5pF allows interim
points of the bus to have little to no effect on the signal integrity.

Internal circuit trimming is utilized, first to trim the impedance to a 5% tolerance,
and then most importantly , to trim the output current to a 5% tolerance, as close
to the maximum SCSI specification as possible. This maximizes the noise mar­gin in fast SCSI operati on. Other featu res include thermal shutdown and cur­rent limit.

This device is offered in low therm al resistance versi ons of the industry stand­ard 16 pin nar row body SOI C, 16 pin ZIP (zig-zag in line package) and 24 pin
TSSOP.

UC5605

9-Line Low Capacitance SCSI Active Terminator

FEATURES DESCRIPTION

BLOCK DIAGRAM

Circuit Design Patented

3/97

UDG-94122

ABSOLUTE MAXIMUM RATINGS

Termpwr Vo ltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +7V

Signal Line Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +7V

Regulator Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6A

Storage Temperature . . . . . . . . . . . . . . . . . . . −65°C to +150°C

Operating Temperature . . . . . . . . . . . . . . . . . −55°C to +150°C

Lead Temperature (Soldering, 10 Sec.). . . . . . . . . . . . . +300°C

RECOMMENDED OPERATING CONDITIONS

Termpwr Voltage . . . . . . . . . . . . . . . . . . . . . . . . . 3.8V to 5.25V

Signal Line Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +5V

Disconnect Input Voltage . . . . . . . . . . . . . . . . . . 0V to Termpwr

CONNECTION DIAGRAMS

DIL-16 (Top View)
N or J Package

UC5605

* DP packag e pi n 5 se rves as signal ground; pin s 4, 12, 13
serve as heatsink/ground.

* PWP package pin 9 serves as signal gro und; pins 5, 6, 7, 8,
17, 18, 19, and 20 serve as heatsink/ground.

ZIP-16 (Top View)
Z Package

SOIC-16 (Top View)
DP Package

TSSOP-24 (To p View)
PWP Package

Note: Drawings are not to scale.

Unless otherwise sp ec ified all voltages ar e wit h res pect to
Ground. Currents are positive into, negative out of the speci­fied terminal.
Consult Packaging Section of Unitrode Integrated Circuits dat­abook for thermal limitations and considerations of packages.

2