The UC1524, UC2524 and UC3524 incorporate on a single monolithic chip
all the functions required for the construction of regulating power supplies, in
verters or switching regulators. They can also be used as the control element
for high-power-output applications. The UC1524 family was designed for
switching regulators of either polarity, transformer-coupled dc-to-dc convert
ers, transformerless voltage doublers and polarity converter applications em
ploying fixed-frequency, pulse-width modulation techniques. The dual
alternating outputs allow either single-ended or push-pull applications. Each
device includes an on-chip reference, error amplifier, programmable oscilla
tor, pulse-steering flip-flop, two uncommitted output transistors, a high-gain
comparator, and current-limiting and shut-down circuitry. The UC1524 is
characterized for operation over the full military temperature range of -55°C
to +125°C. The UC2524 and UC3524 are designed for operation from -25°C
to +85°C and 0° to +70°C, respectively.
The UC1524 is a fixed-frequency pulse-width-modulation
voltage regulator control circuit. The regulator operates at
a frequency that is programmed by one timing resistor
), and one timing capacitor (CT), RTestablishes a
(R
T
constant charging current for C
voltage ramp at C
, which is fed to the comparator pro
T
viding linear control of the output pulse width by the error
amplifier. The UC1524 contains an on-board 5V regulator
that serves as a reference as well as powering the
UC1524’s internal control circuitry and is also useful in
supplying external support functions. This reference volt
age is lowered externally by a resistor divider to provide a
reference within the common-mode range of the error
amplifier or an external reference may be used. The
power supply output is sensed by a second resistor di
vider network to generate a feedback signal to the error
amplifier. The amplifier output voltage is then compared
to the linear voltage ramp at C
pulse out of the high-gain comparator is then steered to
. This results in a linear
T
. The resulting modulated
T
the appropriate output pass transistor (Q
1 or Q2)bythe
pulse-steering flip-flop, which is synchronously toggled by
the oscillator output. The oscillator output pulse also
serves as a blanking pulse to assure both outputs are
never on simultaneously during the transition times. The
-
width of the blanking pulse is controlled by the valve of
. The outputs may be applied in a push-pull configura
C
T
tion in which their frequency is half that of the base oscil
lator, or paralleled for single-ended applications in which
the frequency is equal to that of the oscillator. The output
-
of the error amplifier shares a common input to the com
parator with the current limiting and shutdown circuitry
and can be overridden by signals from either of these in
puts. This common point is also available externally and
-
may be employed to control the gain of, or to compen
sate, the error amplifier or to provide additional control to
the regulator.
3
-
-
-
-
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TYPICAL CHARACTERISTICS
UC1524
UC2524
UC3524
Open-loop voltage amplification of error amplifier vs
frequency.
Oscillator frequency vs timing components.
Output saturation voltage vs load current.Output dead time vs timing capacitance value.
4
APPLICATION INFORMATION
Oscillator
UC1524
UC2524
UC3524
Synchronous Operation
The oscillator controls the frequency of the UC1524 and is
programmed by R
and CTaccording to the approximate
T
formula:
1.18
f
′
RC
TT
whereRTis in kΩ
whereC
is in mF
T
wheref is in kHz
Practical values of C
Practical values of R
fall between 0.001mF and 0.1mF.
T
fall between 1.8kΩ and 100kΩ.
T
This results in a frequency range typically from 120Hz to
500kHz.
Blanking
The output pulse of the oscillator is used as a blanking
pulse at the output. This pulse width is controlled by the
value of C
. If small values of CTare required for fre-
T
quency control, the oscillator output pulse width may still
be increased by applying a shunt capacitance of up to
100pF from pin 3 to ground. If still greater dead-time is
required, it should be accomplished by limiting the maximum duty cycle by clamping the output of the error amplifier. This can easily be done with the circuit in Figure 1:
When an external clock is desired, a clock pulse of ap
proximately 3V can be applied directly to the oscillator
output terminal. The impedance to ground at this point is
approximately 2kΩ. In this configuration R
TCT
must be
selected for a clock period slightly greater than that of the
external clock.
If two or more UC1524 regulators are to operated synchro
nously, all oscillator output terminals should be tied to
gether, allC
terminals connectedto single timing
T
capacitor, and the timing resistor connected to a single R
terminal. The other R
to V
the C