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UC1879
Technical data
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TEXAS INSTRUMENTS UC1879, UC2879, UC3879 Technical data

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PHASE SHIFT RESONANT CONTROLLER

FEATURES DESCRIPTION

• Programmable Output Turn On Delay; Zero
Delay Available
• Compatible with Voltage Mode or Current
Mode Topologies
• Practical Operation at Switching Frequencies
to 300 kHz
• 10-MHz Error Amplifier
• Pin Programmable Undervoltage Lockout
• Low Startup Current – 150 µ A
• Soft Start Control
• Outputs Active Low During UVLO

BLOCK DIAGRAM

UC1879 UC2879 UC3879
SLUS230B – JUNE 1998 – REVISED JUNE 2007
Independently programmable time delays provide dead-time at the turn-on of each output stage, allowing time for each resonant switching interval.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright © 1998–2007, Texas Instruments Incorporated
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UC1879 UC2879 UC3879
SLUS230B – JUNE 1998 – REVISED JUNE 2007

DESCRIPTION (CONTINUED)

With the oscillator capable of operating in excess of 600 kHz, overall output switching frequencies to 300 kHz are practical. In addition to the standard free running mode, with the CLKSYNC pin, the user may configure the UC3879 to accept an external clock synchronization signal. Alternatively, up to three units can be locked together with the operational frequency determined by the fastest device.
Protective features include an undervoltage lockout and overcurrent protection. Additional features include a 10-MHz error amplifier, a 5-V precision reference, and soft start. The UC3879 is available in 20 pin N, J, DW, and Q and 28 pin L packages.

ABSOLUTE MAXIMUM RATINGS

PARAMETER VALUE UNIT
Supply voltage (VC, VIN) 20 V Output current, source or sink, dc 20 Output current, source, sink peak for 0.1 µ s at max frequency of 300
kHz Analog inputs
(Pins 1, 2, 3, 4, 5, 6, 14, 15, 17, 18, 19) –0.3 to 5.3 (Pin 16) –0.03 to VIN
Analog outputs
(Pins 7, 8, 12, 13) –0.3 to VCto 0.3 V Storage temperature range –65 ° C to 150 ° C Junction temperature –55 ° C to 150 ° C ° C Lead temperature (soldering, 10 sec) 300°C
(1) Pin references are to 20-pin DIL and SOIC packages. All voltages are with respect to ground unless otherwise stated. Currents are
positive into, negative out of the specified terminal.
(1)
100

THERMAL CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted)
PACKAGE θ
J-20 70-85 28
N-20 80
DW-20 SOIC 45-95
PLCC-20 43-75 CLCC-20 N/A 5-8
(1) θJCdata values stated were derived from MIL-STD-1835B. MIL-STD-1835B states "The baseline values shown are worst case (mean
+2s) for a 60 x 60 mil microcircuit device silicon die and aplicable for devices with die sizes up to 14400 square mils. For devices die
sizes greater than 14400 square mils use the following values; dual-in-line, 11 ° C/W; flat pacl 10 ° C/W; pin grid array, 10 ° C/W".
(2) Specified θJA(junction-to-ambient) is for devices mounted to 5-in
resistance range is given, lower values are for 5-in
trace widths for power packages and 1.3-mm trace widths for non-power packages with a 100 x 100 mil probe land area at the end of
each trace.
(3) θJCestimated for backside of device, through the metalized thermal conduction pads.
2
aluminum PC board. Test PWB was 0.062 in thick and typically used 0.635-mm
JA
(2)
(2) (2)
2
FR4 PC board with one ounce copper wire where noted. When
θ
JC
(1)
35 25 34
(2) (3)
mA
V
2
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RT
RAMP
GND
CLKSYNC
UVSEL
CT
DELSETA-B
OUTA
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
COMP
VREF
OUTC
SS
OUTD
EA–
CS
DELSETC-D
9
10VIN
VC
OUTB
PWRGND
12
11
DIL-20,SOIC-2
JORNPACKAGE,DWPACKAGE
(TOP VIEW)
N/C
N/C
DELSETA-B
CT UVSEL
CLKSYNC
N/C
RT
RAMP
GND
N/C
N/C
VREF
COMP
1
4
3
2
28
27
25
242322 21
20
18
17
16
15
14
13
6
7
111098
EA–
CS
N/C
DELSETC-D
SS
N/C
N/C
OUTD
OUTC
VC
VIN
PWRGND
OUTB
OUTC
CLCC-28
(TOP VIEW)
L PACKAGE
3
18
17
16
DELSETC-D
12
20
19
15
14
4
5
6
7
8
9
13
10
11 12
SS
OUTD
CS EA–
COMP
VREF
GND
RAMP
RT
OUTC
VC
VIN
PWRGND
OUTB
CLKSYNC UVSEL DELSETA-B
OUTA
CT
PLCC-20
QPACKAGE
(TOP VIEW)
SLUS230B – JUNE 1998 – REVISED JUNE 2007
Product Selection Guide
TEMPERATURE RANGE AVAILABLE PACKAGES
UCC1879 –55 ° C to 125 ° C J, L UCC2879 –40 ° C to 85 ° C N, DW, Q, J, L UCC3879 0 ° C to 70 ° C N, DW, Q
UC1879 UC2879 UC3879
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UC1879 UC2879 UC3879
SLUS230B – JUNE 1998 – REVISED JUNE 2007

ELECTRICAL CHARACTERISTICS

Unless specified; VC = VIN = V = 0.01 µ F, TA= TJ.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Undervoltage Lockout
Start threshold
UVLO hysteresis
Input bias, UVSEL pin V
Supply Current
I
startup 150 600
VIN
IVCstartup 10 100
I
operating
VIN
IVCoperating 4 8
Voltage Reference
Output voltage TJ= 25 ° C 4.92 5 5.08 V Line regulation 11 V < VIN < 18 V 1 10 Load regulation I Total variation Line, Load, Temperature 4.875 5.125 V Short circuit current VREF = 0 V, TJ= 25 ° C –60 –15 mA
Error Amplifier
Error amplifier input voltage 2.4 2.5 2.6 V Input bias current 0.6 3 µ A AVOL 1 V < VCOMP < 4 V 60 90 PSRR 11 V < VIN < 18 V 85 100 Output sink current V Output source current V Output voltage high I Output voltage low I Slew rate TA= 25 ° C 6 11 V/ µ s
= 12 V, CT = 470 pF, RT = 9.53k, R
UVSEL
V
= VIN 9 10.75 12.5
UVSEL
V
= Open 12.5 15.25 16.5
UVSEL
V
= VIN 1.15 1.75 2.15
UVSEL
V
= Open 5.2 6 7.4
UVSEL
= VIN = 8 V 30 µ A
UVSEL
VIN = V I
DELSETA-B
VIN = V I
DELSETA-B
UVSEL
= I
UVSEL
= I
= 8 V, VC = 18 V,
DELSETC-D = 0
= 8 V, VC = 18 V,
DELSETC-D = 0
UC3879, UC2879 23 35 UC1879 23 36 mA
= –10 mA 5 20
VREF
= 1 V 1 2.5
COMP
= 4 V –1.3 –0.5
COMP
= –0.5 mA 4 4.7 5
COMP
= 1 mA 0 0.5 1
COMP
DELSETA-B
= R
DELSEC-D
= 4.8k, C
DELSETA-B
= C
DELSETC-D
V
µ A
mV
dB
mA
V
4
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200
%
T
q = f
SLUS230B – JUNE 1998 – REVISED JUNE 2007
ELECTRICAL CHARACTERISTICS (continued)
Unless specified; VC = VIN = V = 0.01 µ F, TA= TJ.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
PWM Comparator
RAMP offset voltage TJ= 25 ° C PWM phase shift,
T
DELSETA-B
, T
DELSETC-D
Output skew, T
DELSETA-B
, T
DELSETC-D
Ramp to output delay, T
DELSETA-B
= 0, T
DELSETC-D
Oscillator
Initial accuracy TA= 25 ° C 180 200 220 kHz Voltage stability 11 V < VIN < 18 V 1 2 % Total variation Line, Temperature 160 200 240 kHz CLKSYNC threshold 2.3 2.5 2.7 Clock out high 2.8 4 V Clock out low 0.5 1 1.5 Clock out pulse width 400 600 ns Ramp valley voltage 0.2 0.4 Ramp peak voltage 2.8 2.9 3.2
Current Limit
Input bias V Threshold voltage 2.35 2.5 2.65 V Delay to OUTA, B, C, D 160 300 ns
Cycle-by-Cycle Current Limit
Input bias V Threshold voltage 1.85 2 2.15 V Delay to output zero phase 110 300 ns
(1) Ramp offset voltage has a temperature coefficient of about –4 mV/ ° C.
(2)
= 0
(2)
= 0
= 0
= 12 V, CT = 470 pF, RT = 9.53k, R
UVSEL
(1)
V
> V
COMP
V
COMP
V
COMP
V
COMP
RAMPpeak
< Zero Phase Shift Voltage 0% 0.3% 2%
> V
RAMPpeak
< Zero Phase Shift Voltage 10 UC3879, UC2879 115 250 UC1879 115 300
= 3 V 2 10 µ A
CS
= 2.2 V 2 10 µ A
CS
DELSETA-B
= R
DELSEC-D
= 4.8k, C
DELSETA-B
1.1 1.25 1.4 V
+ V
RAMPoffset
+ V
RAMPoffset
98% 99.7% 102%
10
UC1879 UC2879 UC3879
= C
DELSETC-D
ns
V
(2) Phase shift percentage (0% = 0 , 100% = 180 ) is defined as
where is the phase shift, and and T are defined in Figure 1 . At 0% phase shift, is the output skew.
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