Improved Current Mode PWM Controller
DESCRIPTIONFEATURES
• Pin-for-Pin Compatible With the UC3846
• 65ns Typical Delay From Shutdown to
Outputs, and 50ns Typical Delay From
Sync to Outputs
• Improved Current Sense Amplifier With
Reduced Noise Sensitivity
• Differential Current Sense with 3V
Common Mode Range
• Trimmed Oscillator Discharge Current
for Accurate Deadband Control
• Accurate 1V Shutdown Threshold
• High Current Dual Totem Pole Outputs
(1.5A peak)
• TTL Compatible Oscillator SYNC Pin
Thresholds
The UC3856 is a high performance version of the popular UC3846
series of current mode controllers, and is intended for both design
upgrades and new applications where speed and accuracy are important. All input to output delays have been minimized, and the current
sense output is slew rate limited to reduce noise sensitivity. Fast 1.5A
peak output stages have been added to allow rapid switching of
power FETs.
A low impedance TTL compatible sync output has been implemented
with a tri-state function when used as a sync input.
Internal chip grounding has been improved to minimize internal
“noise” caused when dr iving large capacitive loads. This, in conjunction with the improved differential current sense amplifier results in
enhanced noise immunity.
Other features include a trimmed oscillator current (8%) for accurate
frequency and dead time control; a 1V, 5% shutdown threshold; and
4kV minimum ESD protection on all pins.
UC1856
UC2856
UC3856
• 4kV ESD Protection
BLOCK DIAGRAM
9/96
UDG-96176
ABSOLUTE MAXIMUM RATINGS
Supply V oltage....................................................................+40V
Collector Supply Voltage.....................................................+40V
Output Current, Source or Sink
DC...................................................................................0.5A
Pulse (0.5µs)...................................................................2.0A
Error Amp Inputs....................................................−0.3V to +VIN
Shutdown Input.....................................................−0.3V to +10V
Current Sense Inputs..............................................−0.3V to +3V
SYNC Output Current......................................................±10mA
Error Amplifier Output Current...........................................−5mA
Soft Start Sink Current.......................................................50mA
Oscillator Charging Current .................................................5mA
Power Dissipation at TA = 25°C (Note 2).......................1000mW
Power Dissipation at TC = 25°C (Note 2) ......................2000mW
Junction Temperature.......................................−55°C to +150°C
Storage Temperature Range............................−65°C to +150°C
Lead Temperature (Soldering, 10 sec.)...........................+300°C
All voltages are with respect to Ground.Currents are positive
into, negative out of the specified terminal.Consult packaging
section of databook for thermal limitations and considerations of
package.
UC1856
UC2856
UC3856
CONNECTION DIAGRAMS
DIL–16,SOIC-16 (Top View)
J or N,DW PACKAGE
PLCC-28 (Top View)
QP PACKAGE
PLCC-20 (Top View)
Q PACKAGE
ELECTRICAL CHARACTERISTICS Unless otherwise stated, these specifications apply for TA = −55°C to +125°C for
UC1856;− 40°C to +85°C for the UC2856;and 0°C to +70°C for the UC3856, VIN
PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Reference Section
Output V oltage TJ = 25°C, Io = 1mA 5.05 5.10 5.15 5.00 5.10 5.20 V
Line Regulation VIN = 8V to 40V 20 20 mV
Load Regulation Io =−1mA to −10mA 15 15 mV
Total Output Variation Line, Load, and Temperature 5.00 5.20 4.95 5.25 V
Output Noise Voltage 10Hz < f < 10kHz, TJ = 25°C 50 50 µV
Long T erm Stability TJ = 125°C, 1000 Hrs (Note 2) 5 25 5 25 mV
Short Circuit Current VREF = 0V −25 −45 −65 −25 −45 −65 mA
Oscillator Section
Initial Accuracy TJ = 25°C 180 200 220 180 200 220 kHz
Over Operating Range 170 230 170 230 kHz
= 15V, RT = 10k, CT = 1nF , TA= TJ.
UC1856/UC2856 UC3856
2
UC1856
UC2856
UC3856
ELECTRICAL CHARACTERISTICS (cont.)
+125°C for UC1856;− 40°C to +85°C for the UC2856;and 0°C to +70°C for the UC3856, VIN
PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Oscillator Section (cont.)
Voltage Stability VIN = 8V to 40V 2 2 %
Discharge Current TJ = 25°C, VCT = 2V 7.5 8.0 8.8 7.5 8.0 8.8 mA
VCT = 2V 6.7 8.0 8.8 6.7 8.0 8.8 mA
Sync Output High Level Io =−1mA 2.4 3.6 2.4 3.6 V
Sync Output Low Level Io =+1mA 0.2 0.4 0.2 0.4 V
Sync Input High Level CT = 0V, RT = VREF 2.0 1.5 2.0 1.5 V
Sync Input Low Level CT = 0V, RT =VREF 1.5 0.8 1.5 0.8 V
Sync Input Current CT = 0V, RT = VREF 1 10 1 10 µA
VSYNC = 5V
Sync Delay to Outputs CT = 0V, RT =VREF 50 100 50 100 ns
VSYNC = 0.8V to 2V
Error Amplifier Section
Input Offset Voltage VCM = 2V 5 10 mV
Input Bias Current −1 −1 µA
Input Offset Current 500 500 nA
Common Mode Range VIN = 8V to 40V 0 VIN − 2 0 VIN − 2V
Open Loop Gain Vo = 1.2V to 3V 80 100 80 100 dB
Unity Gain Bandwidth TJ = 25°C 1 1.5 1 1.5 MHz
CMRR VCM = 0V to 38V, VIN = 40V 75 100 75 100 dB
PSRR VIN = 8V to 40V 80 100 80 100 dB
Output Sink Current VID =−15mV, VcOMP = 1.2V 5 10 5 10 mA
Output Source Current VID = 15mV, VCOMP = 2.5V −0.4 −0.5 −0.4 −0.5 mA
Output High Level VID = 50mV, RL (COMP) = 15k 4.3 4.6 4.9 4.3 4.6 4.9 V
Output Low Level VID =−50mV, RL (COMP) = 15k 0.7 1 0.7 1 V
Current Sense Amplifier Section
Amplifier Gain VCS−=0V, CL SS Open (Notes 3,4) 2.5 2.75 3.0 2.5 2.75 3.0 V/V
Maximum Differential CL SSOpen (Note 3) 1.1 1.2 1.1 1.2 V
Input Signal (VCS+− Vcs-) RL (COMP) = 15k
Input Offset Voltage V
CMRR VCM = 0V to 3V 60 60 dB
PSRR VIN = 8V to 40V 60 60 dB
Input Bias Current VCL SS = 0.5V, COMP Open (Note 3) −1 −3 −1 −3 µA
Input Offset Current VCL SS = 0.5V, COMP Open (Note 3) 1 1 mA
Input Common Mode Range 0 3 0 3 V
Delay to Outputs V
Current Limit Adjust Section
Current Limit Offset V
Input Bias Current VEA+ =VREF, VEA−=0V −10 −30 −10 −30 µA
Shutdown T erminal Section
Threshold V oltage 0.95 1.00 1.05 0.95 1.00 1.05 V
Input V oltage Range 0 5 0 5 V
CL SS = 0.5V 5 35 5 35 mV
COMP Open (Note 3)
EA+ = VREF, EA−=0V 120 250 120 250 ns
CS+ − CS−=0V to 1.5V
CS- = 0V 0.43 0.5 0.57 0.43 0.5 0.57 V
VCS+ = 0V, COMP = Open (Note 3)
Unless otherwise stated, these specifications apply for TA = −55°C to
= 15V, RT = 10k, CT = 1nF , TA= TJ.
UC1856/UC2856 UC3856
3
UC1856
UC2856
UC3856
ELECTRICAL CHARACTERISTICS (cont.) Unless otherwise stated, these specifications apply for TA = −55°C to
+125°C for UC1856;− 40°C to +85°C for the UC2856;and 0°C to +70°C for the UC3856, VIN
UC1856/UC2856 UC3856
PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX UNITS
Shutdown Terminal Section (cont.)
Minimum Latching (Note 5) 3 1.5 3 1.5 mA
Current (ICL SS)
Maximum Non-Latching (Note 6) 1.5 0.8 1.5 0.8 mA
Current (ICL SS)
Delay to Outputs VSHUTDOWN = 0 to 1.3V 65 110 65 110 ns
Output Section
Collector-Emitter V oltage 40 40 V
Off-State Bias Current VC = 40V 250 250 µA
Output Low Level IOUT = 20mA 0.1 0.5 0.1 0.5 V
IOUT = 200mA 0.5 2.6 0.5 2.6 V
Output High Level IOUT =−20mA 12.5 13.2 12.5 13.2 V
IOUT =−200mA 12 13.1 12 13.1 V
Rise Time C1 = 1nF 40 80 40 80 ns
Fall Time C1 = 1nF 40 80 40 80 ns
UVLO Low Saturation VIN = 0V, IOUT = 20mA 0.8 1.5 0.8 1.5 V
PWM Section
Maximum Duty Cycle 45 47 50 45 47 50 %
Minimum Duty Cycle 0 0 %
Undervoltage Lockout Section
Startup Threshold 7.7 8.0 7.7 8.0 V
Threshold Hysterisis 0.7 0.7 V
Total Standby Current
Supply Current 18 23 18 23 mA
Note 1: All voltages are with respect to GND.Currents are positive into, negative out of the specified terminal.
Note 2: This parameter, although guaranteed over the recommended operating conditions is not 100% tested in production.
Note 3: Parameter measured at trip point of latch with V
Note 4: Amplifier gain defined as:
G
∆
V
COMP
=
∆
VCS+
;
+ =VREF, V
EA
-=
0V.
∆
V
CS
−=
0V to 1.0V
EA
Note 5: Current into CL SS guaranteed to latch circuit into shutdown state.
Note 6: Current into CL SS guaranteed not to latch circuit into shutdown state.
= 15V, RT = 10k, CT = 1nF , TA= TJ.
4
APPLICATIONS INFORMATION
Output deadtime is determined by size of the external capacitor, CT, according to the formula:Td =
For large values of R
Oscillator frequency is approximated by the formula:fT =
T:Td = 250CT
Oscillator Circuit
2
RT CT
2C
T
3.6
8mA −........
R
UC1856
UC2856
UC3856
T
UDG-96177
Error Amplifier Output Configuration
Error Amplifier can source up to 0.5mA.
Error Amplifier Open-Loop D.C.Gain vs
110
100
Error Amplifier Gain and Phase vs Frequency
80
VIN=20V
TJ =25
60
40
20
0
OPEN-LOOP VOLTAGE GAIN (dB)
100 1k 10k 100k 1M
FREQUENCY (Hz)
UDG-96178 UDG-96179
OPEN-LOOP PHASE
o
o
0
o
-90
o
-180
Load Resistance
VIN=20V
o
TJ =25
90
80
OPEN-LOOP VOLTAGE GAIN (dB)
70
0
10 20 30 40 50 60 70 80 90 100
OUTPUT LOAD RESISTANCE RL (k-OHMS)
UDG-96180
5
APPLICATIONS INFORMATION (cont.)
UC1856
UC2856
UC3856
Parallel Operation
Slaving allows parallel operation of two or more units with equal current sharing.
Pulse by Pulse Current Limiting
Peak current (IS) is determined by the formula:IS =
R2 VREF
( )
R1 + R2
3R
−0.5
S
UDG-96181
UDG-96182
6
APPLICATIONS DATA (cont.)
UC1856
UC2856
UC3856
UDG-96183
VREF
If < 0.8mA, the shutdown latch will commutate
R1
SS = 0.8mA and a restart cycle will be initiated.
when I
Current Sense Amplifier Connections
A small RC filter may be required in some applications to reduce switch transients.
Differential input allows remote, noise sensing.
VREF
If > 3mA, the device will latch off until power is
R1
recycled.
7
UDG-96184
UDG-96185
APPLICATIONS INFORMATION (cont.)
UC1856 Open Loop Test Circuit
UC1856
UC2856
UC3856
UNITRODE INTEGRATED CIRCUITS
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL.603-424-2410 • FAX 603-424-3460
- BYPASS CAPS SHOULD BE LOW ESR & ESL TYPE
- SHORT E/A- & COMP FOR UNITY GAIN TESTING
THE USE OF A GROUND PLANE IS HIGHLY RECOMMENDED
UDG-96186
8
PACKAGE OPTION ADDENDUM
www.ti.com
20-Dec-2007
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
5962-9453001M2A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
5962-9453001MEA ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type
UC1856J ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type
UC1856J883B ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type
UC1856L OBSOLETE TO/SOT L 28 TBD Call TI Call TI
UC1856L20 ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
UC1856L20883B ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
UC1856L883B OBSOLETE TO/SOT L 28 TBD Call TI Call TI
UC2856DW ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br)
UC2856DWG4 ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br)
UC2856DWTR ACTIVE SOIC DW 16 2000 Green (RoHS &
no Sb/Br)
UC2856DWTRG4 ACTIVE SOIC DW 16 2000 Green (RoHS &
no Sb/Br)
UC2856J ACTIVE CDIP J 16 1 TBD A42 SNPB N / A for Pkg Type
UC2856N ACTIVE PDIP N 16 25 Green (RoHS &
no Sb/Br)
UC2856NG4 ACTIVE PDIP N 16 25 Green (RoHS &
no Sb/Br)
UC3856DW ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br)
UC3856DWG4 ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br)
UC3856DWTR ACTIVE SOIC DW 16 2000 Green (RoHS &
no Sb/Br)
UC3856DWTRG4 ACTIVE SOIC DW 16 2000 Green (RoHS &
no Sb/Br)
UC3856N ACTIVE PDIP N 16 25 Green (RoHS &
no Sb/Br)
UC3856NG4 ACTIVE PDIP N 16 25 Green (RoHS &
no Sb/Br)
UC3856Q ACTIVE PLCC FN 20 46 Green (RoHS &
no Sb/Br)
UC3856QG3 ACTIVE PLCC FN 20 46 Green (RoHS &
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU N / A for Pkg Type
CU NIPDAU N / A for Pkg Type
CU SN Level-2-260C-1 YEAR
CU SN Level-2-260C-1 YEAR
(3)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
20-Dec-2007
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
TAPE AND REEL INFORMATION
11-Mar-2008
*All dimensions are nominal
Device Package
UC2856DWTR SOIC DW 16 2000 330.0 16.4 10.85 10.8 2.7 12.0 16.0 Q1
UC3856DWTR SOIC DW 16 2000 330.0 16.4 10.85 10.8 2.7 12.0 16.0 Q1
Type
Package
Drawing
Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm)W(mm)
Pin1
Quadrant
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UC2856DWTR SOIC DW 16 2000 346.0 346.0 33.0
UC3856DWTR SOIC DW 16 2000 346.0 346.0 33.0
Pack Materials-Page 2
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