PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SLES241B
September 2009–Revised June 2010
TVP5151
SLES241B–SEPTEMBER 2009–REVISED JUNE 2010
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Contents
1TVP5151 Features ............................................................................................................... 7
• Fully Differential CMOS Analog Preprocessing
Channels With Clamping and Automatic Gain• Advanced Programmable Video Output
Control (AGC) for Best Signal-to-Noise (S/N)Formats
Performance
• Ultralow Power ConsumptionInterval (VBI) Data During Active Video
• 48-Terminal PBGA Package (ZQC) or– Sliced VBI Data During Horizontal Blanking
32-Terminal TQFP Package (PBS)or Active Video
• Power-Down Mode: <1 mW• VBI Modes Supported
• Brightness, Saturation, Hue, and Sharpness– Teletext (NABTS, WST)
Control Through I2C
• Complementary 4-Line (3-H Delay) AdaptiveExtended Data Services (XDS)
Comb Filters for Both Cross-Luminance and
Cross-Chrominance Noise Reduction
• Patented Architecture for Locking to Weak,Code
Noisy, or Unstable Signals
• Single 27.000-MHz Crystal for All StandardsCompatible Mode
• Internal Phase-Locked Loop (PLL) for– Custom Configuration Mode That Allows
Line-Locked Clock and SamplingUser to Program Slice Engine for Unique VBI
• Subcarrier Genlock Output for Synchronizing
Color Subcarrier of External Encoder• Power-On Reset
• Variable Digital I/O Supply Voltage Range from• Industrial Temperature Range (TVP5151I):
1.8 V to 3.3 V–40°C to 85°C
<br>
<br>
• Standard Programmable Video Output Formats
– ITU-R BT.656, 8-Bit 4:2:2 With Embedded
Syncs
– 8-Bit 4:2:2 With Discrete Syncs
• Macrovision™ Copy Protection Detection
– 2× Oversampled Raw Vertical Blanking
– Closed-Caption Decode With FIFO and
– Wide Screen Signaling, Video Program
System, CGMS-A, Vertical Interval Time
– Gemstar 1x/2x Electronic Program Guide
Data Signals
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
The TVP5151 device is an ultralow-power NTSC/PAL/SECAM video decoder. Available in a space-saving
48-terminal PBGA package or a 32-terminal TQFP package, the TVP5151 decoder converts NTSC, PAL,
and SECAM video signals to 8-bit ITU-R BT.656 format. Discrete syncs are also available. The optimized
architecture of the TVP5151 decoder allows for ultralow power consumption. The decoder consumes
138-mW power under typical operating conditions and consumes less than 1 mW in power-down mode,
considerably increasing battery life in portable applications. The decoder uses just one crystal for all
supported standards. The TVP5151 decoder can be programmed using an I2C serial interface.
The TVP5151 decoder converts baseband analog video into digital YCbCr 4:2:2 component video.
Composite and S-video inputs are supported. The TVP5151 decoder includes one 9-bit analog-to-digital
converter (ADC) with 2× sampling. Sampling is ITU-R BT.601 (27.0 MHz, generated from the 27.000-MHz
crystal or oscillator input) and is line locked. The output formats can be 8-bit 4:2:2 or 8-bit ITU-R BT.656
with embedded synchronization.
The TVP5151 decoder utilizes Texas Instruments patented technology for locking to weak, noisy, or
unstable signals. A Genlock/real-time control (RTC) output is generated for synchronizing downstream
video encoders.
Complementary four-line adaptive comb filtering is available for both the luminance and chrominance data
paths to reduce both cross-luminance and cross-chrominance artifacts; a chrominance trap filter is also
available.
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Video characteristics including hue, brightness, saturation, and sharpness may be programmed using the
industry standard I2C serial interface. The TVP5151 decoder generates synchronization, blanking, lock,
and clock signals in addition to digital video outputs. The TVP5151 decoder includes methods for
advanced vertical blanking interval (VBI) data retrieval. The VBI data processor slices, parses, and
performs error checking on teletext, closed caption, and other data in several formats.
The TVP5151 decoder detects copy-protected input signals according to the Macrovision™ standard and
detects Type 1, 2, 3, and colorstripe processes.
The main blocks of the TVP5151 decoder include:
•Robust sync detector
•ADC with analog processor
•Y/C separation using four-line adaptive comb filter
•Chrominance processor
•Luminance processor
•Video clock/timing processor and power-down control
The following is a partial list of suggested applications:
•Digital televisions
•PDAs
•Notebook PCs
•Cell phones
•Video recorder/players
•Internet appliances/web pads
•Handheld games
•Surveillance
•Portable navigation
•Portable video projectors
2.3Related Products
•TVP5150AM1
•TVP5154A
•TVP5146M2
•TVP5147M1
•TVP5158
SLES241B–SEPTEMBER 2009–REVISED JUNE 2010
2.4Trademarks
TI and MicroStar Junior are trademarks of Texas Instruments.
Macrovision is a trademark of Macrovision Corporation.
Gemstar is a trademark of Gemstar-TV Guide International.
Other trademarks are the property of their respective owners.
2.5Document Conventions
Throughout this data manual, several conventions are used to convey information. These conventions are:
•To identify a binary number or field, a lower case b follows the numbers. For example, 000b is a 3-bit
binary field.
•To identify a hexadecimal number or field, a lower case h follows the numbers. For example, 8AFh is a
12-bit hexadecimal field.
•All other numbers that appear in this document that do not have either a b or h following the number
are assumed to be decimal format.
•If the signal or terminal name has a bar above the name (for example, RESETB), this indicates the
logical NOT function. When asserted, this signal is a logic low, 0, or 0b.
•RSVD indicates that the referenced item is reserved.
The TVP5151 video decoder is packaged in a 48-terminal PBGA package or a 32-terminal TQFP
package. Figure 2-2 shows the terminal diagrams for both packages. Table 2-1 gives a description of the
terminals.
AIP1AA11Irange is 0-0.75 VPP, and may require an attenuator to reduce the input amplitude to the
AIP1BB12Irange is 0-0.75 VPP, and may require an attenuator to reduce the input amplitude to the
CH_AGNDA331GAnalog ground
CH_AVDDA232PAnalog supply. Connect to 1.8-V analog supply.
NC––No connect
PLL_AGNDC23GPLL ground. Connect to analog ground.
PLL_AVDDC14PPLL supply. Connect to 1.8-V analog supply.
REFMA430O
REFPB429O
XTAL1/OSCD25I
XTAL2D16O
Digital Section
NO.I/ODESCRIPTION
ZQCPBS
Analog input. Connect to the video analog input via 0.1-µF capacitor. The maximum input
desired level. If not used, connect to AGND via a 0.1-µF capacitor (see Figure 6-1).
Analog input. Connect to the video analog input via 0.1-µF capacitor. The maximum input
desired level. If not used, connect to AGND via a 0.1-µF capacitor (see Figure 6-1).
B2, B3,
B6, C4,
C5,
D3–D6,
E2–E5,
F2, F5, F6
A/D reference negative output. Connect to analog ground through a 1-µF capacitor. Also, it
is recommended to connect directly to REFP through a 1-µF capacitor (see Figure 6-1).
A/D reference positive output. Connect to analog ground through a 1-µF capacitor (see
Figure 6-1).
External clock reference input. Connect to analog ground if an external single-ended
oscillator is connected to AVID/CLK_IN pin.
External clock reference output. Not connected if XTAL1 or CLK_IN is driven by an external
single-ended oscillator.
Active video indicator output/external clk input
When XTAL1 is used as a reference clock and this terminal is left unconnected, this
terminal is internally pulled down.
AVID/CLK_INA626I/O
DGNDE619GDigital ground
DVDDE720PDigital supply. Connect to 1.8-V digital supply.
FID/GLCOC623OGLCO: This serial output carries color PLL information. A slave device can decode the
HSYNCA725OHorizontal synchronization signal
INTREQ/GPCL/
VBLK
B527O
When XTAL1 is used as a reference clock and AVID output is required, this pin must be
low until terminal is configured as an output. This may be dependent on external circuitry
connected to this terminal.
When XTAL 1 is connected to ground, CLK_IN may be connected to an external
single-ended oscillator from a 1.8-V to 3.3-V compatible clock signal depending on
IO_DVDD voltage.
FID: Odd/even field indicator or vertical lock indicator. For the odd/even indicator, a 1
indicates the odd field.
information to allow chrominance frequency control from the TVP5151 decoder. Data is
transmitted at the SCLK rate in Genlock mode. In RTC mode, SCLK/4 is used.
INTREQ: Interrupt request output
GPCL/VBLK: General-purpose control logic. This terminal has two functions:
•GPCL: General-purpose output. In this mode the state of GPCL is directly programmed
via I2C.
•VBLK: Vertical blank output. In this mode the GPCL terminal indicates the vertical
blanking interval of the output video. The beginning and end times of this signal are
programmable via I2C.
IO_DVDDG210PDigital output supply, 1.8 V to 3.3 V
PCLK/SCLKG19OSystem clock at either 1× or 2× the frequency of the pixel clock.
PDNA528I
RESETBF18I
SCLD721I/OI2C serial clock (open drain)
SDAC722I/OI2C serial data (open drain)
VSYNC/PALIB724O
YOUT[6:0]G515OITU-R BT.656 output/YCbCr 4:2:2 output with discrete syncs
YOUT7/I2CSELF311I/O
NO.I/ODESCRIPTION
ZQCPBS
Power-down terminal (active low). Puts the decoder in standby mode. Preserves the value
of the registers.
Active-low reset. RESETB can be used only when PDN = 1. When RESETB is pulled low, it
resets all the registers and restarts the internal microprocessor.
VSYNC: Vertical synchronization signal
PALI: PAL line indicator or horizontal lock indicator. For the PAL line indicator:
1 = Noninverted line
0 = Inverted line
G312
F413
G414
G616
G717
F718
I2CSEL: Determines address for I2C (sampled during reset). A pullup or pulldown resistor is
needed (>1 kΩ) to program the terminal to the desired address.
1 = Address is BAh
0 = Address is B8h
YOUT7: Most significant bit (MSB) of ITU-R BT.656 output/YCbCr 4:2:2 output
The TVP5151 decoder has an analog input channel that accepts two video inputs that are ac-coupled.
The decoder supports a maximum input voltage range of 0.75 V; therefore, an attenuation of one-half is
needed for most input signals with a peak-to-peak variation of 1.5 V. The nominal parallel termination
before the input to the device is recommended to be 75 Ω. See the application diagram in Figure 6-1 for
the recommended configuration. The two analog input ports can be connected as follows:
•Two selectable composite video inputs, or
•One S-video input
An internal clamping circuit restores the sync-tip of the ac-coupled video signal to a fixed dc level.
The programmable gain amplifier (PGA) and the automatic gain control (AGC) algorithm work together to
make sure that the input signal is amplified sufficiently to ensure the proper input range for the ADC.
The ADC has nine bits of resolution and runs at a nominal speed of 27 MHz. The clock input for the ADC
comes from the horizontal PLL.
3.2Composite Processing Block Diagram
The composite processing block processes NTSC/PAL/SECAM signals into the YCbCr color space.
Figure 3-1 shows the basic architecture of this processing block.
SLES241B–SEPTEMBER 2009–REVISED JUNE 2010
Figure 3-1 shows the luminance/chrominance (Y/C) separation process in the TVP5151 decoder. The
composite video is multiplied by subcarrier signals in the quadrature modulator to generate the color
difference signals Cb and Cr. Cb and Cr are then low pass (LP) filtered to achieve the desired bandwidth
and to reduce crosstalk.
An adaptive four-line comb filter separates CbCr from Y. Chrominance is remodulated through another
quadrature modulator and subtracted from the line-delayed composite video to generate luminance.
Brightness, hue, saturation, and sharpness (using the peaking filter) are programmable via I2C.
The Y/C separation is bypassed for S-video input. For S-video, the remodulation path is disabled.
The four-line comb filter can be selectively bypassed in the luminance or chrominance path. If the comb
filter is bypassed in the luminance path, then chrominance trap filters are used which are shown in
Figure 3-2 and Figure 3-3. TI's patented adaptive four-line comb filter algorithm reduces artifacts such as
hanging dots at color boundaries and detects and properly handles false colors in high-frequency
luminance images such as a multiburst pattern or circle pattern.
Response, NTSC ITU-R BT.601 SamplingResponse, PAL ITU-R BT.601 Sampling
3.4Color Low-Pass Filter
In some applications, it is desirable to limit the Cb/Cr bandwidth to avoid crosstalk. This is especially true
in case of video signals that have asymmetrical Cb/Cr sidebands. The color LP filters provided limit the
bandwidth of the Cb/Cr signals.
Color LP filters are needed when the comb filtering turns off, due to extreme color transitions in the input
image. See Section 3.21.25, Chrominance Control #2 Register, for the response of these filters. The filters
have three options that allow three different frequency responses based on the color frequency
characteristics of the input video as shown in Figure 3-4.
Figure 3-4. Color Low-Pass Filter with Filter Characteristics, NTSC/PAL ITU-R BT.601 Sampling
The luminance component is derived from the composite signal by subtracting the remodulated
chrominance information. A line delay exists in this path to compensate for the line delay in the adaptive
comb filter in the color processing chain. The luminance information is then fed into the peaking circuit,
which enhances the high frequency components of the signal, thus improving sharpness.
3.6Chrominance Processing
For NTSC/PAL formats, the color processing begins with a quadrature demodulator. The Cb/Cr signals
then pass through the gain control stage for chrominance saturation adjustment. An adaptive comb filter is
applied to the demodulated signals to separate chrominance and eliminate cross-chrominance artifacts.
An automatic color killer circuit is also included in this block. The color killer suppresses the chrominance
processing when the color burst of the video signal is present. The SECAM standard is similar to PAL
except for the modulation of color which is FM instead of QAM.
3.7Timing Processor
The timing processor is a combination of hardware and software running in the internal microprocessor
that serves to control horizontal lock to the input sync pulse edge, AGC and offset adjustment in the
analog front end, vertical sync detection, and Macrovision detection.
3.8VBI Data Processor (VDP)
The TVP5151 VDP slices various data services such as teletext (WST, NABTS), closed captioning (CC),
wide screen signaling (WSS), etc. These services are acquired by programming the VDP to enable
standards in the VBI. The results are stored in a FIFO and/or registers. The teletext results are stored only
in a FIFO. Table 3-1 lists a summary of the types of VBI data supported according to the video standard. It
supports ITU-R BT. 601 sampling for each.
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LINE MODE REGISTER
(D0h–FCh) BITS [3:0]
0000bWST SECAMTeletext, SECAM
0001bWST PAL BTeletext, PAL, System B
0010bWST PAL CTeletext, PAL, System C
0011bWST, NTSC BTeletext, NTSC, System B
0100bNABTS, NTSC CTeletext, NTSC, System C
0101bNABTS, NTSC DTeletext, NTSC, System D (Japan)
0110bCC, PALClosed caption PAL
0111bCC, NTSCClosed caption NTSC
1000bWSS/CGMS-AWide-screen signaling/Copy Generation Management System-Analog, PAL
1001bWSS/CGMS-AWide-screen signaling/Copy Generation Management System-Analog, NTSC
1010bVITC, PALVertical interval timecode, PAL
1011bVITC, NTSCVertical interval timecode, NTSC
1100bVPS, PALVideo program system, PAL
1101bGemstar 2x Custom 1Electronic program guide
1110bReservedReserved
1111bActive VideoActive video/full field
At power-up the host interface is required to program the VDP-configuration RAM (VDP-CRAM) contents
with the lookup table (see Section 3.21.58). This is done through port address C3h. Each read from or
write to this address auto increments an internal counter to the next RAM location. To access the
VDP-CRAM, the line mode registers (D0h to FCh) must be programmed with FFh to avoid a conflict with
the internal microprocessor and the VDP in both writing and reading. Full field mode must also be
disabled.
Available VBI lines are from line 6 to line 27 of both field 1 and field 2. Each line can be any VBI mode.
Output data is available either through the VBI-FIFO (B0h) or through dedicated registers at 90h to AFh,
both of which are available through the I2C port.
3.9VBI FIFO and Ancillary Data in Video Stream
Sliced VBI data can be output as ancillary data in the video stream in the ITU-R BT.656 mode. VBI data is
output during the horizontal blanking period following the line from which the data was retrieved. Table 3-2
shows the header format and sequence of the ancillary data inserted into the video stream. This format is
also used to store any VBI data into the FIFO. The size of FIFO is 512 bytes. Therefore, the FIFO can
store up to 11 lines of teletext data with the NTSC NABTS standard.
Table 3-2. Ancillary Data Format and Sequence
BYTE NO.D6D5D4D3D2D1DESCRIPTION
000000000
111111111Ancillary data preamble
211111111
3NEPEP010DID2DID1DID0Data ID (DID)
4NEPEPF5F4F3F2F1F0Secondary data ID (SDID)
5NEPEPN5N4N3N2N1N0Number of 32-bit data (NN)
6Video line [7:0]Internal data ID0 (IDID0)
7000Match 1 Match 2Video line [9:8]Internal data ID1 (IDID1)
81. DataData byte
EP:Even parity for D0–D5
NEP:Negated even parity
DID:91h: Sliced data of VBI lines of first field
SDID:This field holds the data format taken from the line mode register of the corresponding line.
NN:Number of Dwords beginning with byte 8 through 4(N+2). This value is the number of
IDID0:Transaction video line number [7:0]
D7D0
(MSB)(LSB)
Data
error
m–1. DataData byte
m. DataData byte
RSVDCS[5:0]Check sum
53h: Sliced data of line 24 to end of first field
55h: Sliced data of VBI lines of second field
97h: Sliced data of line 24 to end of second field
IDID1:Bit 0/1 = Transaction video line number [9:8]
Bit 2 = Match 2 flag
Bit 3 = Match 1 flag
Bit 4 = 1 if an error was detected in the EDC block; 0 if not
CS:Sum of D0–D7 of DID through last data byte.
Fill byte:Fill bytes make a multiple of 4 bytes from byte 0 to last fill byte.
3.10 Raw Video Data Output
The TVP5151 decoder can output raw A/D video data at 2x sampling rate for external VBI slicing. This is
transmitted as an ancillary data block during the active horizontal portion of the line and during vertical
blanking.
3.11 Output Formatter
The YCbCr digital output can be programmed as 8-bit 4:2:2 or 8-bit ITU-R BT.656 parallel interface
standard.
Table 3-3. Summary of Line Frequencies, Data Rates, and Pixel Counts
A.AVID rising edge occurs four SCLK cycles early when in the ITU-R BT.656 output mode.
Figure 3-6. Horizontal Synchronization Signals
3.13 Active Video (AVID) Cropping
AVID cropping provides a means to decrease bandwidth of the video output. This is accomplished by
horizontally blanking a number of AVID pulses and by vertically blanking a number of lines per frame. The
horizontal AVID cropping is controlled using registers 11h and 12h for start pixels MSB and LSB,
respectively.
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Registers 13h and 14h provide access to stop pixels MSB and LSB, respectively. The vertical AVID
cropping is controlled using the vertical blanking (VBLK) start and stop registers at addresses 18h and
19h. Figure 3-7 shows an AVID application.
Standards with embedded syncs insert SAV and EAV codes into the datastream at the beginning and end
of horizontal blanking. These codes contain the V and F bits that also define vertical timing. F and V
change on EAV. Table 3-4 gives the format of the SAV and EAV codes.
H equals 1 always indicates EAV. H equals 0 always indicates SAV. The alignment of V and F to the line
and field counter varies depending on the standard. See ITU-R BT.656 for more information on embedded
syncs.
The P bits are protection bits:
P3 = V xor H
P2 = F xor H
P1 = F xor V
P0 = F xor V xor H
D7 (MSB)D6D5D4D3D2D1D0
Preamble11111111
Preamble00000000
Preamble00000000
Status word1FVHP3P2P1P0
The I2C standard consists of two signals, serial input/output data line (SDA) and input/output clock line
(SCL), which carry information between the devices connected to the bus. A third signal (I2CSEL) is used
for slave address selection. Although the I2C system can be multimastered, the TVP5151 decoder
functions only as a slave device.
Both SDA and SCL must be connected to a positive supply voltage via a pullup resistor. When the bus is
free, both lines are high. The slave address select terminal (I2CSEL) enables the use of two TVP5151
decoders tied to the same I2C bus. At power up, the status of the I2CSEL is polled. Depending on the
write and read addresses to be used for the TVP5151 decoder, it can either be pulled low or high through
a resistor. This terminal is multiplexed with YOUT7 and hence must not be tied directly to ground or
IO_DVDD. Table 3-6 summarizes the terminal functions of the I2C-mode host interface.
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Table 3-5. Write Address
Selection
I2CSELWRITE ADDRESS
0B8h
1BAh
Table 3-6. I2C Terminal Description
SIGNALTYPEDESCRIPTION
I2CSEL (YOUT7)ISlave address selection
SCLI/O (open drain)Input/output clock line
SDAI/O (open drain)Input/output data line
Data transfer rate on the bus is up to 400 kbit/s. The number of interfaces connected to the bus is
dependent on the bus capacitance limit of 400 pF. The data on the SDA line must be stable during the
high period of the SCL except for start and stop conditions. The high or low state of the data line can only
change with the clock signal on the SCL line being low. A high-to-low transition on the SDA line while the
SCL is high indicates an I2C start condition. A low-to-high transition on the SDA line while the SCL is high
indicates an I2C stop condition.
Every byte placed on the SDA must be eight bits long. The number of bytes which can be transferred is
unrestricted. Each byte must be followed by an acknowledge bit. The acknowledge-related clock pulse is
generated by the I2C master.
Data transfers occur utilizing the following illustrated formats.
An I2C master initiates a write operation to the TVP5151 decoder by generating a start condition (S)
followed by the TVP5151 I2C slave address (see the following illustration), in MSB first bit order, followed
by a 0 to indicate a write cycle. After receiving an acknowledge from the TVP5151 decoder, the master
presents the subaddress of the register, or the first of a block of registers it wants to write, followed by one
or more bytes of data, MSB first. The TVP5151 decoder acknowledges each byte after completion of each
transfer. The I2C master terminates the write operation by generating a stop condition (P).
I2C Write data (master)DataDataDataDataDataDataDataData
(1)
Step 7
I2C Acknowledge (slave)A
Step 80
I2C Stop (master)P
(1) Repeat steps 6 and 7 until all data have been written.
3.15.2 I2C Read Operation
The read operation consists of two phases. The first phase is the address phase. In this phase, an I2C
master initiates a write operation to the TVP5151 decoder by generating a start condition (S) followed by
the TVP5151 I2C slave address, in MSB first bit order, followed by a 0 to indicate a write cycle. After
receiving an acknowledge from the TVP5151 decoder, the master presents the subaddress of the register
or the first of a block of registers it wants to read. After the cycle is acknowledged, the master terminates
the cycle immediately by generating a stop condition (P).
The second phase is the data phase. In this phase, an I2C master initiates a read operation to the
TVP5151 decoder by generating a start condition followed by the TVP5151 I2C slave address (see the
following illustration of a read operation), in MSB first bit order, followed by a 1 to indicate a read cycle.
After an acknowledge from the TVP5151 decoder, the I2C master receives one or more bytes of data from
the TVP5151 decoder. The I2C master acknowledges the transfer at the end of each byte. After the last
data byte desired has been transferred from the TVP5151 decoder to the master, the master generates a
not acknowledge followed by a stop.
The TVP5151 decoder requires delays in the I2C accesses to accommodate its internal processor's timing.
In accordance with I2C specifications, the TVP5151 decoder holds the I2C clock line (SCL) low to indicate
the wait period to the I2C master. If the I2C master is not designed to check for the I2C clock line held-low
condition, then the maximum delays must always be inserted where required. These delays are of variable
length; maximum delays are indicated in the following diagram:
Normal register writing addresses 00h to 8Fh (addresses 90h to FFh do not require delays).
The 64-µs delay is for all registers that do not require a reinitialization. Delays may be more for some
registers.
3.16 Clock Circuits
An internal line-locked PLL generates the system and pixel clocks. A 27.000-MHz clock is required to
drive the PLL. This may be input to the TVP5151 decoder on terminal 5 (XTAL1), or a crystal of
27.000-MHz fundamental resonant frequency may be connected across terminals 5 and 6 (XTAL2).
Figure 3-8 shows the reference clock configurations. For the example crystal circuit shown (a
parallel-resonant crystal with 27.000-MHz fundamental frequency), the external capacitors must have the
following relationship:
CL1= CL2= 2CL– C
where C
is the terminal capacitance with respect to ground, and CLis the crystal load capacitance
STRAY
specified by the crystal manufacturer.
STRAY
SLES241B–SEPTEMBER 2009–REVISED JUNE 2010
Figure 3-8 shows the reference clock configurations.
NOTE: The resistor (R) in parallel with the crystal is recommended to support a wide range of crystal types. A 100-kΩ resistor
may be used for most crystal types.
Figure 3-8. Reference Clock Configurations
An alternate method to supply an external source with a 1.8-V to 3.3-V peak-to-peak level is to pull pin 5
(XTAL1/OSC) low and connect a 1.8-V to 3.3-V external oscillator clock source to pin 26, AVID/CLK_IN,
depending on what IO_DVDD supply voltage is used.
Clock source frequency should have an accuracy of ±50 ppm (max).
A Genlock control function is provided to support a standard video encoder to synchronize its internal
color oscillator for properly reproduced color with unstable timebase sources such as VCRs.
The frequency control word of the internal color subcarrier digitally tuned oscillator (DTO) and the
subcarrier phase reset bit are transmitted via terminal 23 (GLCO). The frequency control word is a 23-bit
binary number. The frequency of the DTO can be calculated from the following equation:
f
= (f
dto
where f
/223) × f
ctrl
dto
sclk
is the frequency of the DTO, f
the SCLK.
3.17.1 GLCO Interface
A write of 1 to bit 4 of the chrominance control register at I2C subaddress 1Ah causes the subcarrier DTO
phase reset bit to be sent on the next scan line on GLCO. The active-low reset bit occurs seven SCLKs
after the transmission of the last bit of DTO frequency control. Upon the transmission of the reset bit, the
phase of the TVP5151 internal subcarrier DTO is reset to zero.
A Genlock slave device can be connected to the GLCO terminal and uses the information on GLCO to
synchronize its internal color phase DTO to achieve clean line and color lock.
Figure 3-9 shows the timing diagram of the GLCO mode.
Figure 3-10 shows the timing diagram of the RTC mode. Clock rate for the RTC mode is four times slower
than the GLCO clock rate. For Color PLL frequency control, the upper 22 bits are used. Each frequency
control bit is two clock cycles long. The active-low reset bit occurs six CLKs after the transmission of the
last bit of PLL frequency control.
SLES241B–SEPTEMBER 2009–REVISED JUNE 2010
Figure 3-10. RTC Timing
3.18 Reset and Power Down
The RESETB and PDN terminals work together to put the TVP5151 decoder into one of the two modes.
Table 3-8 shows the configuration.
After power-up, the device is in an unknown state with its outputs undefined, until it receives a RESETB
signal as depicted in Figure 3-11. After RESETB is released, outputs SCLK and YOUT0 to YOUT7 are in
high-impedance state until TVP5151 is initialized and the outputs are activated.
I2C SCL and SDA signals must not change state until the TVP5151 reset sequence has been
completed.
PDNRESETBCONFIGURATION
NOTE
Table 3-8. Reset and Power-Down Modes
00Reserved (unknown state)
01Powers down the decoder
10Resets the decoder
11Normal operation
The TVP5151 decoder is initialized and controlled by a set of internal registers that set all device operating
parameters. Communication between the external controller and the TVP5151 decoder is through I2C.
Table 3-11 shows the summary of these registers. The reserved registers must not be written. Reserved
bits in the defined registers must be written with zeros, unless otherwise noted. The detailed programming
information of each register is described in the following sections.
REGISTERADDRESSDEFAULTR/W
Video input source selection #100h00hR/W
Analog channel controls01h15hR/W
Operation mode controls02h00hR/W
Miscellaneous controls03h00hR/W
Autoswitch mask04hDChR/W
Miscellaneous output controls05h00hR/W
Color killer threshold control06h10hR/W
Luminance processing control #107h60hR/W
Luminance processing control #208h00hR/W
Brightness control09h80hR/W
Color saturation control0Ah80hR/W
Hue control0Bh00hR/W
Reserved0Ch
Outputs and data rates select0Dh47hR/W
Luminance processing control #30Eh00hR/W
Configuration shared pins0Fh00hR/W
Reserved10h
Active video cropping start pixel MSB11h00hR/W
Active video cropping start pixel LSB12h00hR/W
Active video cropping stop pixel MSB13h00hR/W
Active video cropping stop pixel LSB14h00hR/W
Genlock and RTC15h01hR/W
Horizontal sync start16h80hR/W
Reserved17h
Vertical blanking start18h00hR/W
Vertical blanking stop19h00hR/W
Chrominance control #11Ah0ChR/W
Chrominance control #21Bh14hR/W
Interrupt reset register B1Ch00hR/W
Interrupt enable register B1Dh00hR/W
Interrupt configuration register B1Eh00hR/W
Reserved1Fh-20h
I2C indirect registers21h-24h00hR/W
Reserved25h-27h
Video standard28h00hR/W
Reserved29h–2Bh
Cb gain factor2ChR
Cr gain factor2DhR
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Table 3-11. Register Summary
(1)
(1) R = Read only, W = Write only, R/W = Read and write
0 = Color burst reference for AGC disabled (default)
1 = Color burst reference for AGC enabled (not recommended)
TV/VCR mode
00 = Automatic mode determined by the internal detection circuit (default)
01 = Reserved
10 = VCR (nonstandard video) mode
11 = TV (standard video) mode
With automatic detection enabled, unstable or nonstandard syncs on the input video forces the
detector into the VCR mode. This turns off the comb filters and turns on the chrominance trap filter.
Note: GPCL output enable must not be programmed to be 0 when register 0Fh bit 1 is 1 (GPCL/VBLK).
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Lock status (HVLK) (configured along with register 0Fh, see Figure 3-12 for the relationship between the
configuration shared pins)
0 = Terminal VSYNC/PALI outputs the PAL indicator (PALI) signal and terminal FID/GLCO outputs the
field ID (FID) signal (default) (if terminals are configured to output PALI and FID in register 0Fh).
1 = Terminal VSYNC/PALI outputs the horizontal lock indicator (HLK) and terminal FID outputs the
vertical lock indicator (VLK) (if terminals are configured to output PALI and FID in register 0Fh).
These are additional functions that are provided for ease of use.
YCbCr output enable
0 = YOUT[7:0] high impedance (default)
1 = YOUT[7:0] active
Note: YOUT7 must be pulled high or low for device I2C address select.
HSYNC, VSYNC/PALI, active video indicator (AVID), and FID/GLCO output enables
0 = HSYNC, VSYNC/PALI, AVID, and FID/GLCO are high-impedance (default).
1 = HSYNC, VSYNC/PALI, AVID, and FID/GLCO are active.
Note: This control bit has no effect on the FID/GLCO output when it is programmed to output the
GLCO signal (see bit 3 of address 0Fh). When the GLCO signal is selected, the FID/GLCO output is
always active.
Vertical blanking on/off
0 = Vertical blanking (VBLK) off (default)
1 = Vertical blanking (VBLK) on
Clock output enable
0 = SCLK output is high impedance (default)
1 = SCLK output is enabled
Note: To achieve lowest power consumption, outputs placed in the high-impedance state should not be
left floating. A 10-kΩ pulldown resistor is recommended if not driven externally.
Note: When enabling the outputs, ensure the clock output is not accidently disabled.
Table 3-13. Digital Output Control
REGISTER 03h, BIT 3REGISTER C2h, BIT 2
(TVPOE)(VDPOE)
0XHigh impedanceAfter both YCbCr output enable bits are programmed
X0High impedanceAfter both YCbCr output enable bits are programmed
11ActiveAfter both YCbCr output enable bits are programmed
Also see the configuration shared pins register at subaddress 0Fh.
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TVP5151
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SLES241B–SEPTEMBER 2009–REVISED JUNE 2010
3.21.5 Autoswitch Mask Register
Address04h
DefaultDCh
76543210
ReservedSEC_OFFN4.43_OFFPALN_OFFPALM_OFFReserved
N4.43_OFF
0 = NTSC4.43 is unmasked from the autoswitch process. Autoswitch does switch to NTSC4.43.
1 = NTSC4.43 is masked from the autoswitch process. Autoswitch does not switch to NTSC4.43
(default).
PALN_OFF
0 = PAL-N is unmasked from the autoswitch process. Autoswitch does switch to PAL-N.
1 = PAL-N is masked from the autoswitch process. Autoswitch does not switch to PAL-N (default).
PALM_OFF
0 = PAL-M is unmasked from the autoswitch process. Autoswitch does switch to PAL-M.
1 = PAL-M is masked from the autoswitch process. Autoswitch does not switch to PAL-M (default).
SEC_OFF
0 = SECAM is unmasked from the autoswitch process. Autoswitch does switch to SECAM (default).
1 = SECAM is masked from the autoswitch process. Autoswitch does not switch to SECAM.
3.21.6 Miscellaneous Output Controls Register
Address05h
Default00h
76543210
ReservedAVID/CLK_INReserved
function select
AVID/CLK_IN function select
0 = CLK_IN (default)
1 = AVID
3.21.7 Color Killer Threshold Control Register
Address06h
Default10h
76543210
ReservedAutomatic color killerColor killer threshold
Automatic color killer
00 = Automatic mode (default)
01 = Reserved
10 = Color killer enabled, CbCr terminals forced to a zero color state
11 = Color killer disabled
Color killer threshold
11111 = –30 dB (minimum)
10000 = –24 dB (default)
00000 = –18 dB (maximum)
2× luminancePedestal notDisable rawLuminance bypassLuminance signal delay with respect to chrominance signal
output enablepresentheaderenabled during
2× luminance output enable
0 = Output depends on bit 4, luminance bypass enabled during vertical blanking (default).
1 = Outputs 2x luminance samples during the entire frame. This bit takes precedence over bit 4.
Pedestal not present
0 = 7.5 IRE pedestal is present on the analog video input signal.
1 = Pedestal is not present on the analog video input signal (default).
Disable raw header
0 = Insert 656 ancillary headers for raw data
1 = Disable 656 ancillary headers and instead force dummy ones (40h) (default)
Luminance bypass enabled during vertical blanking
0 = Disabled. If bit 7, 2× luminance output enable, is 0, normal luminance processing occurs and
YCbCr samples are output during the entire frame (default).
1 = Enabled. If bit 7, 2× luminance output enable, is 0, normal luminance processing occurs and
YCbCr samples are output during VACTIVE and 2× luminance samples are output during VBLK.
Luminance bypass occurs for the duration of the vertical blanking as defined by registers 18h and 19h.
vertical blanking
Luminance bypass occurs for the duration of the vertical blanking as defined by registers 18h and 19h.
Luminance signal delay with respect to chrominance signal in pixel clock increments (range –8 to +7 pixel
ReservedYCbCr outputCbCr codeYCbCr data path bypassYCbCr output format
YCbCr output code range
CbCr code format
YCbCr data path bypass
code rangeformat
0 = ITU-R BT.601 coding range (Y ranges from 16 to 235. U and V range from 16 to 240)
1 = Extended coding range (Y, U, and V range from 1 to 254) (default)
00 = Normal operation (default)
01 = Decimation filter output connects directly to the YCbCr output pins. This data is similar to the
digitized composite data, but the HBLANK area is replaced with ITU-R BT.656 digital blanking.
10 = Digitized composite (or digitized S-video luminance). A/D output connects directly to YCbCr
Luminance filter select [1:0] selects one of the four chrominance trap (notch) filters to produce luminance
signal by removing the chrominance signal from the composite video signal. The stopband of the
chrominance trap filter is centered at the chrominance subcarrier frequency with stopband bandwidth
controlled by the two control bits. See the following table for the stopband bandwidths. The WCF bit is
controlled in the chrominance control #2 register, see Section 3.21.25.
See Figure 3-12 for the relationship between the configuration shared pins.
3.21.16 Active Video Cropping Start Pixel MSB Register
Address11h
Default00h
76543210
AVID start pixel MSB [9:2]
Active video cropping start pixel MSB [9:2], set this register first before setting register 12h. The TVP5151
decoder updates the AVID start values only when register 12h is written to. This start pixel value is relative
to the default values of the AVID start pixel.
3.21.17 Active Video Cropping Start Pixel LSB Register
Address12h
Default00h
76543210
ReservedAVID activeAVID start pixel LSB [1:0]
AVID active
0 = AVID out active in VBLK (default)
1 = AVID out inactive in VBLK
Active video cropping start pixel LSB [1:0]: The TVP5151 decoder updates the AVID start values only
3.21.18 Active Video Cropping Stop Pixel MSB Register
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Address13h
Default00h
76543210
AVID stop pixel MSB [9:2]
Active video cropping stop pixel MSB [9:2], set this register first before setting the register 14h. The
TVP5151 decoder updates the AVID stop values only when register 14h is written to. This stop pixel value
is relative to the default values of the AVID stop pixel.
3.21.19 Active Video Cropping Stop Pixel LSB Register
Address14h
Default00h
76543210
ReservedAVID stop pixel LSB
Active video cropping stop pixel LSB [1:0]: The number of pixels of active video must be an even number.
The TVP5151 decoder updates the AVID stop values only when this register is written to.
00Nonstandard evenForce to 1Switch at field boundary
Nonstandard oddTogglesSwitch at field boundary
01
10
11Illegal
GLCO/RTC. The following table shows the different modes.
StandardITU-R BT.656ITU-R BT.656
NonstandardTogglesSwitch at field boundary
StandardITU-R BT.656ITU-R BT.656
NonstandardPulse modeSwitch at field boundary
BIT 2BIT 1BIT 0GENLOCK/RTC MODE
0X0GLCO
0X1
1X0GLCO
1X1RTC output mode 1
RTC output mode 0
(default)
All other values are reserved.
Figure 3-9 shows the timing of GLCO, and Figure 3-10 shows the timing of RTC.
Detailed timing information is also available in Section 3.12.
3.21.22 Vertical Blanking Start Register
Address18h
Default00h
76543210
Vertical blanking (VBLK) start
0111 1111 = 127 lines after start of vertical blanking interval
0000 0001 = 1 line after start of vertical blanking interval
0000 0000 = Same time as start of vertical blanking interval (default) (see Figure 3-5)
1111 1111 = 1 line before start of vertical blanking interval
1000 0000 = 128 lines before start of vertical blanking interval
Vertical blanking is adjustable with respect to the standard vertical blanking intervals. The setting in this
register determines the timing of the GPCL/VBLK signal when it is configured to output vertical blank (see
register 03h). The setting in this register also determines the duration of the luminance bypass function
(see register 07h).
0111 1111 = 127 lines after stop of vertical blanking interval
0000 0001 = 1 line after stop of vertical blanking interval
0000 0000 = Same time as stop of vertical blanking interval (default) (see Figure 3-5)
1111 1111 = 1 line before stop of vertical blanking interval
1000 0000 = 128 lines before stop of vertical blanking interval
Vertical blanking is adjustable with respect to the standard vertical blanking intervals. The setting in this
register determines the timing of the GPCL/VBLK signal when it is configured to output vertical blank (see
register 03h). The setting in this register also determines the duration of the luminance bypass function
(see register 07h).
3.21.24 Chrominance Control #1 Register
Address1Ah
Default0Ch
76543210
ReservedColor PLL resetChrominanceChrominanceAutomatic color gain control
adaptive combcomb filter
filter enableenable (CE)
(ACE)
Color PLL reset
0 = Color PLL not reset (default)
1 = Color PLL reset
When a 1 is written to this bit, the color PLL phase is reset to zero and the subcarrier PLL phase reset
bit is transmitted on terminal 23 (GLCO) on the next line (NTSC or PAL).
Chrominance adaptive comb filter enable (ACE)
0 = Disable
1 = Enable (default)
Chrominance comb filter enable (CE)
0 = Disable
1 = Enable (default)
Automatic color gain control (ACGC)
00 = ACGC enabled (default)
01 = Reserved
10 = ACGC disabled
11 = ACGC frozen to the previously set value
Interrupt reset register B is used by the external processor to reset the interrupt status bits in interrupt
status register B. Bits loaded with a 1 allow the corresponding interrupt status bit to reset to 0. Bits loaded
with a 0 have no effect on the interrupt status bits.
Software initialization reset
0 = No effect (default)
1 = Reset software initialization bit
Macrovision detect changed reset
0 = No effect (default)
1 = Reset Macrovision detect changed bit
Field rate changed reset
0 = No effect (default)
1 = Reset field rate changed bit
Line alternation changed reset
0 = No effect (default)
1 = Reset line alternation changed bit
Color lock changed reset
0 = No effect (default)
1 = Reset color lock changed bit
H/V lock changed reset
0 = No effect (default)
1 = Reset H/V lock changed bit
TV/VCR changed reset [TV/VCR mode is determined by counting the total number of lines/frame. The
mode switches to VCR for nonstandard number of lines]
0 = No effect (default)
1 = Reset TV/VCR changed bit
Interrupt enable register B is used by the external processor to mask unnecessary interrupt sources for
interrupt B. Bits loaded with a 1 allow the corresponding interrupt condition to generate an interrupt on the
external pin. Conversely, bits loaded with zeros mask the corresponding interrupt condition from
generating an interrupt on the external pin. This register only affects the external pin, it does not affect the
bits in the interrupt status register. A given condition can set the appropriate bit in the status register and
not cause an interrupt on the external pin. To determine if this device is driving the interrupt pin either
AND interrupt status register B with interrupt enable register B or check the state of interrupt B in the
interrupt B active register.
0 = Interrupt B is active low (default).
1 = Interrupt B is active high.
Interrupt polarity B must be the same as interrupt polarity A of Interrupt Configuration Register A at
Address C2h.
Interrupt Configuration Register B is used to configure the polarity of interrupt B on the external interrupt
pin. When the interrupt B is configured for active low, the pin is driven low when active and high
impedance when inactive (open-drain). Conversely, when the interrupt B is configured for active high, it is
driven high for active and driven low for inactive.
Note: An external pullup resistor (4.7kΩ to 10kΩ) is required when the polarity of the external interrupt
terminal (pin 27) is configured as active low.
With the autoswitch code running, the application can force the device to operate in a particular video
standard mode by writing the appropriate value into this register.
This is a read-only register that provides the gain applied to the Cb in the YCbCr data stream.
3.21.31 Cr Gain Factor Register
Address2Dh
76543210
Cr gain factor
This is a read-only register that provides the gain applied to the Cr in the YCbCr data stream.
3.21.32 Macrovision On Counter Register
Address2Eh
Default0Fh
76543210
Macrovision on counter
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This register allows the user to determine how many consecutive frames in which the Macrovision AGC
pulses are detected before the decoder decides that the Macrovision AGC pulses are present.
3.21.33 Macrovision Off Counter Register
Address2Fh
Default01h
76543210
Macrovision off counter
This register allows the user to determine how many consecutive frames in which the Macrovision AGC
pulses are not detected before the decoder decides that the Macrovision AGC pulses are not present.
3.21.34 656 Revision Select Register
Address30h
Default00h
76543210
Reserved656 revision
656 revision select
0 = Adheres to ITU-R BT.656.4 and BT.656.5 timing (default)
1 = Adheres to ITU-R BT.656.3 timing
0 = Software initialization is not ready.
1 = Software initialization is ready.
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Macrovision detect changed
0 = Macrovision detect status has not changed.
1 = Macrovision detect status has changed.
Field rate changed
0 = Field rate has not changed.
1 = Field rate has changed.
Line alternation changed
0 = Line alteration has not changed.
1 = Line alternation has changed.
Color lock changed
0 = Color lock status has not changed.
1 = Color lock status has changed.
H/V lock changed
0 = H/V lock status has not changed.
1 = H/V lock status has changed.
TV/VCR changed
0 = TV/VCR status has not changed.
1 = TV/VCR status has changed.
Interrupt status register B is polled by the external processor to determine the interrupt source for interrupt
B. After an interrupt condition is set, it can be reset by writing to the interrupt reset register B at
subaddress 1Ch with a 1 in the appropriate bit.
0 = Interrupt B is not active on the external terminal (default).
1 = Interrupt B is active on the external terminal.
The interrupt active register B is polled by the external processor to determine if interrupt B is active.
3.21.43 Status Register #1
Address88h
76543210
Peak whiteLine-alternatingField rateLost lock detectColorVertical syncHorizontal sync TV/VCR status
detect statusstatusstatussubcarrier locklock statuslock status
Peak white detect status
0 = Peak white is not detected.
1 = Peak white is detected.
status
Line-alternating status
0 = Nonline alternating
1 = Line alternating
Field rate status
0 = 60 Hz
1 = 50 Hz
Lost lock detect
0 = No lost lock since status register #1 was last read.
1 = Lost lock since status register #1 was last read.
Color subcarrier lock status
0 = Color subcarrier is not locked.
1 = Color subcarrier is locked.
Vertical sync lock status
0 = Vertical sync is not locked.
1 = Vertical sync is locked.
Horizontal sync lock status
0 = Horizontal sync is not locked.
1 = Horizontal sync is locked.
TV/VCR status. TV mode is determined by detecting standard line-to-line variations and specific
chrominance SCH phases based on the standard input video format. VCR mode is determined by
detecting variations in the chrominance SCH phases compared to the chrominance SCH phases of the
standard input video format.
ReservedWeak signalPAL switchField sequence AGC and offsetMacrovision detection
detectionpolaritystatusfrozen status
Weak signal detection
0 = No weak signal
1 = Weak signal mode
PAL switch polarity of first line of odd field
0 = PAL switch is 0.
1 = PAL switch is 1.
Field sequence status
0 = Even field
1 = Odd field
AGC and offset frozen status
0 = AGC and offset are not frozen.
1 = AGC and offset are frozen.
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Macrovision detection
000 = No copy protection
001 = AGC process present (Macrovision Type 1 present)
010 = Colorstripe process Type 2 present
011 = AGC process and colorstripe process Type 2 present
100 = Reserved
101 = Reserved
110 = Colorstripe process Type 3 present
111 = AGC process and color stripe process Type 3 present
Analog gain: 4-bit front-end AGC analog gain setting
Digital gain: 4 MSBs of 6-bit front-end AGC digital gain setting
The product of the analog and digital gain is as follows:
This register contains information about the detected video standard at which the device is currently
operating. When autoswitch code is running, this register must be tested to determine which video
standard has been detected.
90hClosed caption field 1 byte 1
91hClosed caption field 1 byte 2
92hClosed caption field 2 byte 1
93hClosed caption field 2 byte 2
These registers contain the closed caption data arranged in bytes per field.
3.21.49 WSS/CGMS-A Data Registers
Address94h–99h
NTSC
Address76543210BYTE
94hb5b4b3b2b1b0WSS field 1 byte 1
95hb13b12b11b10b9b8b7b6WSS field 1 byte 2
96hb19b18b17b16b15b14WSS field 1 byte 3
97hb5b4b3b2b1b0WSS field 2 byte 1
98hb13b12b11b10b9b8b7b6WSS field 2 byte 2
99hb19b18b17b16b15b14WSS field 2 byte 3
These registers contain the wide screen signaling (WSS/CGMS-A) data for NTSC.
For NTSC, the bits are:
Bits 0–1 represent word 0, aspect ratio.
Bits 2–5 represent word 1, header code for word 2.
Bits 6–13 represent word 2, copy control.
Bits 14–19 represent word 3, CRC.
PAL/SECAM
Address76543210BYTE
94hb7b6b5b4b3b2b1b0WSS field 1 byte 1
95hb13b12b11b10b9b8WSS field 1 byte 2
96hReserved
97hb7b6b5b4b3b2b1b0WSS field 2 byte 1
98hb13b12b11b10b9b8WSS field 2 byte 2
99hReserved
For PAL/SECAM, the bits are:
Bits 0–3 represent group 1, aspect ratio.
Bits 4–7 represent group 2, enhanced services.
Bits 8–10 represent group 3, subtitles.
Bits 11–13 represent group 4, others.
This address is provided to access VBI data in the FIFO through the host port. All forms of teletext data
come directly from the FIFO, while all other forms of VBI data can be programmed to come from the
registers or from the FIFO. Current status of the FIFO can be found at address C6h and the number of
bytes in the FIFO is located at address C7h. If the host port is to be used to read data from the FIFO, then
the host access enable bit at address CDh must be set to 1. The format used for the VBI FIFO is shown in
For an NABTS system, the packet prefix consists of five bytes. Each byte contains four data bits (D[3:0])
interlaced with four Hamming protection bits (H[3:0]):
76543210
D[3]H[3]D[2]H[2]D[1]H[1]D[0]H[0]
Only the data portion D[3:0] from each byte is applied to a teletext filter function with the corresponding
pattern bits P[3:0] and mask bits M[3:0]. Hamming protection bits are ignored by the filter.
For a WST system (PAL or NTSC), the packet prefix consists of two bytes so that two patterns are used.
Patterns 3, 4, and 5 are ignored.
The mask bits enable filtering using the corresponding bit in the pattern register. For example, a 1 in the
LSB of mask 1 means that the filter module must compare the LSB of nibble 1 in the pattern register to
the first data bit on the transaction. If these match, a true result is returned. A 0 in a bit of mask 1 means
that the filter module must ignore that data bit of the transaction. If all zeros are programmed in the mask
bits, the filter matches all patterns returning a true result (default 00h).
Pattern and mask for each byte and filter are referred as <1,2><P,M><1,2,3,4,5>, where:
<1,2> identifies the filter 1 or 2
<P,M> identifies the pattern or mask
<1,2,3,4,5> identifies the byte number
The interrupt status register A can be polled by the host processor to determine the source of an interrupt.
After an interrupt condition is set it can be reset by writing to this register with a 1 in the appropriate bit(s).
Lock state interrupt
0 = TVP5151 is not locked to the video signal (default).
1 = TVP5151 is locked to the video signal.
Lock interrupt
0 = A transition has not occurred on the lock signal (default).
1 = A transition has occurred on the lock signal.
FIFO threshold interrupt
0 = The amount of data in the FIFO has not yet crossed the threshold programmed at address C8h
(default).
1 = The amount of data in the FIFO has crossed the threshold programmed at address C8h.
Line interrupt
0 = The video line number has not yet been reached (default).
1 = The video line number programmed in address CAh has occurred.
Data interrupt
0 = No data is available (default).
1 = VBI data is available either in the FIFO or in the VBI data registers.
The interrupt enable register A is used by the host processor to mask unnecessary interrupt sources. Bits
loaded with a 1 allow the corresponding interrupt condition to generate an interrupt on the external pin.
Conversely, bits loaded with a 0 mask the corresponding interrupt condition from generating an interrupt
on the external pin. This register only affects the interrupt on the external terminal, it does not affect the
bits in interrupt status register A. A given condition can set the appropriate bit in the status register and not
cause an interrupt on the external terminal. To determine if this device is driving the interrupt terminal,
either perform a logical AND of interrupt status register A with interrupt enable register A, or check the
state of the interrupt A bit in the interrupt configuration register at address C2h.
0 = YCbCr pins are high impedance.
1 = YCbCr pins are active if other conditions are met (default) (see Table 3-13).
Interrupt A (read only)
0 = Interrupt A is not active on the external pin (default).
1 = Interrupt A is active on the external pin.
Interrupt polarity A must be the same as interrupt polarity B of Interrupt Configuration Register B at
Address 1Eh.
Interrupt polarity A
0 = Interrupt A is active low (default).
1 = Interrupt A is active high.
Interrupt configuration register A is used to configure the polarity of the external interrupt terminal. When
interrupt A is configured as active low, the terminal is driven low when active and high impedance when
inactive (open drain). Conversely, when the terminal is configured as active high, it is driven high when
active and driven low when inactive.
(VDPOE)polarity A
Note: An external pullup resistor (4.7kΩ to 10kΩ) is required when the polarity of the external interrupt
terminal (pin 27) is configured as active low.
3.21.58 VDP Configuration RAM Register
AddressC3hC4hC5h
DefaultDCh0Fh00h
Address76543210
C3hConfiguration data
C4hRAM address (7:0)
C5hReservedRAM
The configuration RAM data is provided to initialize the VDP with initial constants. The configuration RAM
is 512 bytes organized as 32 different configurations of 16 bytes each. The first 12 configurations are
defined for the current VBI standards. An additional two configurations can be used as a custom
programmed mode for unique standards such as Gemstar.
Address C3h is used to read or write to the RAM. The RAM internal address counter is automatically
incremented with each transaction. Addresses C5h and C4h make up a 9-bit address to load the internal
address counter with a specific start address. This can be used to write a subset of the RAM for only
those standards of interest.
NOTE
Registers D0h–FBh must all be programmed with FFh before writing or reading the
configuration RAM. Full field mode (CFh) must be disabled as well.
FIFO full errorFIFO emptyTTX availableCC field 1CC field 2WSS availableVPS availableVITC available
The VDP status register indicates whether data is available in either the FIFO or data registers, and status
information about the FIFO. Reading data from the corresponding register does not clear the status flags
automatically. These flags are only reset by writing a 1 to the respective bit. However, bit 6 is updated
automatically.
FIFO full error
0 = No FIFO full error
1 = FIFO was full during a write to FIFO.
The FIFO full error flag is set when the current line of VBI data can not enter the FIFO. For example, if
the FIFO has only ten bytes left and teletext is the current VBI line, the FIFO full error flag is set, but no
data is written because the entire teletext line does not fit. However, if the next VBI line is closed
caption requiring only two bytes of data plus the header, this goes into the FIFO, even if the full error
flag is set.
FIFO empty
0 = FIFO is not empty.
1 = FIFO is empty.
availableavailable
TTX available
0 = Teletext data is not available.
1 = Teletext data is available.
CC field 1 available
0 = Closed caption data from field 1 is not available.
1 = Closed caption data from field 1 is available.
CC field 2 available
0 = Closed caption data from field 2 is not available.
1 = Closed caption data from field 2 is available.
WSS available
0 = WSS data is not available.
1 = WSS data is available.
VPS available
0 = VPS data is not available.
1 = VPS data is available.
VITC available
0 = VITC data is not available.
1 = VITC data is available.
This register provides the number of words in the FIFO. One word equals two bytes.
3.21.61 FIFO Interrupt Threshold Register
AddressC8h
Default80h
76543210
Number of words
This register is programmed to trigger an interrupt when the number of words in the FIFO exceeds this
value (default 80h). This interrupt must be enabled at address C1h. One word equals two bytes.
3.21.62 FIFO Reset Register
AddressC9h
Default00h
76543210
Any data
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Writing any data to this register resets the FIFO and clears any data present in all VBI read registers.
3.21.63 Line Number Interrupt Register
AddressCAh
Default00h
76543210
Field 1 enableField 2 enableLine number
This register is programmed to trigger an interrupt when the video line number matches this value in bits
5:0. This interrupt must be enabled at address C1h. The value of 0 or 1 does not generate an interrupt.
These registers form a 10-bit horizontal pixel position from the falling edge of sync, where the VDP
controller initiates the program from one line standard to the next line standard; for example, the previous
line of teletext to the next line of closed caption. This value must be set so that the switch occurs after the
previous transaction has cleared the delay in the VDP, but early enough to allow the new values to be
programmed before the current settings are required.
3.21.65 FIFO Output Control Register
AddressCDh
Default01h
76543210
ReservedHost access
This register is programmed to allow I2C access to the FIFO or to allow all VDP data to go out the video
port as ancillary data.
enable
Host access enable
0 = Output FIFO data to the video output Y[7:0] as ancillary data
1 = Read FIFO data via I2C register B0h (default)
3.21.66 Full Field Enable Register
AddressCFh
Default00h
76543210
ReservedFull field enable
This register enables the full field mode. In this mode, all lines outside the vertical blank area and all lines
in the line mode registers programmed with FFh are sliced with the definition of register FCh. Values other
than FFh in the line mode registers allow a different slice mode for that particular line.
Full field enable
0 = Disable full field mode (default)
1 = Enable full field mode
D0Line 6 Field 1
D1Line 6 Field 2
D2Line 7 Field 1
D3Line 7 Field 2
D4Line 8 Field 1
D5Line 8 Field 2
D6Line 9 Field 1
D7Line 9 Field 2
D8Line 10 Field 1
D9Line 10 Field 2
DALine 11 Field 1
DBLine 11 Field 2
DCLine 12 Field 1
DDLine 12 Field 2
DELine 13 Field 1
DFLine 13 Field 2
E0Line 14 Field 1
E1Line 14 Field 2
E2Line 15 Field 1
E3Line 15 Field 2
E4Line 16 Field 1
E5Line 16 Field 2
E6Line 17 Field 1
E7Line 17 Field 2
E8Line 18 Field 1
E9Line 18 Field 2
EALine 19 Field 1
EBLine 19 Field 2
ECLine 20 Field 1
EDLine 20 Field 2
EELine 21 Field 1
EFLine 21 Field 2
F0Line 22 Field 1
F1Line 22 Field 2
F2Line 23 Field 1
F3Line 23 Field 2
F4Line 24 Field 1
F5Line 24 Field 2
F6Line 25 Field 1
F7Line 25 Field 2
F8Line 26 Field 1
F9Line 26 Field 2
FALine 27 Field 1
FBLine 27 Field 2
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These registers program the specific VBI standard at a specific line in the video field.
0 = Disable filtering of null bytes in closed caption modes
1 = Enable filtering of null bytes in closed caption modes (default)
In teletext modes, bit 7 enables the data filter function for that particular line. If it is set to 0, the data
filter passes all data on that line.
0 = Send VBI data to registers only
1 = Send VBI data to FIFO and the registers. Teletext data only goes to FIFO (default).
0 = Allow VBI data with errors in the FIFO
1 = Do not allow VBI data with errors in the FIFO (default)
0 = Do not enable error detection and correction
1 = Enable error detection and correction (default)
0000 = WST SECAM
0001 = WST PAL B
0010 = WST PAL C
0011 = WST NTSC
0100 = NABTS NTSC
0101 = TTX NTSC-J
0110 = CC PAL
0111 = CC NTSC
1000 = WSS/CGMS-A PAL
1001 = WSS/CGMS-A NTSC
1010 = VITC PAL
1011 = VITC NTSC
1100 = VPS PAL
1101 = Gemstar 2x Custom 1
1110 = Custom 2
1111 = Active video (VDP off) (default)
A value of FFh in the line mode registers is required for any line to be sliced as part of the full field mode.
3.21.68 Full Field Mode Register
AddressFCh
Default7Fh
76543210
Full field mode
This register programs the specific VBI standard for full field mode. It can be any VBI standard. Individual
line settings take priority over the full field register. This allows each VBI line to be programmed
independently but have the remaining lines in full field mode. The full field mode register has the same
definitions as the line mode registers (default 7Fh).
over operating free-air temperature range (unless otherwise noted)
Supply voltage range
Digital input voltage range, VIto DGND–0.5 V to 4.5 V
Input voltage range, XTAL1 to PLL_GND–0.5 V to 2.3 V
Analog input voltage range AIto CH_AGND–0.2 V to 2.0 V
Digital output voltage range, VOto DGND–0.5 V to 4.5 V
Operating free-air temperature, T
Storage temperature range, T
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not recommended. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
PLL_AVDDAnalog PLL supply voltage1.651.81.95V
CH_AVDDAnalog core supply voltage1.651.81.95V
V
I(P-P)
V
IH
V
IL
V
IH_XTAL
V
IL_XTAL
I
OH
I
OL
I
OH_SCLK
I
OL_SCLK
T
A
(1) Specified by design
Analog input voltage (ac-coupling necessary)00.75V
Digital input voltage high
Digital input voltage low
XTAL input voltage high
XTAL input voltage low
High-level output current
Low-level output current
SCLK high-level output current
SCLK low-level output current
Operating free-air temperature°C
(1)
IO_DVDD to DGND–0.5 V to 4.5 V
DVDD to DGND–0.5 V to 2.3 V
PLL_AVDD to PLL_AGND–0.5 V to 2.3 V
CH_AVDD to CH_AGND–0.5 V to 2.3 V
Typical supply voltages: DVDD = 1.8 V, PLL_AVDD = 1.8 V, CH_AVDD = 1.8 V, IO_DVDD = 3.3 V,
For minimum/maximum values: TA= 0°C to 70°C for commercial or TA= –40°C to 85°C for industrial,
For typical values: TA= 25°C (unless otherwise noted)
4.5DC Electrical Characteristics
PARAMETERTEST CONDITIONS
I
DD(IO_D)
I
DD(D)
I
DD(PLL_A)
I
DD(CH_A)
P
TOT
P
DOWN
C
i
V
OH
V
OL
V
OH_SCLK
V
OL_SCLK
I
IH
I
IL
3.3-V I/O digital supply current100% color bar input6.97.9mA
1.8-V digital supply current100% color bar input3033.5mA
1.8-V analog PLL supply current100% color bar input5.77.9mA
1.8-V analog core supply current100% color bar input27.939.2mA
Total power dissipation, normal mode100% color bar input137185mW
Total power dissipation, power-down mode
Input capacitance
Output voltage high
Output voltage low
SCLK output voltage high
SCLK output voltage low
High-level input current
Low-level input current
(3)
(3)
(3)
(3)
(3)
(4)
(4)
(2)
100% color bar input1mW
By design8pF
IOH= 2 mA0.8 IO_DVDDV
IOL= –2 mA0.22 IO_DVDDV
IOH= 4 mA0.8 IO_DVDDV
IOL= –4 mA0.22 IO_DVDDV
VI= V
IH
VI= V
IL
(1) Measured with 22-Ω series termination resistors and 10-pF load.
(2) Assured by device characterization
(3) Specified by design
(4) YOUT7 is a bidirectional terminal with an internal pulldown resistor. This terminal may sink more than the specified current when in
RESET mode.
(1)
MINTYPMAX UNIT
±20µA
±20µA
4.6Analog Electrical Characteristics
PARAMETERTEST CONDITIONSMINTYPMAX UNIT
Z
Input impedance, analog video inputs
i
C
Input capacitance, analog video inputs
i
V
Input voltage range
i(pp)
(2)
ΔGGain control maximum12dB
ΔGGain control minimum0dB
DNLAbsolute differential nonlinearityA/D only0.51LSB
INLAbsolute integral nonlinearityA/D only12.5LSB
FrFrequency response6 MHz, Specified by design–0.9dB
SNRSignal-to-noise ratio6 MHz, 1.0 V
NSNoise spectrum50% flat field50dB
DPDifferential phaseModulated ramp0.5°
DGDifferential gainModulated ramp1.5%
(1) Specified by design
(2) The 0.75-V maximum applies to the sync-chrominance amplitude, not sync-white. The recommended termination resistors are 37.4 Ω,
t1Bus free time between STOP and START1.3µs
t2Data Hold time00.9µs
t3Data Setup time100ns
t4Setup time for a (repeated) START condition0.6µs
t5Setup time for a STOP condition0.6ns
t6Hold time (repeated) START condition0.6µs
t7Rise time SDA and SCL signal250ns
t8Fall time SDA and SCL signal250ns
CbCapacitive load for each bus line400pF
f
I2C clock frequency400kHz
I2C
(1) Specified by design
(1)
SLES241B–SEPTEMBER 2009–REVISED JUNE 2010
Figure 4-2. I2C Host Interface Timing
4.9Power Dissipation Ratings
BOARDPACKAGER
Low-KTQFP-32 (PBS)39.3ºC/W125.3ºC/W0.638 W0.160 W
High-KTQFP-32 (PBS)39.3ºC/W91.1ºC/W0.878 W0.220 W
(1) Specified with 105°C maximum junction temperature (TJ).
The following example register settings are provided only as a reference. These settings, given the
assumed input connector, video format, and output format, set up the TVP5151 decoder and provide
video output. Example register settings for other features and the VBI data processor are not provided
here.
5.1Example 1
5.1.1Assumptions
Device: TVP5151
Input connector: Composite (AIP1A)
Video format: NTSC-M, PAL (B, G, H, I), or SECAM
NTSC-4.43, PAL-N, and PAL-M are masked from the autoswitch process by default. See the
autoswitch mask register at address 04h.
Output format: 8-bit ITU-R BT.656 with embedded syncs
5.1.2Recommended Settings
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NOTE
Recommended I2C writes: For this setup, only one write is required. All other registers are set up by
default.
I2C register address 03h = Miscellaneous controls register address
I2C data 09h = Enables YCbCr output and the clock output
NOTE
HSYNC, VSYNC/PALI, AVID, and FID/GLCO are high impedance by default. See the
miscellaneous control register at address 03h.
Device: TVP5151
Input connector: S-video (AIP1A (luminance), AIP1B (chrominance))
Video Format: NTSC (M, 4.43), PAL (B, G, H, I, M, N, Nc) or SECAM (B, D, G, K1, L)
Output format: 8-bit 4:2:2 YCbCr with discrete sync outputs
5.2.2Recommended Settings
Recommended I2C writes: This setup requires additional writes to output the discrete sync 4:2:2 data
outputs, the HSYNC, and the VSYNC, and to autoswitch between all video formats mentioned above.
I2C register address 00h = Video input source selection #1 register
I2C data 01h = Selects the S-Video input, AIP1A (luminance), and AIP1B (chrominance)
<br/>
I2C register address 03h = Miscellaneous controls register address
I2C data 0Dh = Enables the YCbCr output data, HSYNC, VSYNC/PALI, AVID, and FID/GLCO
<br/>
SLES241B–SEPTEMBER 2009–REVISED JUNE 2010
I2C register address 04h = Autoswitch mask register
I2C data C0h = Unmask NTSC-4.43, PAL-N, and PAL-M from the autoswitch process
<br/>
I2C register address 0Dh = Outputs and data rates select register
I2C data 40h = Enables 8-bit 4:2:2 YCbCr with discrete sync output
Implies I C address is BAh. If B8h is to be used,
connect pulldown resistor to digital ground.
2
0.1 µF
C11
37.4 Ω
37.4 Ω
37.4 Ω
37.4 Ω
R
AFF
AFF
TVP5151
SLES241B–SEPTEMBER 2009–REVISED JUNE 2010
6Application Information
6.1Application Example
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A.The use of INTREQ/GPCL, AVID, HSYNC, and VSYNC is optional.
B.When OSC is connected through S1, remove the capacitors for the crystal.
C. PDN needs to be high, if device has to be always operational.
D. RESETB is operational only when PDN is high. This allows an active-low reset to the device.
E.100-kΩ resistor (R) in parallel with the crystal is recommended for most crystal types.
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com23-Mar-2010
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
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