TEXAS INSTRUMENTS TVP3010 Technical data

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TVP3010

Data Manual

Video Interface Palette

SLAS082

September 1994

IMPORTANT NOTICE

Texas Instruments Incorporated (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current.

TI warrants performance of its semiconductor products and related software to current specifications in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

Please be aware that TI products are not intended for use in life-support appliances, devices, or systems. Use of TI product in such applications requires the written approval of the appropriate TI officer. Certain applications using semiconductor devices may involve potential risks of personal injury, property damage, or loss of life. In order to minimize these risks, adequate design and operating safeguards should be provided by the customer to minimize inherent or procedural hazards. Inclusion of TI products in such applications is understood to be fully at the risk of the customer using TI devices or systems.

TI assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or services described herein. Nor does TI warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used.

SLAS082, December 1993

 1993, Texas Instruments Incorporated

Printed in the U.S.A.

Contents

Section Title Page

1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Features 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Functional Block Diagram 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Terminal Assignments 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Ordering Information 1–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Terminal Functions 1–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Detailed Description 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 MPU Interface 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Color Palette 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1 Writing to Color-Palette RAM 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.2 Reading From Color-Palette RAM 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.3 Palette-Page Register 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.4 Read Masking 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Clock Selection and Output-Clock (SCLK, RCLK, and VCLK) Generation 2–5. . . .

2.3.1 RCLK, SCLK, VCLK 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.2 Frame-Buffer Clocking: Self- or Externally Clocked 2–7. . . . . . . . . . . . . . . . . .

2.4 Multiplexing Scheme 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.1 Little-Endian and Big-Endian Data Format 2–11. . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.2 VGA Pass-Through Mode 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.3 Pseudo-Color Mode 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.4 Direct-Color Mode 2–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.5 True-Color Mode 2–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.6 Multiplex-Control Registers 2–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 On-Chip Cursor 2–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.1 Cursor RAM 2–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.2 Two-Color 64 × 64 Cursor 2–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.3 64 × 64 Cursor Positioning 2–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.4 Crosshair Cursor 2–25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.5 Dual-Cursor Positioning 2–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 Auxiliary Window, Port Select, and Color-Key Switching 2–27. . . . . . . . . . . . . . . . . . . .

2.6.1 Windowing Control 2–28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.2 Color-Key-Switching Control 2–29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 Overscan 2–30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8 Horizontal Zooming 2–31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9 Test Functions 2–32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9.1 16-Bit CRC 2–32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9.2 Sense Comparator Output and Test Register 2–32. . . . . . . . . . . . . . . . . . . . . . .

2.9.3 Identification Code 2–33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iii

Contents (Continued)

Section Title Page

2.10 MUXOUT [SENSE] Output 2–33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1 Reset 2–33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.1 Power-On Reset 2–33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.2 Software Reset 2–33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.12 Frame-Buffer Interface 2–33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.13 Analog Output Specifications 2–34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.14 Video Control: Horizontal Sync, Vertical Sync, and Blank 2–36. . . . . . . . . . . . . . . . . .

2.15 Split Shift-Register-T ransfer VRAMs 2–36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16 Control-Register Definitions 2–37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.1 Configuration Register 2–37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.2 General-Control Register 2–38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.3 Cursor-Control Register 2–39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.4 Cursor-Position X and Y Registers 2–40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.5 Sprite-Origin X and Y Registers 2–41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.6 Window-Start X and Y Registers 2–42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.7 Window-Stop X and Y Registers 2–43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.8 Cursor-Color 0, 1 RGB Registers 2–44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.9 Cursor-RAM Address Register 2–45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.10 Cursor-RAM Data Register 2–45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.11 Auxiliary Control Register 2–46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.12 Color-Key-Control Register 2–46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.13 Color-Key (Red, Green, Blue, Overlay) Low and High Registers 2–47. . . .

2.16.14 Overscan-Color RGB Registers 2–48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.15 CRC LSB and MSB Registers 2–49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.16 CRC-Control Register 2–49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Electrical Characteristics 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range 3–1. . . .

3.2 Recommended Operating Conditions 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Electrical Characteristics 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Operating Characteristics 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 Timing Requirements 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6 Switching Characteristics 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7 Timing Diagrams 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Appendix A PC Board Layout Considerations A–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Appendix B RCLK Frequency < VCLK Frequency B–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Appendix C Little-Endian and Big-Endian Data Formats C–1. . . . . . . . . . . . . . . . . . . . . . .

Appendix D Examples: Register Settings D–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Appendix E Mechanical Data E–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Illustrations

Figure Title Page

1–1 Functional Block Diagram 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–2 Terminal Assignments 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–1 Dot Clock/VCLK/RCLK/SCLK Relationship 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 SCLK/VCLK Control Timing

(SSRT Disabled, RCLK/SCLK Frequency = VCLK Frequency) 2–9. . . . . . . . . . . . . . . .

2–3 SCLK/VCLK Control Timing

(SSRT Enabled, RCLK/SCLK Frequency = VCLK Frequency) 2–10. . . . . . . . . . . . . . . . .

2–4 SCLK/VCLK Control Timing

(SSRT Disabled, RCLK/SCLK Frequency = 4 x VCLK Frequency) 2–10. . . . . . . . . . . . .

2–5 SCLK/VCLK Control Timing

(SSRT Enabled, RCLK/SCLK Frequency = 4 x VCLK Frequency) 2–11. . . . . . . . . . . . .

2–6 Cursor-RAM Organization 2–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–7 Common Sprite-Origin Settings 2–25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–8 Dual-Cursor Positioning 2–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–9 One Possible Custom Cursor Creation 2–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–10 VGA in the Auxiliary Window 2–29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–11 Multiple VGA Windows Using Port Select (PSEL) 2–29. . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–12 Overscan 2–31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–13 Equivalent Circuit of the Current Output (IOG) 2–34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–14 Composite Video Output (With 7.5 IRE, 8-Bit Output) 2–35. . . . . . . . . . . . . . . . . . . . . . . .

2–15 Composite Video Output (With 0 IRE, 8-Bit Output) 2–35. . . . . . . . . . . . . . . . . . . . . . . . . .

2–16 Split Shift-Register-Transfer Timing 2–36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1 MPU Interface Timing 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 Video Input/Output Timing 3–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–3 SFLAG Timing (When SSRT Function is Enabled) 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . .

A–1 Typical Connection Diagram and Parts A–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A–2 Typical Component Placement With Split-Power Plane A–4. . . . . . . . . . . . . . . . . . . . . . .

B–1 VCLK and SCLK Phase Relationship (Case 1) B–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B–2 VCLK and SCLK Phase Relationship (Case 2) B–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C–1 Little-Endian and Big-Endian Mapping of 8-Bit/Pixel Pseudo-Color Data in

Memory to Monitor Screen C–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Tables

Table Title Page

2–1 Direct Register Map 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 Indirect Register Map (Extended Registers) 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–3 Allocation of Palette-Page Register Bits 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–4 Input-Clock-Selection Register 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–5 Output-Clock-Selection Register Format 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–6 Multiplex Mode and Bus-Width Selection 2–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–7 Pseudo-Color Mode Pixel-Latching Sequence 2–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–8 Direct-Color Mode Pixel-Latching Sequence (Little-Endian) 2–19. . . . . . . . . . . . . . . . . . .

2–9 Direct-Color Mode Pixel-Latching Sequence (Big-Endian) 2–20. . . . . . . . . . . . . . . . . . . .

2–10 True-Color Mode Pixel-Latching Sequence (Little-Endian) 2–21. . . . . . . . . . . . . . . . . . . .

2–11 True-Color Mode Pixel-Latching Sequence (Big-Endian) 2–22. . . . . . . . . . . . . . . . . . . . . .

2–12 Configuration Register 2–37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–13 General-Control Register 2–38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–14 Cursor-Control Register 2–39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D–1 8-Bit/Pixel Pseudo-Color (32-Bit Pixel Bus, 4:1) Self-Clocked, LCLK

and RCLK Enabled D–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D–2 24-Bit True Color (32-Bit Pixel Bus, 1:1) Self-Clocked, RCLK = LCLK Internal D–1. . .

D–3 24-Bit Direct Color (32-Bit Pixel Bus, 1:1) Self-Clocked, No Overlay D–1. . . . . . . . . . . .

D–4 24-Bit Direct Color (32-Bit Pixel Bus, 1:1) Self-Clocked,

Overlay PSEL Switched D–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D–5 24-Bit Direct Color (32-Bit Pixel Bus, 1:1) Externally-Clocked, VGA PSEL Switched

Overlay Auxiliary Window Switched D–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D–6 16-Bit Direct Color (32-Bit Pixel Bus, 2:1) Self-Clocked,

Overlay Auxiliary Window Switched D–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 Introduction

The TVP3010 palette is an advanced Video Interface Palette (VIP) from Texas Instruments implemented in the EPIC 0.8-micron CMOS process. Maximum flexibility is provided by the pixel multiplexing scheme. The scheme accommodates 64-, 32-, 16-, 8-, and 4-bit pixel buses without any circuit modification. This enables the system to be easily reconfigured for varying amounts of available video RAM. The device supports selection of little- or big-endian data format for the pixel-bus/frame-buffer interface. Data can be split into 1, 2, 4, or 8 bit planes for pseudo-color mode or split into 12-, 16- or 24-bit true-color and direct-color modes. For the 24-bit direct color modes, an 8-bit overlay plane is available. The 16-bit direct- and true-color modes can be configured to IBM XGA An additional 12-bit mode (4, 4, 4, 4) is supported with 4 bits for each color and overlay. An on-chip, IBM XGA-compatible hardware cursor is incorporated so that further increases in graphics system performance are possible. The device is also software compatible with the IMSG176/8 and Bt476/8 color palettes.

An internal frequency doubler is incorporated, allowing convenient and cost-effective clock source alternatives to be utilized. An auxiliary windowing function and a pixel-port-select function are provided so that overlay or VGA graphics can be displayed on top of direct color inside or outside a specified auxiliary window. Color-keyed switching of direct color and overlay is also supported.

Clocking is provided through one of five TTL inputs, CLK0–CLK4, and is software selectable. Additionally , CLK1/CLK2 and CLK3/CLK4 can be selected as differential ECL clock sources. The video, shift clock, and reference clock outputs provide a software-selected divide ratio of the chosen clock input. The reference clock can optionally be provided as an output on CLK3, and a data latch clock can optionally be input on CLK4.

The TVP3010 has three 256-by-8 color lookup tables with triple 8-bit video digital-to-analog converters (DACs) capable of directly driving a doubly terminated 75-Ω line. The lookup tables are designed with a dual-ported RAM architecture that enables ultra-high speed operation. Sync generation is incorporated on the green output channel. Horizontal sync and vertical sync are fed through the device and optionally inverted to indicate screen resolution to the monitor. A palette-page register is used to provide the additional bits of palette address when 1, 2, or 4 bit planes are used. This allows the screen colors to be changed with only one microprocessor interface unit (MPU) write cycle.

The device features a separate VGA bus that allows data from the feature connector of most VGA-supported personal computers to be fed directly into the palette without the need for external data multiplexing. This allows a replacement graphics board to remain downwards compatible by utilizing the existing graphics circuitry often located on the motherboard.

The TVP3010 VIP is highly system integrated. It can be connected to the serial port of VRAM devices without external buffer logic and connected to many graphics engines directly. The split shift-register transfer function, which is supported by VRAM, is also supported by the TVP3010.

The system-integration concept is carried to manufacturing test and field diagnosis. To support these, several highly integrated test functions have been designed to enable simplified testing of the palette, the graphics board, and the graphics system.

The 32-bit TVP3010 is pin compatible with the TLC3407X VIP, allowing convenient performance upgrades when using devices in the TI Video Interface Palette family.

The TVP3010 includes circuits that are patented and circuit designs that have patents pending.



(5, 6, 5), T ARGA (5, 5, 5, 1), or (6, 6, 4) as another existing format.

NOTE:

EPIC is a trademark of Texas Instruments Incorporated. XGA is a registered trademark of IBM. TARGA is a registered trademark of Truevision Incorporated.

1–1

1.1 Features

• Second-Generation Video Interface Palette

• Supports System Resolutions of:

– 1600 × 1280 × 1, 2, 4, 8, 16 Bits/Pixel @ 60-Hz Refresh Rate – 1280 × 1024 × 1, 2, 4, 8, 16 Bits/Pixel @ 60-Hz and 72-Hz Refresh Rate – 1024 × 768 × 1, 2, 4, 8, 16, 24 Bits/Pixel @ 60-Hz and 72-Hz Refresh Rate – And lower resolutions

• Direct-Color Modes: – 24-Bit/Pixel with 8-Bit Overlay

– 16-Bit/Pixel (5, 6, 5) XGA Configuration – 16-Bit/Pixel (6, 6, 4) Configuration – 15-Bit/Pixel With 1 Bit Overlay (5, 5, 5, 1) TARGA Configuration – 12-Bit/Pixel With 4 Bit Overlay (4, 4, 4, 4)

• True-Color Modes: – 24-Bit/Pixel With Gamma Correction

– 16-Bit/Pixel (5, 6, 5) XGA Configuration With Gamma Correction – 16-Bit/Pixel (6, 6, 4) Configuration with Gamma Correction – 15-Bit/Pixel (5, 5, 5) TARGA Configuration With Gamma Correction – 12-Bit/Pixel (4, 4, 4) With Gamma Correction

• RCLK/SCLK/LCLK Data Latching Mechanism Allows Flexible Control of VRAM Timing

• Direct Interfacing to Video RAM

• Support for Split Shift-Register Transfers

• 64-Bit-Wide Pixel Bus

• On-Chip Hardware Cursor:

– 64 × 64 × 2 Cursor (XGA Functionally Compatible) – Full-Window Crosshair – Dual-Cursor Mode

• 85-,110-,135-, and 170-MHz Versions

• Supports Overscan for Creation of Custom Screen Borders

• Versatile Pixel Bus Interface Supports Little- and Big-Endian Data Formats

• Windowed Overlay and VGA Capability

• Color-Keyed Switching of Direct Color and Overlay

• On-Chip Clock Selection

• Internal Frequency Doubler

• Triple 8-Bit D/A Converters

• Analog Output Comparators

• Triple 256 × 8 Color Palette RAMs

• RS-343A Compatible Outputs

• Direct VGA Pass-Through Capability

• Palette-Page Register

• Horizontal Zooming Capability

• Software Downward Compatible With IMSG176/8 and Bt476/8

• Directly Interfaces to Graphics Processors

• EPIC 0.8-µm CMOS Process

1–2

1.2 Functional Block Diagram

True-Color

32 32

P(0–31)

VGA(0–7)

D(0–7)

RS(0–2)

Input

Latch

Input

Latch

MPU

Registers

and

Control

Logic

Multiplexer

Pseudo-

Color

MUX

1:1 2:1 4:1

8:1 16:1 32:1

Clock Select

2 4 8

and

Control

8–8–8 6–6–4 5–6–5 5–5–5 4–4–4

24 16 16 15

Read

Mask

Frequency

Doubler

12-24

Stuffing

Logic

Page

8 8

Reg

8 24

Color-Key

Switch

24 24

8 8

64 × 64

Cursor

Control

RAM

and

Direct-Color

Pipeline Delay

256 × 8

Red

RAM

256 × 8

Green

RAM

256 × 8

Blue

RAM

1 × 24

Cursor

Color 0

1 × 24

Cursor

Color 1

1 × 24

Overscan

Auxiliary Window

ref

1.235 V

Output

and

Port Select

REF

MUX

FS ADJUST

DAC

Test Function

and

Sense Comparator

Video-Signal

Control

COMP

IOR

IOG

IOB

MUXOUT [SENSE] HSYNCOUT

VSYNCOUT

CLK0

SFLAG

CLK1/CLK2

VCLK

SCLK

CLK4 [LCLK]

CLK3 [RCLK]

8/6 [OVS]

Figure 1–1. Functional Block Diagram

RS3 [PSEL]

VSYNC

HSYNC

VGABL

SYSBL

1–3

1.3 Terminal Assignments

P19

P18

P20

P21

P22

P23

P24

10 9 8 7 611 5

P17

P16

P15

P14

P13

P12

P11

P10

20 21

RS0

34 35

37 38 39 40

P27

P26

3214

P28

84 83

P25

41 42 43 44 45

P30

P29

82 81 80 79

46 47 48 49

P31

GND

SCLK

78 77 76 75

VCLK

CLK0

CLK1COMP

50 51 52 53

CLK2

74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54

CLK3[RCLK]

[LCLK]

CLK4 VGA7 VGA6 VGA5 VGA4 VGA3 VGA2 VGA1 VGA0 8/6[OVS] MUXOUT

[SENSE] SFLAG VGABL SYSBL VSYNC HSYNC AV

GND AV

GND

1–4

RS1

D0D1D2D3D4

RS2

RS3[PSEL]

GND

IOR

IOG

VSYNCOUT

HSYNCOUT

IOB

Figure 1–2. Terminal Assignments

REF

FS ADJUST

1.4 Ordering Information

I/O

DESCRIPTION

TVP3010 – XXX XX

Pixel Clock Frequency Indicator

MUST CONTAIN THREE CHARACTERS:

–85: 85-MHz pixel clock

–110: 110-MHz pixel clock –135: 135-MHz pixel clock –170: 170-MHz pixel clock

Package

MUST CONTAIN TWO LETTERS:

FN: square plastic J-leaded chip carrier (formed leads)

1.5 Terminal Functions

TERMINAL

NAME NO.

CLK0 77 I

CLK1, CLK2 75, 76 I

CLK3[RCLK] 74 I/O Dot clock 3 TTL input or reference clock output. When configured as

CLK4[LCLK] 73 I Dot clock 4 TTL input or pixel-port latch clock. This terminal can be

COMP 52 I Compensation. COMP provides compensation for the internal

D(0–7) 36–43 I/O

FS ADJUST 51 I Full-scale adjustment. A resistor connected between this terminal and

NOTE: All unused inputs should be tied to a logic level and not be allowed to float.

55, 57 Analog power. All AVDD terminals must be connected.

(TTL

compatible)

(TTL/ECL

compatible)

45, 81 Digital power. All DVDD terminals must be connected.

(TTL

compatible)

Dot clock 0 input. CLK0 can be selected to drive the dot clock at frequencies up to 140 MHz. When VGA mode is active, the default clock source is CLK0. The maximum frequency in VGA mode is 85 MHz.

Dual-mode dot clock input. These inputs are essentially ECLcompatible inputs, but two TTL clocks may be used on the CLK1 and CLK2 if so selected in the input clock select register. These inputs may be selected as the dot clock up to the device limit while in the ECL mode or up to 140 MHz in the TTL mode.

CLK3, this terminal is similar to CLK0 and can be selected to drive the dot clock at frequencies up to 140 MHz. When configured as RCLK, this terminal outputs the reference clock signal, which is similar to the SCLK signal but not gated off during blank. This signal can be used for pixel-port timing reference or other system synchronization. The terminal defaults to CLK3 after reset.

configured to drive dot clock frequencies up to 140 MHz, or it can be configured as a latch clock input to latch pixel-port input data. This terminal defaults to CLK4 after reset, and LCLK is internally connected to RCLK to latch pixel-port data.

reference amplifier . A 0.1-µF ceramic capacitor is required between this terminal and A VDD. The COMP capacitor must be as close to the device as possible to avoid noise pick up.

MPU interface data bus. These terminals are used to transfer data in and out of the register map and palette/overlay RAM.

ground controls the full-scale range of the DACs.

1–5

1.5 Terminal Functions (Continued)

I/O

DESCRIPTION

TERMINAL

NAME NO.

GND 44, 54, 56, 80 Ground. All GND terminals must be connected. The GNDs are

HSYNCOUT 46 O

(TTL

compatible)

IOR, IOG, IOB 48, 49, 50 O Analog current outputs. These outputs can drive a 37.5-Ω load

MUXOUT [SENSE] 63 O

(TTL

compatible)

P(0–31) 1–29, 82–84 I

(TTL

compatible)

REF 53 Voltage reference for DACs. An internal voltage reference of

RD 31 I

(TTL

compatible)

RS(0–2) 32–34 I

(TTL

compatible)

RS3, [PSEL] 35 I

(TTL

compatible)

SCLK 79 O

(TTL

compatible)

NOTE: All unused inputs should be tied to a logic level and not be allowed to float.

connected internally . Horizontal sync output after pipeline delay . For system mode the

output can be programmed, but for the VGA mode the output carries the same polarity as the input.

directly (doubly terminated 75-Ω line), thus eliminating the requirement for any external buffering.

Multiplexer output control or DAC comparator output signal. When this terminal is configured as a multiplexer output control, it is software programmable through the configuration register. When the multiplexer control register is set to VGA mode, this output terminal and corresponding configuration register bit are set low to indicate to external devices that VGA pass through mode is being used. Alternatively, this terminal can be configured as the DAC comparator output. In this case, the terminal is low if one or more of the DAC output analog levels is above the internal comparator reference of 350 mV " 50 mV.

Pixel input port. The port can be used in various modes as shown in the multiplexer control register. All the unused terminals need to be tied to GND.

nominally 1.235 V is provided, which requires an external 0.1-µF ceramic capacitor between REF and analog GND. However, the internal reference voltage can be overdriven by an externally supplied reference voltage. Typical connection is shown in Appendix A.

Read strobe input. A logic 0 on this terminal initiates a read from the register map. Reads are performed asynchronously and are initiated on the low-going edge of RD

Register-select input or port-select input. When configured as the RS3 input, this terminal has no effect. When configured as the port select input, this terminal allows the creation of VGA or overlay windows in a direct color background on a pixel-by-pixel basis.

Shift-clock output. SCLK is selected as a division of the dot clock input. The output signals are gated off during blank, although SCLK is still used internally to synchronize with the activation of blank

(see Figure 3–1).

1–6

1.5 Terminal Functions (Continued)

I/O

DESCRIPTION

TERMINAL

NAME NO.

SFLAG 62 I

SYSBL 60 I

HSYNC, VSYNC

VCLK 78 O

VGABL 61 I

VGA(0–7) 65–72 I

VSYNCOUT 47 O

WR 30 I

8/6 [OVS] 64 I

NOTE: All unused inputs should be tied to a logic level and not be allowed to float.

58, 59 I

(TTL

compatible)

(TTL

compatible)

(TTL

compatible)

(TTL

compatible)

(TTL

capability)

(TTL

capability)

(TTL

capability)

(TTL

capability)

(TTL

capability)

Split shift-register-transfer flag. The TVP3010 VIP detects a lowto-high transition on this terminal during a blank sequence and immediately generates an SCLK pulse. This early SCLK pulse replaces the first SCLK pulse in the normal sequence.

System blank input. SYSBL is active (low).

Horizontal and vertical sync inputs. These signals are used to generate the sync level on the green current output. They are active (low) inputs, but the HSYNCOUT and VSYNCOUT outputs can be programmed through general control register .

Video clock output. VCLK is the user-programmable output for synchronization to graphics processor.

VGA blank input. VGABL is active (low).

VGA pass-through bus. These buses can be selected as the pixel bus for VGA mode, but it does not allow for any multiplexing.

Vertical sync output after pipeline delay . For system mode, the output can be programmed but for the VGA mode, the output carries the same polarity as the input.

Write strobe input. A logic 0 on this terminal initiates a write to the register map. As with RD initiated on the low-going edge of WR

DAC resolution selection or overscan input. This terminal is used to select the data bus width (8 or 6 bits) for the DAC and is essentially provided in order to maintain compatibility with the IMSG176. When this terminal is a logical 1, 8-bit bus transfers are used with D7 the MSB and D0 the LSB. For 6-bit bus operation, while the color palette still has the 8-bit information D5 shifts to the bit 7 position with D0 shifted to the bit 2 position and the two LSBs are filled with zeros at the output multiplexer to DAC. The palette holding register zeroes the two MSBs when it is read in the 6-bit mode. The terminal can also be configured to function as the overscan input facilitating the creation of custom screen borders. This terminal defaults to 8/6

, write transfers are asynchronous and

, (see Figure 3–1).

after reset.

1–7

1–8

2 Detailed Description

The 32-bit TVP3010 is pin compatible with the TLC34076 but offers advanced features. To facilitate the enhanced functionality , some terminals have dual functions. The dual-function terminals are controlled by the configuration register discussed in Section 2.16.1. At reset, all terminals default to the TLC34076 terminal functions.

2.1 MPU Interface

The processor interface is controlled via read and write strobes (RD, WR), three register-select terminals [RS(0–2)], and the 8/6 path to the color-palette RAM and is provided in order to maintain compatibility with the IMSG176. Since

[OVS] terminal is a dual-function terminal, two bits are provided in the configuration register to control

the 8/6 this function. Configuration register bit 1 determines whether the 8/6 If configuration register bit 1 is set to logic 0 (default), then 8/6 operation is controlled by the terminal. With

held low, data on the lowest six bits of the data bus are internally shifted up by two bits to occupy the

8/6 upper six bits at the output multiplexer and the bottom two bits are then zeroed. This operation is carried out in order to utilize the maximum range of the DACs.

The direct register map is shown in Table 2–1. Extended registers can be accessed through the index register. The index register map is shown in Table 2–2. In general, the index register must first be loaded with the target address value. Successive reads or writes from and to the data register then access the target location. The MPU interface operates asynchronously, with data transfers being synchronized by internal logic.

RS3 is a don’t care for register addressing but is used as the PSEL input. See Section 2.6.

RS2 RS1 RS0 REGISTER ADDRESSED BY MPU R/W DEFAULT (HEX)

0 0 0 Palette-Address Register – W rite Mode R/W XX 0 0 1 Color-Palette Holding Register R/W XX 0 1 0 Pixel Read Mask R/W FF 0 1 1 Palette-Address Register – Read Mode R/W XX 1 0 0 Reserved XX 1 0 1 Reserved XX 1 1 0 Index Register R/W XX 1 1 1 Data Register R/W XX

-select terminal. The 8/6 terminal is used to select between an 8- or 6-bit-wide data

[OVS] terminal operates as 8/6 or OVS.

NOTE:

T able 2–1. Direct Register Map

T able 2–2. Indirect Register Map (Extended Registers)

INDEX REGISTER

(HEX)

00 R/W 00 Cursor-Position X LSB 01 R/W 00 Cursor-Position X MSB 02 R/W 00 Cursor-Position Y LSB 03 R/W 00 Cursor-Position Y MSB

NOTE: Reserved registers should be avoided; otherwise, circuit behavior could deviate

from that specified. Reserved-undefined registers are nonexistent locations on the register map.

R/W

DEFAULT

(HEX)

BY INDEX REGISTER

2–1

T able 2–2. Indirect Register Map (Extended Registers) (Continued)

INDEX REGISTER

(HEX)

04 R/W 1F Sprite-Origin X 05 R/W 1F Sprite-Origin Y 06 R/W 00 Cursor-Control Register 07 Reserved 08 W XX Cursor-RAM Address LSB

09 W XX Cursor-RAM Address MSB 0A R/W XX Cursor-RAM Data 0B Reserved

0C–0F Reserved-Undefined

10 R/W XX Window-Start X LSB

11 R/W XX Window-Start X MSB

12 R/W XX Window-Stop X LSB

13 R/W XX Window-Stop X MSB

14 R/W XX Window-Start Y LSB

15 R/W XX Window-Start Y MSB

16 R/W XX Window-Stop Y LSB

17 R/W XX Window-Stop Y MSB

18 R/W 80 Multiplexer-Control Register 1

19 R/W 98 Multiplexer-Control Register 2 1A R/W 00 Input-Clock-Selection Register 1B R/W 3E Output-Clock-Selection Register 1C R/W 00 Palette-Page Register 1D R/W 20 General-Control Register 1E R/W 00 Configuration Register

1F Reserved-Undefined

20 R/W XX Overscan Color Red

21 R/W XX Overscan Color Green

22 R/W XX Overscan Color Blue

23 R/W XX Cursor Color 0, Red

24 R/W XX Cursor Color 0, Green

25 R/W XX Cursor Color 0, Blue

26 R/W XX Cursor Color 1, Red

27 R/W XX Cursor Color 1, Green

28 R/W XX Cursor Color 1, Blue

29 R/W 09 Auxiliary-Control Register

NOTE: Reserved registers should be avoided; otherwise, circuit behavior could deviate

from that specified. Reserved-undefined registers are nonexistent locations on the register map.

R/W

DEFAULT

(HEX)

BY INDEX REGISTER

2–2

T able 2–2. Indirect Register Map (Extended Registers) (Continued)

INDEX REGISTER

(HEX)

2A Reserved 2B Reserved 2C Reserved 2D Reserved 2E Reserved

2F Reserved

30 R/W XX Color-Key OL/VGA Low

31 R/W XX Color-Key OL/VGA High

32 R/W XX Color-Key Red Low

33 R/W XX Color-Key Red High

34 R/W XX Color-Key Green Low

35 R/W XX Color-Key Green High

36 R/W XX Color-Key Blue Low

37 R/W XX Color-Key Blue High

38 R/W 10 Color-Key Control Register

39 Reserved-Undefined 3A R/W 00 Sense Test Register 3B R XX Test Data Register 3C R XX CRC LSB 3D R XX CRC MSB 3E W XX CRC Control Register

3F R 10 ID Register FF W XX Reset Register

NOTE: Reserved registers should be avoided; otherwise, circuit behavior could deviate

from that specified. Reserved-undefined registers are nonexistent locations on the register map.

R/W

DEFAULT

(HEX)

BY INDEX REGISTER

2.2 Color Palette

The color palette is addressed by an internal 8-bit address register for reading/writing data from/to the RAM. This register is automatically incremented following a RAM transfer, allowing the entire palette to be read/written with only one access of the address register. When the address register increments beyond the last location in RAM, it is reset to the first location (address 0). All read and write accesses to the RAM are asynchronous to SCLK, VCLK, and dot clock but performed within one dot clock. Therefore, they do not cause any noticeable disturbance on the display .

The color RAM is 24 bits wide for each location and 8 bits wide for each color. Since the MPU access is eight bits wide, the color data stored in the palette is eight bits even when the six-bit mode is chosen (8/6 If the six-bit mode is chosen, the two MSBs of color data in the palette have the values previously written. However, if they are read back in the six-bit mode, the two MSBs are 0s to be compatible with IMSG176 and Bt176. The output multiplexer shifts the six LSB bits to the six MSB positions and fills the two LSBs with 0s after the color palette. The multiplexer then feeds the data to the DAC. The test register and the CRC calculation both take data after the output multiplexer, enabling total system verification. The color-palette access is described in the following two sections, and it is fully compatible with IMSG176/8 and Bt476/8.

= 0).

2–3

2.2.1 Writing to Color-Palette RAM

T o load the color palette, the MPU must first write to the address register (write mode) with the address where the modification is to start. This is then followed by three successive writes to the palette holding register with eight bits of red, green, and blue data. After the blue write cycle, the three bytes of color data are concatenated into a 24-bit word that is then written to the RAM location specified by the address register. The address register then increments to the next location, which the MPU may modify by simply writing another sequence of red, green, and blue data. A block of color values in consecutive locations may be written to by writing the start address and performing continuous red, green, and blue write cycles until the entire block has been written.

2.2.2 Reading From Color-Palette RAM

Reading from the palette is performed by writing to the address register (read mode) with the location to be read. This then initiates a transfer from the palette RAM into the holding register, followed by an increment of the address register. Three successive MPU reads from the holding register produce red, green, and blue color data (6 or 8 bits depending on the 8/6

mode) for the specified location. Following the blue read cycle, the contents of the color-palette RAM at the address specified by the address register are copied into the holding register and the address register is again incremented. As with writing to the palette, a block of color values in consecutive locations may be read by writing the start address and performing continuous red, green, and blue read cycles until the entire block has been read. Since the color-palette RAM is dual ported, the RAM may be read during active display without disturbing the video.

2.2.3 Palette-Page Register

The palette-page register appears as an 8-bit register on the extended register map (see Section 2.1). Its purpose is to provide high-speed color changing by removing the need for palette reloading. When using 1, 2, or 4 bit planes, the additional planes are provided from the page register. When using four bit planes, the pixel inputs specify the lower four bits of the palette address with the upper four bits specified from the page register. This gives the user the capability of selecting from 16 palette pages with only one chip access, thus allowing all the screen colors to be changed at the line frequency . A bit-to-bit correspondence is used; therefore, in the above configuration, page-register bits 7 through 4 map onto palette-address bits 7 through 4, respectively. This is illustrated in Table 2–3.

NOTE:

The additional bits from the page register are inserted after the read mask. The palette-page register specifies the additional bit planes for the overlay field in

direct-color modes with less than 8 bits per pixel overlay .

T able 2–3. Allocation of Palette-Page Register Bits

NUMBER OF BIT PLANES MSB PALETTE-ADDRESS BITS LSB

8 M M M M M M M M 4 P7 P6 P5 P4 M M M M 2 P7 P6 P5 P4 P3 P2 M M

1 P7 P6 P5 P4 P3 P2 P1 M Pn = n bit from page register M = bit from pixel port

2.2.4 Read Masking

The read-mask register is an 8-bit register used to enable or disable a bit plane from addressing the color-palette RAM in the pseudo-color modes. Each palette address bit is logically ANDed with the corresponding bit from the read mask register before going to the palette-page register and addressing the palette RAM.

In order to provide maximum flexibility to control palette data, the read mask operation is performed before the addition of the page register bits. Therefore, care must be taken in those modes that have less than eight bits per pixel of pseudo-color or overlay data. Be aware of the palette-page register settings in these modes.

2–4

2.3 Clock Selection and Output-Clock (SCLK, RCLK, and VCLK) Generation

The TVP3010 VIP provides a maximum of five clock inputs. One of them (CLK0) is dedicated as a TTL input. The other four can be selected as either two differential ECL input or two extra TTL inputs. The TTL inputs can be used for video rates up to 140 MHz. The dual-mode clock input (ECL/TTL) is primarily an ECL input but can be used as TTL-compatible inputs if the input-clock-selection register is so programmed. The clock source used at power up is CLK0; an alternative source can be selected by software during normal operation. This chosen clock input can be used unmodified as the dot clock (representing pixel rate to the monitor). Alternatively, if the input-clock-selection register is programmed to use the internal frequency doubler, the chosen clock source is used as a reference for multiplication. The device also allows for user programming of RCLK, SCLK and VCLK outputs (reference, shift and video clocks) by using the output-clock-selection register. The input-clock- and output-clock-selection registers are shown in Tables 2–4 and 2–5 and are located in the indirect register map (see Table 2–2).

The ECL inputs can be used as a differential or single-ended inputs. If CLK1 or CLK3 is used as a single-ended ECL input, CLK2 or CLK4 needs to be externally terminated to set the input common-mode signal level. This can be done with a simple resistor divided, as is the case with fully differential ECL. Care needs to be taken when choosing the resistor values to ensure that the dc level on CLK2 or CLK4 is in the middle of the CLK1 or CLK3 ECL-input signal range.

2.3.1 RCLK, SCLK, VCLK

The TVP3010 VIP provides user-programmable reference clock (RCLK), shift clock (SCLK), and video (VCLK) clock outputs that can be set as divisions of the dot clock. RCLK is a continuously running reference clock and is not disabled during blank. RCLK can be selected as divisions of 1, 2, 4, 8, 16, 32 or 64 of the dot clock (see Table 2–5). It is provided as a clock reference and is typically connected back to the LCLK input to latch pixel-port data. Since pixel-port data is latched on the rising edge of LCLK, the RCLK frequency must be set as a function of the desired multiplexing ratio (that depends on the pixel bus width and number of bit planes). See Section 2.4 and Table 2–6.

SCLK is the same as RCLK but disabled during the blank active period. SCLK is designed to be used as the shift clock to interface directly with the VRAM. If SCLK is not used, the output can be switched off and held low to protect against VRAM lockup due to invalid SCLK frequencies. The detailed SCLK control timing is discussed in Section 2.3.2 and illustrated in Figures 2–2 through 2–5.

VCLK is designed to be used as the timing reference by the graphics processor or other custom-designed control logic to generate the graphics system control signals (SYSBL selected as divisions of 1, 2, 4, 8, 16, 32, or 64 of the dot clock and can also be held at logic 1 (see T able 2–5). The default setup is VCLK held at logic 1 since it is not used in VGA pass-through mode. Since these control signals are sampled by VCLK, VCLK must be enabled for these to function properly (see Figures 2–2 through 2–5).

Even though RCLK/SCLK and VCLK can be selected independently, there is still a relationship between the two as discussed below. Many system considerations have been carefully covered in their design, leaving maximum freedom to the user.

Internally , RCLK, SCLK, and VCLK are generated from a common clock counter that is counted at the rising edge of the dot clock. Therefore, when VCLK is enabled, it is naturally in phase with RCLK and SCLK as shown in Figure 2–1.

Normally, the video control signal inputs HSYNC VCLK when in a non-VGA mode. If the configuration register is programmed for opposite VCLK polarity, these video control signals are latched on the rising edge of VCLK.

The internal clock counter is initialized any time the output-clock-selection register is written with 3F (hex). This provides a simple mechanism to synchronize multiple palettes or system devices by providing a known phase relationship for the various system clocks. It is left up to the user to provide some means of disabling the dot clock input to the part while this reset is occurring if multiple parts are to be synchronized.

, VSYNC, and SYSBL are latched on the falling edge of

, HSYNC, and VSYNC). VCLK can be

2–5

The reset default divide ratio for RCLK is 64:1 with SCLK held at logic 0 and VCLK held at logic 1. When choosing certain video timing parameters, exercise caution if the selected RCLK frequency is less than the selected VCLK frequency . Refer to Appendix B for a more detailed discussion.

Dot Clock

(dot clock/4 as an example)

RCLK = SCLK

(dot clock/2 as an example)

VCLK

Figure 2–1. Dot Clock/VCLK/RCLK/SCLK Relationship

The input-clock-selection register is used to select the desired input clock source. T able 2–4 details how to program the various options.

T able 2–4. Input-Clock-Selection Register

INPUT-CLOCK-SELECT REGISTER

†

CLK0 is chosen at reset as required for VGA pass-through.

NOTES: 1. Register bits 3 and 7 are don’t-care bits.

(HEX) (see Note 1)

00 Select CLK0 as TTL clock source 01 Select CLK1 as TTL clock source 02 Select CLK2 as TTL clock source 03 Select CLK3 as TTL clock source 04 Select CLK4 as TTL clock source 06 Select CLK3/CLK4 as ECL clock source up to 140 MHz 07 Select CLK1/CLK2 as ECL clock source up to device limit 10 Select CLK0 as doubled TTL clock source 11 Select CLK1 as doubled TTL clock source 12 Select CLK2 as doubled TTL clock source 13 Select CLK3 as doubled TTL clock source 14 Select CLK4 as doubled TTL clock source 16 Select CLK3/CLK4 as doubled ECL clock source 17 Select CLK1/CLK2 as doubled ECL clock source

2. Register bits 5 and 6 are reserved.

3. When the clocks are selected from one input clock source to another, a minimum of 30 ns is needed before the new clocks are stabilized and running.

FUNCTION (see Note 2)

†

2–6

The output-clock-selection register is used to program the desired divided-down frequencies for the

FUNCTION

(

reference/shift and video clocks.

Table 2–5. Output-Clock-Selection Register Format

OUTPUT-CLOCK-SELECTION-REGISTER BITS (see Note 4)

6 543210

0 0 0 x x x VCLK/1 output ratio 0 0 1 x x x VCLK/2 output ratio 0 1 0 x x x VCLK/4 output ration 0 1 1 x x x VCLK/8 output ratio 1 0 0 x x x VCLK/16 output ratio 1 0 1 x x x VCLK/32 output ratio 1 1 0 x x x VCLK/64 output ratio 1 1 1 x x x VCLK output held at logic 1 x x x 0 0 0 RCLK/1 output ratio (see Notes 4 and 7) x x x 0 0 1 RCLK/2 output ratio (see Notes 4 and 7) x x x 0 1 0 RCLK/4 output ratio (see Notes 4 and 7) x x x 0 1 1 RCLK/8 output ratio (see Notes 4 and 7) x x x 1 0 0 RCLK/16 output ratio (see Notes 4 and 7) x x x 1 0 1 RCLK/32 output ratio (see Notes 4 and 7)

x x x 1 1 0 RCLK/64 output ratio (see Notes 4 and 7) 0 x x x 1 1 0 RCLK/64, SCLK output held at logic 0 0 x x x 1 1 1 RCLK, SCLK outputs held at logic 0 x 1 1 1 1 1 1 Clock counter reset (6)

†

These lines indicate the reset conditions as required for VGA pass-through.

NOTES: 4. Register bit 6 enables (logic 1) and disables (default – logic 0) the SCLK output buffer. Register

bit 7 is a don’t care bit.

5. When the clocks are selected from one mode to the other, a minimum of 30 ns is needed before the new clocks are stabilized and running.

6. When the output-clock-selection register is written with 3F (hex), the clock counter is reset, RCLK = SCLK = logic 0, and VCLK = logic 1.

7. SCLK is the same as RCLK except that it is disabled during blank. When the RCLK divide ratio is chosen, this sets the SCLK ratio as well.

see Notes 4, 5, 6, and

†

2.3.2 Frame-Buffer Clocking: Self- or Externally Clocked

The TVP3010 VIP has two pixel-data latching modes, allowing for flexibility in the frame-buffer interface timing. For the pixel port [P(0–31)], data is always latched on the rising edge of LCLK. If auxiliary-control register (ACR) bit 3 is set to logic 1 (default), the internal circuitry is configured for self-clocked mode. In this mode, the RCLK or SCLK output of the palette must be used as the timing reference to present data to the pixel port [P(0–31)]. In self-clocked mode, RCLK can be directly tied back to LCLK or LCLK can be a delayed version of RCLK within the timing requirements of the TVP3010. The self-clocked mode of frame-buffer latching is similar to the operation of the TLC3407X video interface palette devices.

The internal TVP3010 blank signal is generated from either VGABL VGA port is enabled (multiplex-control register 2 (MCR2) bit 7 = logic 1) or disabled (MCR2 bit 7 = logic 0). The rising edge of CLK0 is used to latch VGABL is used to sample and latch the SYSBL

when the VGA port is enabled. The falling edge of VCLK

input when the VGA port is disabled. When the internal blank

becomes active, SCLK is disabled as soon as possible. For example, if SCLK is high when the sampled

goes low, SCLK is allowed to complete the clock cycle and return to the low state. SCLK then is held

SYSBL

or SYSBL, depending on whether the

2–7

low until the sampled SYSBL signal goes back high. At this time, SCLK is enabled to clock the first pixel data valid from VRAM. The TVP3010 video blanking circuitry is designed with sufficient pipeline delay to allow the internal sampled SYSBL

and VGABL signals to align with the pipelined RGB data to the video DACs. The logic described above works in situations where the SCLK period is shorter than, equal to, or longer than the VCLK period.

When in the self-clocked mode, the SCLK control timing is designed to interface directly with the external VRAM. The shift register in the system VRAM is supposed to be updated during the blank active period. When the SYSBL

input is sampled high by the falling edge of VCLK, the VRAM shift clock (SCLK) is restarted to clock the VRAM and enable the first group of pixel data to appear on the pixel bus as well as at the TVP3010 pixel input port. The second SCLK causes the VRAM shift register to shift out the second group of data. At the same time, LCLK latches the first group of pixel data into the VIP (refer to Figure 2–2 for a detailed timing diagram).

The RCLK/SCLK phase relationship is designed such that timing specifications are satisfied for the case where SCLK is driving a typical 2-MB VRAM load and RCLK is connected to LCLK. If an external buffer is required on SCLK so that it can drive a larger load, a similar buffer can be placed on RCLK to match the signal delay before connecting to LCLK. However, the delay from LCLK to RCLK cannot exceed one RCLK period –7 ns. Please refer to the timing parameter specifications for more details.

When the VRAM split shift-register operation is performed (see Figure 2–3), the SCLK timing is adjusted to work with the SFLAG input. Basically, the split shift-register operation inserts an SCLK during the blank period. This causes the first group of pixel data to appear at the pixel port during blank and allows the first group of data to be displayed as soon as the palette comes out of blank. Figures 2–3 and 2–5 show the case when the SSRT (split shift-register transfer) function is enabled. When a rising edge occurs on the SFLAG input, one SCLK with a minimum 15-ns pulse duration is generated after the specified delay. Since this is designed to meet VRAM timing requirements, the SSRT-generated SCLK replaces the first SCLK in the regular shift register transfer case as described above. Refer to Section 2.15 for a detailed explanation of the SSRT function.

Externally clocked timing can be chosen for the pixel bus [P(0–31)] by setting auxiliary control register bit 3 to a logic 0. In externally clocked mode, the RCLK or SCLK output of the palette is not used as the timing reference to present data to the pixel bus. Instead, pixel data is presented to the palette with a synchronous clock and all palette timing is referenced to this clock. In this mode, the external clock should be connected to LCLK and the selected clock input. (If the VGA port is enabled, the CLK0 input is selected independent of the input clock selection register.)

The externally clocked frame-buffer interface mode is intended for applications where windowed or pixel-by-pixel switching between the VGA port and the pixel port is desired in non-VRAM-based graphics systems. In such applications, the VGA port is enabled (multiplex-control register bit 7 set to logic 1) and the appropriate direct-color mode is set in the multiplex-control register. The auxiliary window, port select, and/or color-key switching functions are then configured and enabled to perform the desired switching. By setting the frame-buffer interface to the externally clocked mode, the pixel port and VGA port timing and pipeline delay are made the same. Also, since the VGA port is enabled, all video control signal timing is referenced to CLK0, utilizing the VGABL

, HSYNC, and VSYNC inputs.

The externally clocked frame-buffer interface timing can also be used in non-VGA switching applications, utilizing only the pixel port or only the VGA port. In either case, it is recommended that VGA video-control signals be used (i.e., VGABL

, HSYNC, VSYNC). In this way, all pixel data and video control signals are

referenced to CLK0 and video blank and sync are aligned with pixel data.

NOTE:

If the pixel port is used in externally clocked mode (ACR3 = 0), RCLK must be set to DOT/1 in the output-clock-selection register and a 1:1 multiplexing mode must be selected in the multiplexer control registers (see T able 2–6). The external clock

2–8

should be connected to the LCLK input as well as the selected clock input. If the VGA port is also enabled (MCRB7 = 1), CLK0 is selected as the input clock independent of the input-clock-selection register setting.

VGA switching can only be performed using a 1:1 multiplexing mode. Overlay switching can only be performed using a 1:1 multiplexing mode if the pixel

port is set for externally clocked mode. If the pixel port is self-clocked, any of the multiplex ratios available in Table 2–6 may be used.

If VGA switching is to be performed using externally clocked mode (ACR3 = 0), the full VGA port frequency of 85 MHz may be utilized provided that the VGA port and the pixel port are both synchronized to the CLK0 input clock.

If VGA switching is to be performed using self-clocked mode (ACR3 = 1), the maximum pixel rate cannot exceed 50 MHz. This is because of internal delay from the CLK0 input to the RCLK output. For external clocked timing, the LCLK input needs to be enabled on terminal 73 by programming the configuration register bit 5 to logic 1.

VGA data pipeline delay is adjusted within the TVP3010 VIP depending on whether self- or externally-clocked frame-buffer interface timing is used (see Section 2.3.2). If the TVP3010 palette is programmed for self-clocked timing, three additional dot clock pipeline delays are inserted into the internal VGA data path and into the internal blanking signal. The additional pipeline delay accounts for the difference between VGABL

or SYSBL and the pixel data inputs [P(0–31)] when used in the self- and externally-clocked modes. This is so the VGA and pixel-port data remain synchronous in time when doing auxiliary window, port select, or color-keyed switching (see Section 2.6). If externally clocked timing is used, the VGA port and the pixel port are already synchronous since both data and blanking are presented to the palette during the same CLK0 clock cycle.

VCLK

In Phase

SYSBL

at Input Terminal

Internal Delayed

LCLK = RCLK

Blank

(internal signal

before dot clock

pipeline delay)

Pixel Data

at Input Terminal

SCLK

Latch Last Group

of Pixel Data

Last Group of Pixel Data

Latch First Group of Pixel Data

1st

2nd

3rd

Group

4th

Group

Figure 2–2. SCLK/VCLK Control Timing

(SSRT Disabled, RCLK/SCLK Frequency = VCLK Frequency)

5th

Group

Latch Last Group of Pixel Data

6th

Group

2–9

VCLK

In Phase

at Input Terminal

SYSBL

SFLAG Input

Internal Delayed

LCLK = RCLK

Blank

(internal signal

before dot clock

pipeline delay)

Pixel Data

at Input Terminal

SCLK

VCLK

In Phase

Latch Last Group

of Pixel Data

Last

Group

1st Group of

SCLK Between Split Shift-Register and Regular Shift-Register Transfer

Pixel Data

Latch First Group of Pixel Data

2nd

3rd

Group

4th

Group

5th

Group

Figure 2–3. SCLK/VCLK Control Timing

(SSRT Enabled, RCLK/SCLK Frequency = VCLK Frequency)

Latch Last Group of Pixel Data

6th

Group

at Input Terminal

Internal Delayed

LCLK = RCLK

(internal signal

before dot clock

pipeline delay)

Pixel Data

at Input Terminal

2–10

SYSBL

Latch Last Group

of Pixel Data

Latch first Group of Pixel Data

Blank

1st

Last Group of Pixel Data

Group

2nd

Group

SCLK

Figure 2–4. SCLK/VCLK Control Timing

(SSRT Disabled, RCLK/SCLK Frequency = 4 x VCLK Frequency)

3rd

Group

4th

Group

5th

Group

6th

Group

7th

Group

VCLK

In Phase

at Input Terminal

Internal Delayed

before dot clock

at Input Terminal

SYSBL

SFLAG Input

LCLK = RCLK

Blank

(internal signal

pipeline delay)

Pixel Data

SCLK

Latch Last Group of Pixel Data

Last

Group

First Group of Pixel Data

SCLK Between Split Shift-Register Transfer and Regular Shift-Register Transfer

2nd

Group

Latch Second Group of Pixel Data

Latch First Group of Pixel Data

4th

5th

Group

3rd

Group

6th

Group

7th

Group

Figure 2–5. SCLK/VCLK Control Timing

(SSRT Enabled, RCLK/SCLK Frequency = 4 x VCLK Frequency)

2.4 Multiplexing Scheme

The TVP3010 palette offers a highly versatile multiplexing scheme as illustrated in T ables 2–6 through 2–1 1. The multiplexing scheme allows the pixel bus to be programmed to 1, 2, 4, 8, 12, 16, 24, or 32 bits/pixel with pixel bus widths ranging from 1 bit to 32 bits. The use of on-chip multiplexing allows graphics systems to be designed that can support multiple pixel depths and resolutions with no hardware modification. It also allows the system to be configured to the amount of RAM available. For example, if only 256K bytes of memory are available, an 800-by-600 mode with 4 bit planes (four bits per pixel) could be implemented using an 8-bit-wide pixel bus. If at a later date another 256K bytes are added to another 8 bits of the pixel bus, the user has the option of using 8 bit planes at the same resolution or 4 bit planes at a 1024-by-768 resolution. When a further 512K bytes are added to the remaining 16 bits of the pixel bus, the user has the option of 8 bit planes at 1024-by-768 or 4 bit planes at 1280-by-1024. The TVP3010 palette can also be configured for direct-color or true-color operation. All of the above could be achieved without any board-level hardware modification and without any increase in the speed of the pixel bus.

Multiplexing of the pixel bus is controlled by and programmed through multiplex-control registers 1 and 2. T able 2–6 details the multiplex-control register settings for each mode of operation (see also Sections 2.4.2 through 2.4.6).

2.4.1 Little-Endian and Big-Endian Data Format

The TVP3010 pixel bus supports both little- and big-endian data formats for all pseudo-color, direct-color, and true-color modes of operation. The data-format select is controlled by general-control register bit 3 (see Section 2.16.2). When general-control register (GCR) bit 3 is set to 0 (default), then the format is set to little endian. When GCR bit 3 is set to 1, then the format is set to big endian.

In a big-endian design, the external VRAM data bus bits must be connected in reverse order to the VIP pixel bus; i.e., D31 connected to P0, D0 connected to P31, etc. This ensures that the least significant channel

2–11

always provides the first pixel to be displayed in the pseudo-color or true-color multiplexing modes. The difference between little- and big-endian data formats and how they affect the pixel bus operation is discussed in detail in Appendix C.

2.4.2 VGA Pass-Through Mode

The VGA pass-through mode is used to emulate the VGA modes of most personal computers. The advantage of this mode is that it can take data presented on the feature connector of most VGA-compatible PC systems into the device on a separate bus, thus requiring no external multiplexing. This feature is particularly useful in systems where the existing graphics circuitry is on the motherboard. In this instance, it enables a drop-in graphics card to be implemented that maintains compatibility with all existing software. This is accomplished by using the on-board VGA circuitry but routing the emerging bit-plane data through the TVP3010 palette. VGA pass-through is the default mode at power up or reset.

Since this mode is designed with the feature connector philosophy, all data latching and control timing is referenced to CLK0. When the VGA port is enabled (MCR2 bit 7 = 1), CLK0 is selected as the input clock source independent of the input-clock-selection register. The VGA port always operates as in the externally clocked mode of the pixel port [P(0–31)]; it receives the VGA data [VGA(0–7)] and the VGA blank (VGABL both of which are referenced to an external clock (CLK0). CLK0 also latches the VGABL VSYNC on the VGA port since LCLK only latches data on the pixel port [P(0–31)].

VGA data pipeline delay is adjusted within the TVP3010 palette depending on whether self- or externallyclocked frame-buffer interface timing is used (see Section 2.3.2). If TVP3010 is programmed for self-clocked timing, additional dot clock pipeline delay is inserted into the internal VGA data path. The purpose is so that the VGA and pixel port data can remain synchronous when doing auxiliary window, port select, or color-keyed switching (see Section 2.6). The additional VGA pipeline delay accounts for the dot clock to RCLK pipeline delay within the palette.

video-control signals when in the VGA pass-through mode. External signals on LCLK have no effect

, HSYNC, and

2.4.3 Pseudo-Color Mode

In pseudo-color mode (sometimes called color indexing), the pixel-bus inputs are used to address the palette-RAM LUT (color lookup table). The data in each RAM location is comprised of 24 bits (8 bits for each of the red, green, and blue color DACs). The pseudo-color mode is further grouped into 4 submodes, depending on the data bits per pixel. In each submode, a pixel bus width of 4, 8, 16, or 32 bits may be used. Data should always be presented on the least significant bits of the pixel bus; i.e., when 16 bits are used, the pixel data must be presented on P(15 –0), 8 bits on P(7–0), and 4 bits on P(3–0). See Tables 2–6 through 2–11 for more details.

Submode 1 uses a single bit plane to address the color palette. The pixel port bit is fed into bit 0 of the palette address, with the 7 high-order address bits defined by the palette-page register (see Section 2.2.3). This mode has uses in high-resolution monochrome applications such as desktop publishing. This mode allows the maximum amount of multiplexing with 32:1 ratio, thus giving a pixel bus rate of only 4 MHz at a screen resolution of 1280-by-1024. Although only a single bit is used, alteration of the palette-page register at the line frequency allows 256 different colors to be displayed per screen with two colors per line.

Submode 2 uses two bit planes to address the color palette. The two bits are fed into the low-order address bits of the palette with the six high-order address bits being defined by the palette-page register (see Section 2.2.3). This mode allows a maximum multiplex ratio of 16:1 on the pixel bus and is essentially a four-color alternative to submode 1.

Submode 3 uses four bit planes to address the color palette. The four bits are fed into the low-order address bits of the palette with the four high-order address bits being defined by the palette-page register (see Section 2.2.3). This mode provides 16 pages of 16 colors and can be used at multiplex ratios of /1 to /8.

Submode 4 uses eight bit planes to address the color palette. Since all eight bits of palette address are specified from the pixel port, the page register is not used. This mode allows dot clock-to-LCLK ratios of 1:1

2–12

(8-bit bus), 2:1 (16-bit bus), or 4:1 (32-bit bus). Therefore, in a 32-bit configuration, a 1024-by-768 pixel screen can be implemented with an external data rate of only 16 MHz.

NOTE:

If externally clocked frame-buffer timing is used (ACR3 = logic 0, see Section 2.3.2), only multiplex ratios of 1:1 can be used. See Table 2–6.

The auxiliary window, port select, and color-key switching functions must be disabled and set for palette graphics when in the pseudo-color mode. This is the default condition at reset. See Section 2.6

2.4.4 Direct-Color Mode

In direct-color mode, 24, 16, 15, or 12 bits of data can be transferred directly to the RGB DACs but with the same amount of pipeline delay as the overlay data and the control signals (blank and SYNCs). Depending on which direct-color mode is selected, overlay is provided by utilizing the remaining bits of the pixel bus to address the palette RAM. This results in a 24-bit RAM output that is then used as overlay information to the DACs. The overlay capability is designed to work with the auxiliary window, port select, and color-key switching functions to provide overlay in specific windows or on a pixel-by-pixel basis on the direct-color display as discussed in Section 2.6. See Tables 2–6, 2–8, and 2–9 for more details on selecting the direct-color modes.

The default condition after reset is for the auxiliary window and port select functions to be disabled (ACR1 = ACR2 = logic 0). The color-key comparisons, which are controlled by the color-key control (CKC) register bits 0–3, are also disabled (CKC0 = CKC1 = CKC2 = CKC3 = logic 0). Also, since multiplex-control register 2 bit 7 = logic 1 and ACR0 = CKC4 = logic 1 at reset, the default is for VGA pass through. This is because multiplex-control register 2 bit 7 enables the VGA port and the switching functions (switch = color key = 1, see Section 2.6) are disabled and set for palette graphics (as opposed to direct color-palette bypass).

Submode 1 is the 24-bit direct-color mode that uses eight bits to represent each color and eight bits for overlay. In this mode, there are basically two different configurations: either the 32-bit data is grouped as overlay, red, green, blue, or blue, green, red, overlay.

Submode 2 is the XGA-compatible (5–6–5) 16-bit-color mode supporting five bits of red, six bits of green, and five bits of blue data. The TVP3010 supports multiplex ratios for this mode of 1:1 and 2:1. With 2:1 multiplexing, the TVP3010 can display 1024x768 direct-color using 45-MHz VRAM without any glue logic. Overlay is not available in this mode.

Submode 3 is the T ARGA-compatible (5–5–5) mode that uses 15 bits for color and 1 bit for overlay. It allows 5 bits for each of red, green, and blue data. The TVP3010 supports 1:1 and 2:1 multiplexing ratios in this mode.

Submode 4 is (6–6–4) configuration. It provides six bits of red, six bits of green, and four bits of blue. The TVP3010 also supports 1:1 and 2:1 multiplexing in this mode. Overlay is not available in this mode.

Submode 5 is (4–4–4–4) configuration. It provides 12 bits of direct color and 4 bits of overlay . It allows four bits for each of red, green, and blue data. The TVP3010 supports 1:1 and 2:1 multiplexing ratios in this mode.

See NOTES in the following section.

2–13

2.4.5 True-Color Mode

In true-color mode, the palette RAM is partitioned into three independent 256-word × 8-bit memory blocks that can be individually addressed by each color field of the true-color data. The independent memory blocks provide data for a single DAC output. With this architecture, gamma correction for each color is possible. Since the palette is used in true-color mode, there is no memory space to be used for the overlay function. All of the true-color submodes are the same as direct color except that overlay is not available. See T ables 2–6 through 2–1 1 for more details on mode selection. See note below.

NOTE:

Since less than 8 bits are defined for each color in the various 12- or 16-bit director true-color modes, the data bits for the individual colors are internally shifted to the MSB locations and the remaining LSB locations for each color are set to logic 0 before 8-bit data is sent to the DACs.

Since the overlay information goes through the pseudo-color data path, it is subject to read masking and the palette-page register. This is especially important for those direct-color modes that have less than eight bits of overlay information. The overlay information in these modes justifies to the LSB bit positions, and the remaining MSB positions are filled with the corresponding palette-page data before addressing the palette RAM.

In order to display true color (gamma corrected through the palette), either the auxiliary windowing or the color-key switching function must be set for palette graphics. For direct color, both functions must be set for direct color.

In order to use the overlay capability of the direct-color modes, the color-key switching or port-select function must be configured and enabled. Overlay port data in a window is also available by enabling the auxiliary window function. If either the auxiliary windowing or the color-key switching functions point to palette graphics, palette graphics are always displayed (not direct color).

When in the 24-bit direct-color or true-color modes, the data input works only in the 8-bit mode. In other words, if only six bits are used, the two LSB inputs for each color need to be tied to GND. However, the palette, which is used by the overlay input, is still governed by 8/6 accordingly. The 8/6

The definitions of direct color (palette bypass) and true color are consistent with the IBM XGA terminology .

, and the output multiplexer selects 8 bits or 6 bits of data

is also valid in the other 16-bit modes.

2–14

2.4.6 Multiplex-Control Registers

Color

The pixel-port multiplexer is controlled by two 8-bit registers in the indirect register map (see Section 2.1). The various multiplexing modes can be selected according to the following table.

T able 2–6. Multiplex Mode and Bus-Width Selection

DATA

MODE

VGA 80 98 8 8 1 NA v1

PseudoColor

NOTES: 8. Data bits per pixel is the number of bits of pixel port information used as color data for each displayed pixel,

SUB-

MODE

9. Multiplex ratio indicates the number of pixels per bus load or the number of pixels associated with each

10. This column is a reference to Tables 2–7 through 2–1 1, where the actual manipulation of pixel information

11. It is recommended that all unused input terminals be connected to ground to conserve power.

12. Multiplex-control register 2 bit 7 enables (logic 1) and disables (logic 0 ) the VGA port. If auxiliary-window

MULTIPLEX-

CONTROL

(HEX)

80 00 1 4 4 NA s1 80 01 1 8 8 NA s2 80 02 1 16 16 NA s3 80 03 1 32 32 NA s4 80 08 2 4 2 NA s6 80 09 2 8 4 NA s7 80 0A 2 16 8 NA s8 80 0B 2 32 16 NA s9 80 10 4 4 1 NA s11 80 11 4 8 2 NA s12 80 12 4 16 4 NA s13 80 13 4 32 8 NA s14 80 19 8 8 1 NA s16

often referred to as the number of bit planes.

LCLK (load clock) pulse. For example, with a 32-bit pixel bus width and 8 bit planes, each bus load consists of four pixels. In a typical implementation, the LCLK signal is either connected to or derived from RCLK. Therefore, the RCLK divide ratio must be chosen as a function of the multiplex mode selected. The RCLK divide ratio is not automatically set by mode selection but must be programmed in the output clock selection register by the user.

and pixel latching sequences are illustrated for each of the multiplexing modes.

or port-select switching is to be done involving the VGA port, this bit needs to be set to a logic 1 as well as programming for the correct direct-color mode. For example, if auxiliary windowing is to be done with direct-color submode 1 (32-bit pixel bus) and VGA, instead of programming 1B (hex), multiplex-control register 2 should be programmed to 9B (hex). If only VGA pass-through is desired, the values should be programmed for VGA mode as indicated in Table 2–6. If only VGA pass-through is desired, the values should be programmed as indicated in Table 2–6 for VGA mode.

80 1A 8 16 2 NA s17 80 1B 8 32 4 NA s18

MULTIPLEX-

CONTROL

(HEX)

BITS

PER

PIXEL

(see

Note 8)

PIXEL-

BUS

WIDTH

MULTI-

PLEX

RATIO

(see

Note 9)

OVERLA Y

BITS

PER

PIXEL

TABLE

REFERENCE

(see

Note 10)

2–15

T able 2–6. Multiplex Mode and Bus-Width Selection (Continued)

(5–6–5)

(5–5–5)

16-bi

12-bi

DATA

BITS

PER

PIXEL

(see

Note 8)

PIXEL-

BUS

WIDTH

MULTIPLEX-

CONTROL

(HEX)

06 1B 24 32 1 8 d1 07 1B 24 32 1 8 d3 05 02 16 16 1 NA d5

05 03 16 32 2 NA d6 04 02 15 16 1 1 d8 04 03 15 32 2 1 d9 03 02 16 16 1 NA d11 03 03 16 32 2 NA d12 01 12 12 16 1 4 d14 01 13 12 32 2 4 d15

MODE

Direct

NOTES: 9. Data bits per pixel is the number of bits of pixel port information used as color data for each displayed pixel,

SUB-

MODE

24-bit

XGA

TARGA

(6–6–4)

(4–4–4)

often referred to as the number of bit planes.

10. Multiplex ratio indicates the number of pixels per bus load or the number of pixels associated with each LCLK (load clock) pulse. For example, with a 32-bit pixel bus width and 8 bit planes, each bus load consists of four pixels. In a typical implementation, the LCLK signal is either connected to or derived from RCLK. Therefore, the RCLK divide ratio must be chosen as a function of the multiplex mode selected. The RCLK divide ratio is not automatically set by mode selection but must be programmed in the output clock selection register by the user.

11. This column is a reference to Tables 2–8 through 2–1 1, where the actual manipulation of pixel information and pixel latching sequences are illustrated for each of the multiplexing modes.

12. It is recommended that all unused input terminals be connected to ground to conserve power.

13. Multiplex-control register 2 bit 7 enables (logic 1) and disables (logic 0 ) the VGA port. If auxiliary-window or port-select switching is to be done involving the VGA port, this bit needs to be set to a logic 1 as well as programming for the correct direct-color mode. For example, if auxiliary windowing is to be done with direct-color submode 1 (32-bit pixel bus) and VGA, instead of programming 1B (hex), multiplex-control register 2 should be programmed to 9B (hex). If only VGA pass-through is desired, the values should be programmed for VGA mode as indicated in Table 2–6. If only VGA pass-through is desired, the values should be programmed as indicated in Table 2–6 for VGA mode.

MULTIPLEX-

CONTROL

(HEX)

MULTI-

PLEX

RATIO

(see

Note 9)

OVERLA Y

BITS

PER

PIXEL

TABLE

REFERENCE

(see

Note 10)

2–16

T able 2–6. Multiplex Mode and Bus-Width Selection (Continued)

(5–6–5)

True

(5–5–5)

16-bi

12-bi

DATA

BITS PER

PIXEL

(see

Note 8)

PIXEL-

BUS

WIDTH

MULTIPLEX-

CONTROL

(HEX)

46 03 24 32 1 NA t1 47 03 24 32 1 NA t3 45 02 16 16 1 NA t5

45 03 16 32 2 NA t6 44 02 15 16 1 NA t8 44 03 15 32 2 NA t9 43 02 16 16 1 NA t11 43 03 16 32 2 NA t12 41 02 12 16 1 NA t14 41 03 12 32 2 NA t15

MODE

Color

NOTES: 9. Data bits per pixel is the number of bits of pixel port information used as color data for each displayed pixel,

SUB-

MODE

24-bit

XGA

TARGA

(6–6–4)

(4–4–4)

often referred to as the number of bit planes.

11. This column is a reference to Tables 2–8 through 2–1 1, where the actual manipulation of pixel information and pixel latching sequences are illustrated for each of the multiplexing modes.

12. It is recommended that all unused input terminals be connected to ground to conserve power.

MULTIPLEX-

CONTROL

(HEX)

MULTI-

PLEX

RATIO

(see

Note 9)

OVERLA Y

BITS

PER

PIXEL

TABLE

REFERENCE

(see

Note 10)

2–17

T able 2–7. Pseudo-Color Mode Pixel-Latching Sequence (see Notes 13 and 14)

v1 s1 s2 s3 s4 s6 s7 s8

VGA7–VGA0

s9 s11 s12 s13 s14 s16 s17 s18

P1–P0 P3–P0 P3–P0 P3–P0 P3–P0 P3–P2 P7–P4 P7–P4 P7–P4 P15–P8 P15–P8 P5–P4 P11–P8 P11–P8 P23–P16

• P15–P12 • P31–P24

• •

P31–P30 P31–P28

NOTES: 13. The latching sequence is initiated by a rising edge on LCLK. For modes in which multiple groups of data

are latched, the LCLK rising edge latches all the groups and the pixel clock shifts them out starting with the low-numbered group. For example, in pseudo-color submode 3 with a 16-bit pixel bus width, the rising edge of LCLK latches all the data groups shown above (s13) and the pixel clock shifts them out in the order P(3–0), P(7–4), P(11–8), and P(15–12). Note that each line in each subtable above represents one pixel.

14. When in the big-endian format (GCR3 =1), the pixel bus is externally swapped by the user (i.e., D31 connected to P0, D0 connected to P31). Since data is always shifted out from low-numbered groups to high-numbered groups, the external swapping of the pixel bus causes the groups to be shifted out in the correct order. However , for modes with more than one bit per pixel, the bits in each data group are reversed (LSB to MSB). This is internally corrected by the TVP3010 input multiplexer. The difference between bigand little-endian data formats and how they affect the pixel bus operation is discussed in more detail in Appendix C.

P0 P0 P0 P0 P1, P0 P1–P0 P1–P0 P1 P1 P1 P1 P3, P2 P3–P2 P3–P2 P2 P2 P2 P2 P5–P4 P5–P4 P3 • • • P7–P6 •

• • • •

P7 P15 P31 P15–P14

P7–P0

P7–P0 P7–P0

2–18

T able 2–8. Direct-Color Mode Pixel-Latching Sequence (Little-Endian) (see Note 15)

d1 d3

P31–P24(O), P23–P16(R), P15–P8(G), P7–P0(B) P31–P24(B), P23–P16(G), P15–P8(R), P7–P0(O)

MSB LSB MSB LSB

d5 d6

P15–P1 1(R), P10–P5(G), P4–P0(B) P15–P11(R), P10–P5(G), P4–P0(B)

MSB LSB MSB LSB

d8 d9

P15(O), P14–P10(R), P9–P5(G), P4–P0(B) P15(O), P14–P10(R), P9–P5(G), P4–P0(B)

MSB LSB MSB LSB

d11 d12

P15–P10(R), P9–P4(G), P3–P0(B) P15–P10(R), P9–P4(G), P3–P0(B)

MSB LSB MSB LSB

d14 d15

P15–P12(R), P11–P8(G), P7–P4(B), P3–P0(O) P15–P12(R), P11–P8(G), P7–P4(B), P3–P0(O)

MSB LSB MSB LSB

NOTE 15: The latching sequence is initiated by a rising edge on LCLK. For modes in which multiple pixel data groups

are latched on one LCLK rising edge, the pixel clock shifts them out starting with the low-numbered pixel data group. Note that each line of each subtable above represents one pixel.

P31–P27(R), P26–P21(G), P20–P16(B)

P31(O), P30–P26(R), P25–P21(G), P20–P16(B)

P31–P26(R), P25–P20(G), P19–P16(B)

P31–P28(R), P27–P24(G), P23–P20(B), P19–P16(O)

2–19

T able 2–9. Direct-Color Mode Pixel-Latching Sequence (Big-Endian) (see Notes 16 and 17)

d1 d3

P31–P24(B), P23–P16(G), P15–P8(R), P7–P0(O) P31–P24(O), P23–P16(R), P15–P8(G), P7–P0(B)

MSB LSB MSB LSB

d5 d6

P15–P1 1(B), P10–P5(G), P4–P0(R) P15 – P11(B), P10 – P5(G), P4 – P0(R)

MSB LSB MSB LSB

d8 d9

P15 – P1 1(B),P10– P6(G),P5 – P1(R),P0(O) P15 – P11(B), P10 – P6(G), P5 – P1(R), P0(O)

MSB LSB MSB LSB

d11 d12

P15 – P12(B), P11– P6(G), P5 – P0(R) P15 – P12(B), P11 – P6(G), P5 – P0(R)

MSB LSB MSB LSB

d14 d15

P15 – P12(O), P11– P8(B), P7 – P4(G), P3 – P0(R) P15– P12(O), P11 – P8(B), P7 – P4(G), P3 – P0(R)

MSB LSB MSB LSB

NOTES: 16. The latching sequence is the same as in the little-endian example. Each line represents one pixel.

17. These subtables assume that the pixel bus is externally reverse-wired for big-endian mode operation (i.e., D31 connected to P0, D0 connected to P31) and that big-endian mode has been selected in the generalcontrol register (GCR3=1). The TVP3010 palette internally corrects the bit ordering (LSB to MSB) for each pixel.

P31 – P27(B), P26 – P21(G), P20 – P16(R)

P31 – P27(B), P26 – P22(G), P21 – P17(R), P16(O)

P31 – P28(B), P27 – P22(G), P21 – P16(R)

P31–P28(O), P27– P24(B), P23 – P20(G),

P19 – P16(R)

2–20

T able 2–10. True-Color Mode Pixel-Latching Sequence (Little-Endian) (see Note 15)

t1 t3

P23 – P16(R), P15 – P8(G), P7 – P0(B) P31 – P24(B), P23 – P16(G), P15 – P8(R)

MSB LSB MSB LSB

t5 t6

P15 – P1 1(R), P10– P5(G), P4 – P0(B) P15 – P11(R), P10 – P5(G), P4 – P0(B)

MSB LSB MSB LSB

t8 t9

P14 – P10(R),P9 – P5(G),P4 – P0(B) P14 – P10(R), P9 – P5(G), P4 – P0(B)

MSB LSB MSB LSB

t11 t12

P15 – P10(R), P9 – P4(G), P3 – P0(B) P15– P10(R), P9 – P4(G), P3 – P0(B)

MSB LSB MSB LSB

t14 t15

P15 – P12(R), P11– P8(G), P7 – P4(B) P15 – P12(R), P11 – P8(G), P7 – P4(B)

MSB LSB MSB LSB

NOTE 15: The latching sequence is initiated by a rising edge on LCLK. For modes in which multiple pixel data groups

are latched on one LCLK rising edge, the pixel clock shifts them out starting with the low-numbered pixel data group. Note that each line in each subtable above represents one pixel.

P31 – P27(R), P26 – P21(G), P20 – P16(B)

P30 – P26(R), P25 – P21(G), P20 – P16(B)

P31 – P26(R), P25 – P20(G), P19 – P16(B)

P31 – P28(R), P27 – P24(G), P23 – P20(B)

2–21

T able 2–11. True-Color Mode Pixel-Latching Sequence (Big-Endian) (see Notes 16 and 17)

t1 t3

P31 – P24(B), P23 – P16(G), P15 – P8(R) P23 – P16(R), P15 – P8(G), P7 – P0(B)

MSB LSB MSB LSB

t5 t6

P15 – P1 1(B), P10– P5(G), P4 – P0(R) P15 – P11(B), P10 – P5(G), P4 – P0(R)

MSB LSB MSB LSB

t8 t9

P15 – P1 1(B),P10– P6(G),P5 – P1(R) P15 – P1 1(B), P10– P6(G), P5 – P1(R)

MSB LSB MSB LSB

t11 t12

P15 – P12(B), P11– P6(G), P5 – P0(R) P15 – P12(B), P11 – P6(G), P5 – P0(R)

MSB LSB MSB LSB

t14 t14

P11– P8(B), P7 – P4(G), P3 – P0(R) P11 – P8(B), P7 – P4(G), P3 – P0(R)

MSB LSB MSB LSB

NOTES: 16. The latching sequence is the same as in the little-endian example. Each line represents one pixel.

17. These subtables assume that the pixel bus is externally reverse wired for big-endian mode operation (i.e., D31 connected to P0, D0 connected to P31) and that big-endian mode has been selected in the generalcontrol register (GCR3=1). The TVP3010 palette internally corrects the bit ordering (LSB to MSB) for each pixel.

P31 – P27(B), P26 – P21(G), P20 – P16(R)

P31 – P27(B), P26 – P22(G), P21 – P17(R)

P31 – P28(B), P27 – P22(G), P21 – P16(R)

P27 – P24(B), P23 – P20(G), P19 – P16(R)

2–22

2.5 On-Chip Cursor

The TVP3010 palette has an on-chip two-color 64 x 64 pixel user-definable cursor. The cursor operation defaults to the XGA standard, but X-Windows compatibility is also available (see Section 2.5.2). In addition to the 64 × 64 sprite cursor, TVP3010 also supports a two-color crosshair cursor . The cursors only operate in noninterlaced applications.

The pattern for the 64 × 64 cursor is provided by the cursor RAM, which may be accessed by the MPU at any time. Cursor positioning is performed via the cursor-position (X and Y) registers and the sprite-origin (X and Y) registers (see register bit definitions in Sections 2.16.4 and 2.16.5). Positions x and y are defined in the palette increasing from left to right and from top to bottom, respectively , as seen on the display screen. The cursor position (x,y) is relative to the first pixel displayed. In other words, the very first pixel displayed is located at position (0,0), and the last pixel displayed for a 1024 × 768 system is located at position (1023,

767). On-chip cursor control is performed by the cursor-control register in the indirect register map (06 hex). Bits

0 and 1 control the width of the crosshair (1, 3, 5, or 7 pixels). Bit 2 enables/disables the crosshair cursor, and bit 3 controls the crosshair-cursor color. Bit 4 specifies either XGA or X-window mode for the sprite cursor. Bit 5 controls the color at the intersection of the sprite and crosshair cursors, and bit 6 enables/disables the sprite cursor. See the cursor-control register bit definitions in Section 2.16.3 for more details.

2.5.1 Cursor RAM

The 64 × 64 × 2 cursor RAM is used to define the pixel pattern within the 64 × 64 pixel cursor window. It is not initialized and may be written to or read by the MPU at any time. The cursor-RAM address zero is at the top left corner of the RAM as shown in Figure 2–6.

The cursor RAM is written to by loading a number into the cursor RAM. Address registers 09 and 08 (hex) of the index register indicate the location of the first group of four cursor pixels to be updated (two bits per pixel implies four pixels per byte). Then the first four pixels are written to the cursor-RAM data register 0A (hex) of the index register. This stores the cursor pixel data in the cursor RAM and automatically increments the cursor-RAM address register. A second write to the cursor-RAM data register then loads the next four cursor pixels, and so on. See the register bit definitions in Sections 2.16.9 and 2.16.10.

To read from the cursor RAM, the address of the first cursor-RAM location to be read is loaded into the cursor-RAM address registers. Then a read is performed on the cursor-RAM data register [0A (hex) of the index register]. Similar to the cursor-RAM write operation, when the read is completed, the cursor-RAM address register is automatically incremented and further reads read successive cursor RAM locations.

The cursor RAM is written and read using the same hardware registers, so any task updating either of these on an interrupt thread must save and restore the cursor-RAM address LSB [Index 08 (hex)] and cursor-RAM address MSB [Index 09 (hex)] registers.

NOTE:

When the cursor-RAM address is to be written, always write both the cursor-RAM address LS and MS registers with the cursor-RAM address LSB register first.

It is recommended that the cursor RAM not be accessed while the sprite cursor is enabled; otherwise, there is a possibility that the cursor RAM could be corrupted. Therefore, the sprite cursor should be temporarily disabled [cursor-control register (CCR) bit 6 = 0] when writing to or reading from the cursor RAM.

The cursor-generation logic requires the use of active low sync inputs. Vertical retrace is determined by detecting multiple syncs in blank. The video front-porch time must be at least one RCLK period. The video

back-porch time must be at least 80 pixel clock periods.

2–23

Upper Left Corner as Displayed on Screen

Pixels

Byte 000 Byte 000 Byte 010 Byte 011

. . . . .

Byte 3F0 Byte 3F1

4 Pixels

D7, D6 D5, D4 D3, D2 D1, D0

. . . . . . . .

Byte 00F Byte 01F

Byte 3FF

Figure 2–6. Cursor-RAM Organization

2.5.2 Two-Color 64 × 64 Cursor

The 64 × 64 × 2 cursor RAM provides two bits of cursor information on every pixel clock (dot clock) cycle during the 64 × 64 cursor window. Cursor-control-register bit 4 specifies whether the XGA mode (default = logic 0) or X-window mode (logic 1) standard is used to interpret the cursor information. The two bits of cursor pixel data determine the cursor appearance as shown in the table below:

RAM COLOR SELECTION

PLANE 1 PLANE 2 XGA MODE X-WINDOW MODE

0 0 Cursor color 0 Transparent 0 1 Cursor color 1 Transparent 1 0 Transparent Cursor color 0 1 1 Complement Cursor color 1

NOTE: Cursor colors 0 and 1: These colors are set by writing to the

cursor color 0 and cursor color 1 registers (index: 23 –28 (hex)). Transparent: The underlying pixel color is displayed. Complement: The ones complement of the underlying pixel color is displayed.

2.5.3 64 × 64 Cursor Positioning

The cursor-position (X and Y) registers are used in conjunction with the sprite-origin (X and Y) registers to position the 64 × 64 cursor on the display screen. The cursor-position (X and Y) registers specify the location of the cursor on the display screen relative to the first displayed pixel out of blank. The sprite-origin (X and Y) register specifies where to origin the 64 × 64 cursor array relative to the cursor position (X and Y). Upon reset, the sprite-origin (X and Y) register automatically defaults to (31, 31). Therefore, the cursor-position (X and Y) registers specify the location on the active display screen of the 31st column and 31st row (counting from top left) of the 64 × 64 cursor array . The crosshair cursor intersects at the center of the sprite cursor area.

The sprite-origin (X and Y) registers can be programmed from (0,0) to (63,63). For example, if the sprite-origin (X and Y) registers were programmed to (0,0), the 64 × 64 cursor array would be located in the lower right quadrant with respect to the cursor position (x,y). Figure 2–7 illustrates this more clearly by showing the 64 × 64 cursor array location relative to the cursor position (x) for different sprite-origin values.

2–24

(0,0)

(31,31)

(63,63)

Figure 2–7. Common Sprite-Origin Settings

NOTE: The programmable sprite-origin feature can be especially useful in creating

crosshair cursors and pointers. See Section 2.5.5 and Figures 2–8 and 2–9 for more details.

2.5.4 Crosshair Cursor

Cursor positioning for the crosshair cursor is also done through the cursor-position (X and Y) register. The intersection of the crosshair cursor is specified by the cursor-position (X and Y) register. If the thickness of the crosshair cursor is greater than one pixel, the center of the intersection is the reference position. The thickness of the crosshair cursor is specified by cursor-control register bits 0 and 1 (see Section 2.16.3). The sprite-origin (X and Y) register has no effect on the crosshair cursor location.

In order to display the crosshair cursor, cursor-control register bit 2 must be enabled while CCR bit 3 is used to set the desired color as shown in the following table:

CCR2 CCR3 CROSSHAIR COLOR

0 0 Crosshair not displayed 0 1 Crosshair not displayed 1 0 Cursor color 0 1 1 Cursor color 1

Cursor-control register bits 0 and 1 specify the crosshair cursor thickness (see Section 2.16.3). The crosshair cursor is limited to being displayed within a window specified by the window-start (X and Y)

and window-stop (X and Y) registers. Since the cursor-position (X and Y) register must specify a point within the window boundaries, it is the responsibility of the user software to ensure that the cursor-position (X and Y) register does not specify a point outside the defined window. Refer to Figure 2–8, which shows the relationship between the different window and cursor register specifying regions.

If a full-screen crosshair cursor is desired, the window-start (X and Y) registers should contain 0000 (hex) and the window-stop (X and Y) registers should be set to the last pixel location on the active screen. For the crosshair cursor to be displayed, the window-start and window-stop registers must contain locations on the active screen. If one wishes to temporarily remove the crosshair cursor from the screen without disabling the function, the window-start registers can be programmed with a location off the active screen.

2–25

The crosshair cursor and the auxiliary window function utilize the same set of window registers. Therefore, care must be taken if the crosshair cursor is to be displayed when the auxiliary window function is enabled (ACR0 = 1). See Section 2.6.

2.5.5 Dual-Cursor Positioning

Both the user-definable 64 × 64 cursor and the crosshair cursor may be enabled for display simultaneously , allowing the generation of custom crosshair cursors. As previously mentioned, the sprite-origin (X and Y) register specifies the 64 × 64 cursor pattern location relative to the cursor position and crosshair cursor.

Figure 2–8 illustrates displaying the dual cursors, showing the relationship between the auxiliary window, the crosshair cursor, and the 64 × 64 cursor for the case where the sprite-origin (X and Y) register is set to (31, 31).

Window Start (x, y) Cursor Position (x, y)

Crosshair Cursor

Crosshair Window

64 × 64 Cursor Area

Window Stop (x, y)

Figure 2–8. Dual-Cursor Positioning

Figure 2–9 shows one possible custom cursor that could be created by setting the sprite-origin register to (0,0) and drawing an arrow in 64 × 64 cursor RAM. The cursor window has been set to full screen by setting the window-start (X and Y) register to 0000 (hex) and the window-stop registers to the last active pixel location. The 64 × 64 cursor area could be located in different locations about the cursor position by programming the sprite-origin (X and Y) registers to different values as described earlier (see Section 2.5.3).

Cursor Position (x, y)

Crosshair Cursor

64 × 64 Cursor Area Sprite Origin = (0, 0)

Crosshair Window = Full Screen

2–26

Figure 2–9. One Possible Custom Cursor Creation

When both the 64 x 64 user-definable cursor and the crosshair cursor are enabled, cursor-control register bit 5 specifies the display at the intersection of the crosshair cursor and the 64 × 64 user-definable cursor. The following cursor intersection truth table details the results of all cursor color combinations; see Section 2.16.3 for specific cursor-control register bit definitions.

CROSSHAIR 64 x 64 CURSOR CCR5 = 0 CCR5 = 1

Color 0 Transparent Color 0 Color 0 Color 1 Transparent Color 1 Color 1 Color 0 Complement Color 0 Color 0 Color 1 Complement Color 1 Color 1 Color 0 Color 0 Color 0 Transparent Color 1 Color 0 Color 1 Transparent Color 0 Color 1 Color 0 Complement Color 1 Color 1 Color 1 Complement

2.6 Auxiliary Window, Port Select, and Color-Key Switching

The TVP3010 palette provides three integrated mechanisms for switching between VGA or overlay images and direct-color images midscreen. The auxiliary-window function supports the display of overlay or VGA graphics into a specified window on the screen when in a direct-color mode. The same window registers used to define the crosshair cursor window are used to define the auxiliary window start and window stop (see Sections 2.16.6 and 2.16.7). One application of this function is to fit a VGA picture in the middle of a direct-color display . The port-select function utilizes an external terminal (PSEL) to switch between VGA or overlay and direct-color on a pixel-by-pixel basis, enabling the generation of multiple VGA or overlay windows on a direct-color screen.

The auxiliary-window and port-select functions are integrated so that they can be enabled simultaneously or separately . They are only operable when in one of the direct-color modes, since both VGA and overlay utilize the palette RAM. Overlay windowing is not supported for those direct-color modes that do not have overlay capability . VGA windowing and VGA port selection are supported for all direct-color modes where the multiplex ratio is 1:1 (see Table 2 – 6). If VGA windowing is to be performed, multiplex-control register 2 must have bit 7 set to a logic 1 (activating the VGA port) and the appropriate direct-color mode must be chosen with the remaining multiplex-control register bits. When the VGA port is activated (MCR2 bit 7 = 1), the overlay is disabled and horizontal zooming is disabled.

The auxiliary-window and port-select functions are controlled by the auxiliary-control register, which is programmed through the indirect register map (29 hex, see Section 2.16.11 for register bit definitions).

Like the crosshair-cursor window, for auxiliary graphics to be displayed, both the window-start and windowstop registers must contain locations on the active screen. If full-screen auxiliary graphics is desired, the window-start (X and Y) registers should contain 0000 (hex) and the window-stop (X and Y) registers should be set to the last active pixel location. The window-start register can be programmed with a location off the active screen to temporarily remove the auxiliary window without disabling the function entirely .

The color-key switching function allows switching between VGA or overlay and direct-color on a pixel-by-pixel basis by comparing the incoming VGA/overlay and direct-color data with user-programmable color-key ranges. The color-key ranges are set by writing to the eight 8-bit color-key range registers: color-key red (low, high), color-key green (low , high), color-key blue (low, high), and color-key OL/VGA (low, high). The color-key switching function is controlled by the color-key control register (see Section 2.6.2) All of the registers can be programmed through the indirect register map (see Sections 2.16.12 and 2.16.13 for register bit definitions). Color-key switching involving overlay is not supported for those direct-color modes that do not have overlay capability. Color-key switching involving VGA can be performed in all direct-color modes where the multiplex ratio is 1:1 (see T able 2 – 6). When the VGA port is activated (MCR2 bit 7 = 1), the OL/VGA register (low, high) color comparison is performed on VGA data and the VGA port is color-key switched instead of overlay.

2–27

The windowing and color-key switching functions are integrated much like a logical OR function. If either

MULTIPLEX MODE SELECTED

of the functions switches to palette graphics (VGA or overlay through the palette RAM), palette graphics are displayed instead of direct color. Therefore, when programming the device for any direct-color mode, both the color-key control and auxiliary-window registers must be set such that direct-color graphics is displayed. For true color (gamma corrected through the palette), one of the functions must be set to palette graphics.

All of the switching functions can be performed using self-clocked or externally clocked frame-buffer interface timing. Externally clocked timing allows all pixel port and VGA port timing to be referenced to CLK0 externally but can only be used for multiplex ratios of 1:1. If externally clocked timing is used, it is recommended that the VGA blank signal also be utilized. See Section 2.3.2 for specific details on clocking. All switching involving the VGA port can only be used with a 1:1 multiplex ratio.

2.6.1 Windowing Control

The TVP3010 palette supports several windowing formats. These are specified by the auxiliary-controlregister bits 0–2 and PSEL as shown below.

Window context switching is determined by the following equation:

switch = [(PSEL × ACR2) + (window × ACR1)] ⊕ ACR0

where:

window = 1 inside the auxiliary window. ACR

is the nth bit of the auxiliary-control register.

The following table then applies:

MULTIPLEX MODE SELECTED

NOTES: 18. The multiplex mode is set by multiplex-control registers 1 and 2. If VGA switching is desired, multiplex-

(see Note 18)

direct color with VGA direct color VGA direct color direct color overlay

control register 2 bit 7 must be set to a logic 1 to enable the VGA port and the desired direct-color mode must be chosen with the remaining MCR bits. For example, if direct-color mode 1 is chosen and multiplexcontrol register 2 is normally set to 1B (hex), it would instead be set to 9B (hex) for VGA switching.

19. The DAC output is undefined if switch = 1 when doing overlay switching in a direct-color mode that does not have overlay capability. If switching between direct color and VGA, any direct-color mode may be chosen as long as the multiplex ratio is 1:1.

20. Auxiliary-control register bits ACR2 and ACR1 can be used to independently enable or disable the port-select and windowing functions as shown in the equation above. If both switching functions are disabled, ACR0 is used to default the display to either direct color or palette graphics. Palette graphics are either VGA or overlay if in a direct-color mode or pseudo-color when in the pseudo-color mode. The reset default is for palette graphics to be displayed as needed for the VGA pass-through mode.

21. All of the switching modes that involve overlay and direct color support the multiple multiplexing ratios or LCLK divide ratios specified in Section 2.4.3 and T able 2–6 for those modes supporting overlay . However , caution must be observed when using the port-select function with the multiplexing modes other than 1:1 since the PSEL signal is latched on LCLK (same as the pixel port).

22. The windowing functions can be performed using self-clocked or externally clocked frame-buffer interface timing (see Section 2.3.2). If VGA switching is involved, CLK0 is the main clock source since VGA port data is latched on the rising edge of this signal. Self-clocked timing can be used by externally connecting RCLK to LCLK; however, this method is limited to a pixel rate of 50 MHz due to the delay from CLK0 to RCLK. Externally clocked timing references all pixel data latching to CLK0 by externally connecting CLK0 to LCLK. In both cases, the internal circuit pipeline delay is adjusted so that the VGA and pixel-port data are synchronous in time.

SWITCH = 0 SWITCH = 1

DISPLAY RESULT

2–28

The use of the auxiliary window to display a VGA window in a direct-color background can be accomplished by setting ACR2 = ACR0 = logic 0 and ACR1 = MCR2 bit 7 = logic 1 and is illustrated in Figure 2–10. The user can also configure the auxiliary window to display direct color in the auxiliary window and VGA everywhere else by setting ACR0 = logic 1 (not shown). Similarly , the auxiliary window can be configured to display overlay in the window or outside of the window by setting MCR2 bit 7 = logic 0 (not shown).

Window Start (x, y)

VGA

Direct Color

Auxiliary Window

Window Stop (x, y)

Figure 2–10. VGA in the Auxiliary Window

The use of PSEL to create multiple VGA windows in a direct-color background can be accomplished by setting ACR0 = ACR1 = logic 0 and ACR2 = logic 1. PSEL is then switched to logic 1 wherever VGA display is desired. This is illustrated in Figure 2–1 1. The user can also configure the port select to switch between overlay and direct color (MCR2 bit 7 = logic 0 not shown) and also invert the fields (ACR0 = logic 1).

PSEL

VGA

Direct Color

VGA

Figure 2–11. Multiple VGA Windows Using Port Select (PSEL)

2.6.2 Color-Key-Switching Control

The TVP3010 palette supports color-key-switching modes in which color data from the direct-color and overlay or VGA ports is compared to a set of user-definable color-key registers. Based on the outcome of the comparison, either direct color, overlay, or VGA are displayed (see Note 23). High and low color-key registers are provided for each color and overlay/VGA so that ranges of colors can be compared as opposed to a single color value. The register bit definitions for the color-key OL/VGA (low, high), color-key red (low , high), color-key green (low, high), and color-key blue (low, high) range registers are shown in Section 2.16.13. The color-key function is controlled by the color-key control register bits 0–4. This register definition is shown in Section 2.16.12.

2–29

Color-key switching is performed according to the following equation:

color key = [(OL + CKC0

) × (R + CKC1) × (G + CKC2) × (B + CKC3)] ⊕ CKC4

where: OL = 1 if color-key OL/VGA low ≤ overlay or VGA (Note 23) ≤ color-key OL/VGA high

R = 1 if color-key red low ≤ direct color (RED) ≤ color-key red high G = 1 if color-key green low ≤ direct color (GREEN) ≤ color-key green high B = 1 if color-key blue low ≤ direct color (BLUE) ≤ color-key blue high

then if color key = 1, overlay or VGA is displayed.

if color key = 0, direct-color is displayed.

NOTES: 23. When the VGA port is activated (MCR2 bit 7 = 1), the OL/VGA register (low,high) color comparison is

performed on VGA data and the VGA port is color-key switched. If the VGA port is not activated (MCR2 bit 7 = 0) the comparison is performed on overlay data and overlay is color-key switched.

24. Color-key switching is supported for all direct-color multiplexing modes that have overlay capability when doing overlay switching. When doing VGA switching, all direct-color modes are supported as long as the multiplex ratio is 1:1. The direct-color multiplex mode is set in multiplex-control registers 1 and 2.

25. CKC0–CKC3 can be used to individually enable or disable certain colors in the comparison for maximum flexibility . If color-key switching is not desired, CKC0–CKC3 should be set to logic 0. CKC4 is then used to set the default for either direct color or palette graphics. The default condition at reset is CKC0 = CKC1 = CKC2 = CKC3 = logic 0 and CKC4 = logic 1. This causes the function to default to palette graphics as required for VGA pass-through node.

26. The color-key comparison for the overlay and VGA data is performed after the read-mask and palette-page registers so that an 8-bit comparison can be performed. This also gives the maximum flexibility to the user in performing the color comparisons. If the overlay defined for a given mode is less than 8 bits per pixel, the data is shifted to the LSB locations and the palette-page register fills the remaining MSB positions.

27. For those direct-color modes that have less than 8 bits per pixel of red, green, and blue direct-color data, the data is internally shifted to the MSB positions for each color and the remaining LSB bits are filled with logic 0s before the 8-bit comparisons are performed.

28. The windowing and color-key functions are integrated such that if either switch = 1 (windowing case, see Section 2.6.1) or color-key = 1, palette graphics are displayed (overlay or VGA depending on multiplexcontrol register 2 bit 7) instead of direct-color data. Both functions must be correctly set for proper operation.

2.7 Overscan

The TVP3010 palette provides the capability to produce a custom screen border using the overscan function. The overscan function is controlled by general-control-register (GCR) bits 6 and 7. GCR bit 6 is used to enable overscan, and GCR bit 7 specifies whether the overscan area is defined by the 8/6 terminal or by internal circuitry . The overscan color is user programmable by writing to the overscan color red, green, and blue registers in the indirect register map. For the 8/6

[OVS] terminal to be used to control overscan, it needs to be configured as the OVS input by setting configuration register bit 1 (CR1) to logic 1. When OVS is configured the 8/6

[OVS] function is controlled by configuration register bit 0 (CR0),

which defaults to a 6-bit operation. If the overscan function is enabled (GCR6 = logic 1) and the 8/6

[OVS] terminal is used to control the area of overscan (GCR7 = logic 0), then overscan color is displayed any time that OVS is high and blank (active). Note that blank

is the internal blank signal and can either be generated from VGABL or SYSBL depending on the mode selected. If the TVP3010 internal circuitry is chosen to generate overscan (GCR7 = logic 1), then internal vertical and horizontal sync and blank are used to define the overscan display area. Whenever blank is active and vertical and horizontal sync are inactive, overscan is displayed. Internally generated timing may not work with some CRT monitors.

If overscan is enabled, then the blanking pedestal is imposed on the analog outputs when OVS is high and

is low. If overscan is disabled, then the blanking pedestal occurs when blank is low . Blank can be either

blank SYSBL or VGABL depending on the state of multiplex-control register 2 bit 7.

[OVS]

†

is low

†

The blank and blank

2–30

references are internal signals.

If VGA is disabled, OVS is sampled on the falling edge of VCLK and then resampled on the rising edge of RCLK before being passed to the RCLK and dot clock pipeline delay. If VGA is enabled, then OVS is sampled on the rising edge of CLK0 and passed to dot clock pipeline delay. In this way, the video timing relationship is maintained since the same method and pipeline delay are applied to the SYSBL

and VGABL

signals. Figure 2–12 demonstrates the use of OVS to produce a custom overscan screen border.

OVS

Blank

Display Area

Overscan Border

Figure 2–12. Overscan

2.8 Horizontal Zooming

The TVP3010 palette supports a user-programmable horizontal 2-, 4-, 8-, 16-, or 32-x zooming function. Zooming can be controlled through the auxiliary-control register on the indirect-register map as shown by the following table. Note that the RCLK/SCLK divide ratio also has to be modified in the output-clock selection register.

ACR7 ACR6 ACR5 HORIZONTAL ZOOM

0 0 0 1x 0 0 1 2x 0 1 0 4x 0 1 1 8x 1 0 0 16x 1 0 1 32x

When one of the horizontal zooms (besides 1×) is chosen, the internal pixel data multiplexer is configured such that it replicates the pixel data on successive dot clocks by the number of times specified by ACR(5–7). Also, modify the RCLK/SCLK divide ratio in the output clock selection register to facilitate the pixel replication. The new RCLK divide ratio should be chosen as the old RCLK divide ratio multiplied by the zoom factor. It is recommended that the zoom only be changed during vertical retrace.

The horizontal zoom function applies only to the pixel port P(0–31). If the VGA port is enabled (MCR2 bit 7 = 1), the horizontal zoom function is disabled.

2–31

2.9 Test Functions

The TVP3010 palette provides several functions that enable system testing and verification. These are detailed below.

2.9.1 16-Bit CRC

A 16-bit cyclic redundancy check (CRC) is provided so that video data integrity can be verified at the input to the DACs. The CRC is updated on the second horizontal sync rising edge during vertical retrace and is only calculated on the active screen area; i.e., active blank stops the calculation. The CRC can be performed on any of the 24 data lines that enter the DACs and is controlled by the CRC-control register (CRCC bits 0–4). V alues from 0 to 23 may be written to this register to select between the 24 different DAC data inputs. V alue 0 corresponds to DAC data red 0 (LSB), value 7 to red 7 (MSB), value 8 to green 0 (LSB), value 15 to green 7 (MSB), value 16 to blue 0 (LSB), and value 23 to blue 7 (MSB). The 16-bit remainder that is calculated on the individual DAC data line can be read from the CRCLSB and CRCMSB registers. See Table 2–2 for the indirect register map address. See Sections 2.16.15 and 2.16.16 for the CRC register bit definitions.

As long as the display pattern for each screen remains fixed, the CRC result should remain constant. If the CRC result changes, an error condition should be assumed. Since the CRC is calculated using the common CRC–16 polynomial (X screen in software and compare this to the TVP3010-calculated CRC remainder to verify data integrity .

2.9.2 Sense Comparator Output and Test Register

The TVP3010 provides a SENSE output to support system diagnostics. The MUXOUT [SENSE] terminal can be configured as the SENSE output by programming bit 3 of the configuration register to logic 1. SENSE can be used to determine the presence of the CRT monitor or verify that the RGB termination is correct. SENSE The internal 350-mV reference has a tolerance of ±50 mV when using an external 1.235-V reference. If the internal voltage reference is used, the tolerance is higher.

is a logic L if one or more of the DAC outputs exceeds the internal comparator voltage of 350 mV .

+ X15 + X2 + 1), the user can calculate and store the CRC remainder for a test

The sense comparators are also integrated with the sense-test register so that the comparison results for the red, green, and blue comparators can be read independently through the 8-bit microinterface. When the sense-test register (STR) is read, the results are indicated in the bit positions as shown below.

STR BITS D7 D6 D5 D4 D3 D2 D1 D0

Data 0 0 0 0 0 R G B

where: R = logic 1 if IOR > 350 mV D6–D3 are reserved

G = logic 1 if IOG > 350 mV D7 is disable (logic 1) bit B = logic 1 if IOB > 350 mV

NOTES: A. D7 can be set to a logic 1 to disable the sense comparison function. At reset, the sense comparison is

2–32

enabled (D7 = logic 0). D6 –D3 are reserved. If the sense-test register is written to disable the sense comparator function, bits D6–D0 need to be set to a logic 0.

B. Both the SENSE

blank signal (SYSBL comparators, the frame-buffer inputs should be set up such that data entering the DACs remains unchanged for a sufficient period of time prior to and after the blank-signal falling edge.

output and the sense-test register are latched by the falling edge of the internally sampled

or VGABL depending on mode). In order to have stable voltage inputs to the

2.9.3 Identification Code

An ID register with a hardwired code is provided that can be used as a software verification for different versions of the system design. The ID code in the TVP3010 palette is static and may be read without consideration to the dot clock or video signals. The ID code is read through the indirect register map (see Table 2–2). The value defined for the palette is 10 (hex).

2.10 MUXOUT [SENSE]Output

The MUXOUT [SENSE] terminal can be configured as MUXOUT or SENSE by programming bit 3 of the configuration register (see Section 2.16.1). When the terminal is configured as MUXOUT control external devices. MUXOUT configuration bit 2 through the TVP3010 microinterface. Its typical application is to control an external multiplexer, selecting between the VGA pass-through and normal mode horizontal and vertical sync signals supplied on the HSYNC mode is selected. At any other time, it can be programmed to the desired polarity via the configuration register. The reset default is MUXOUT

and VSYNC inputs. This output is driven low at reset or when the VGA pass-through

is a TTL-compatible output that is software programmable by writing

. See Section 2.9.2 for the detailed description of SENSE.

, it can be used to

2.11 Reset

There are two ways to reset the TVP3010 palette:

• Power-on reset

• Software reset

The default register settings are detailed in Tables 2–1 and 2–2.

2.11.1 Power-On Reset

There is a power-on reset (POR) circuit built into the 32-bit TVP3010. This POR operates at power on only . Even though this circuitry is provided, it is still recommended to utilize the software reset function as described in Section 2.1 1.2 after the power supply has stabilized to ensure the reset condition. All registers reset to VGA default settings.

2.11.2 Software Reset

When data is written to the reset register [FF (hex) on the indirect register map], all other registers are initialized to VGA default settings accordingly . Any data may be written into the reset register to cause this reset to occur.

2.12 Frame-Buffer Interface

The TVP3010 provides three output clock signals and one input clock signal for controlling the frame-buffer interface: SCLK, RCLK, LCLK, and VCLK. SCLK can be used to clock out data from VRAM shift registers directly. Split shift-register-transfer function is also supported. RCLK is provided so that pixel-port [P(0–31)] data loading can be synchronized to the VRAM. LCLK rising edges latch data presented on the pixel port, and VCLK is used to clock and synchronize the video control signals such as HSYNC Clocking of the frame-buffer interface (self-clocked and externally-clocked timing) is discussed in detail in Section 2.3.2.

The 32-terminal interface allows many operational display modes as defined in Section 2.4 and T able 2–6. The pixel latching sequence is initiated by a rising edge on LCLK. For those multiplexed modes in which multiple pixels are latched on one LCLK rising edge, the pixel clock shifts the pixels out starting with the pixels that reside on the low-numbered pixel-port terminals. For example, in an 8-bit-per-pixel pseudo-color mode with an 8:1 multiplex ratio, the pixel display sequence is P(0–7), P(8–15), P(16–23), and P(24–31).

The TVP3010 frame-buffer interface also supports little- and big-endian data formats on the pixel bus. This can be controlled by general-control register bit 3. See Sections 2.4.1 and 2.16.2, and Appendix C for details of operation.

, VSYNC, SYSBL.

2–33

2.13 Analog Output Specifications

PEDESTAL

The DAC outputs are controlled by three current sources (only two for IOR and IOB) as shown in Figure 2–13. The default condition is to have 0-IRE difference between blank and black levels, which is shown in Figure 2–15. If a 7.5-IRE pedestal is desired, it can be selected by setting bit 4 of the general-control register. This video output is shown in Figure 2–14.

IOG

SYNC

(IOG Only)

≈ 15 pF

Blank G0 – G7

C (stray+load)

Figure 2–13. Equivalent Circuit of the Current Output (IOG)

A resistor (R

) is needed between the FS ADJUST terminal and GND to control the magnitude of the

SET

full-scale video signal. The IRE relationships in Figures 2–14 and 2–15 are maintained regardless of the full-scale output current.

The relationship between R

(Ω) = K1 × V

SET

The full-scale output current on IOR and IOB for a given R

IOR, IOB (mA) = K2 × V

and the full scale output current IOG is:

SET

(V)/IOG (mA)

ref

SET

ref

(V)/R

SET

(Ω)

is:

where K1 and K2 are defined as:

IOG IOR, IOB

8-BIT OUTPUT 6-BIT OUTPUT 8-BIT OUTPUT 6-BIT OUTPUT

7.5 IRE K1 = 11,294 K1 = 11,206 K2 = 8,067 K2 = 7,979 0 IRE K1 = 10,684 K1 =10,600 K2 = 7,462 K2 = 7,374

2–34

White

Black

Blank

Sync

White

Green [mA]

26.67

92.5 IRE

7.5 IRE

40 IRE

9.05

7.62

0.00

Figure 2–14. Composite Video Output (With 7.5 IRE, 8-Bit Output)

Green Red/Blue

[mA]

25.24

[V]

1.000

0.340

0.286

0.000

[V]

0.950

Red/Blue

[mA]

19.05

1.44

0.00

[mA]

17.62

[V]

0.714

0.054

0.000

[V]

0.660

100 IRE

Black/

Blank

40 IRE

Sync

Figure 2–15. Composite Video Output (With 0 IRE, 8-Bit Output)

NOTE: 75-Ω doubly terminated load, V

levels.

= 1.235 V , R

ref

7.62

0.286

0.00

0.000

= 523 Ω. RS343A-levels and tolerances are assumed on all

SET

0.000

2–35

2.14 Video Control: Horizontal Sync, Vertical Sync, and Blank

For the high-resolution system modes, HSYNC and VSYNC are active-low pulses that are passed through true/complement gates to the HSYNCOUT and VSYNCOUT outputs. The output polarities of HSYNCOUT and VSYNCOUT can be programmed through the general-control register. However , for the VGA mode, the polarities required by the monitor are already provided at the feature connector where HSYNC

and VSYNC are sourced. Therefore, the palette passes them through to HSYNCOUT and VSYNCOUT without polarity change. As described in Section 2.3 and Figures 2–2 through 2–5, the SYSBL are sampled and latched at the falling edge of VCLK in the system modes while VGABL VSYNC

are latched at the rising edge of CLK0 in the VGA mode. After SYSBL is sampled with VCLK, it is

, HSYNC and VSYNC inputs

, HSYNC, and

sampled on the rising edge of the internal RCLK and passed to the dot clock pipeline delay. When multiplex-control register 2 bit 7 is set to logic 1 to activate the VGA port, the CLK0 and VGABL selected. Otherwise, VCLK is used to latch HSYNC

HSYNC

, VSYNC, and blank (generated either from the system mode or VGA-mode video control signals)

, VSYNC, and SYSBL is selected.

inputs are

have internal pipeline delays so that the sync and blank signals align with the RGB data at the DAC outputs. Due to the sample and latch timing delay , it is possible to have active SCLKs after the selected blank input becomes active. The relationship between VCLK and SCLK and the internal VCLK sample and latch delay needs to be carefully reviewed and programmed. See Section 2.3 and Figures 2–2 and 2–3 for more details.

As shown in Figure 2–13, active HSYNC They are not qualified by the internal blank

and VSYNC turns off the sync current source (after pipeline delay).

signal. Therefore, to ensure proper operation, HSYNC and

VSYNC should be designed such that they are active only during the blank active time. To alter the polarity of the HSYNCOUT and VSYNCOUT outputs, the MPU must set or clear the

corresponding bits in general-control register (see Section 2.16.2). The polarity of these signals can only be altered when not in VGA mode. These bits default to logic 0, which is an active-low output.

2.15 Split Shift-Register-Transfer VRAMs

The TVP3010 palette has direct support for split shift-register-transfer (SSRT) VRAMs. In order to allow the VRAMs to perform a split shift-register transfer, an extra SCLK cycle must be inserted during the blank sequence. This is initiated when the SSRT enable bit (bit 2) in the general-control register is set to logic 1 and a rising edge on the SFLAG input is detected. An SCLK pulse is generated within 20 ns of the rising edge of the SFLAG signal. A minimum 15-ns logic-high duration is provided to satisfy all the –15 VRAM timing requirements. The rising edge of the SFLAG input triggers SCLK, but it needs to stay high for a specified minimum duration. By controlling the SFLAG timing, the delay time from the rising edge of VRAM

signal to SCLK can be satisfied. The relationship between SCLK, the SFLAG input, and SYSBL is

TRG shown as follows:

SYSBL

SSRT Enable

(general-control

SFLAG Input

SCLK

Figure 2–16. Split Shift-Register-Transfer Timing

If external SFLAG logic is designed as an R–S latch that is set by split shift-register-transfer timing and reset by SYSBL

going high, the delay from SYSBL high to SFLAG low cannot exceed one half of one SCLK cycle.

Otherwise, the SCLK generation logic could fail.

2–36

If the SSRT function is enabled but SFLAG is held low , the SCLK runs as if the SSRT function is disabled.

CR7XR

CR6

VCLK polarity select specifies whether the VCLK signal is in phase or opposite

CR5

internally connected to RCLK. If bit 5 logic 1, then CLK4[LCLK] is configured CR4

RCLK enable specifies whether RCLK is output on CLK3[RCLK]. If disabled, CR3

MUXOUT or SENSE selects MUXOUT or SENSE on MUXOUT[SENSE]. See

CR2

MUXOUT level terminal. If configuration register bit CR3 = logic 0, then this

CR1

8/6 function signal. If CR1 0, then 8/6[OVS] is configured as the 8/6 terminal. CR0

8/6 level. When CR1 = logic 1, this bit controls the 8/6 operation. See

Since the SFLAG input is not qualified by the blank signal within the palette, it needs to be held low or disabled any time the SSRT SCLK pulse is not intended. Refer to Section 2.3 and Figures 2–2 through 2–5 for more system details.

2.16 Control-Register Definitions

2.16.1 Configuration Register

The configuration register is used to control the dual function pins on the TVP3010 so that it can maintain pin compatibility with the TLC3407x VIP parts. At reset, the configuration register defaults to TLC3407x compatible pin settings. Bit 7 of the configuration register corresponds to data bus bit 7, index = 1E (hex).

T able 2–12. Configuration Register

BIT

NAME

0: In phase (default) 1: Opposite phase

0: Internal RCLK (default)

1: CLK4[LCLK] 0: Disabled (default)

1: Enabled 0: MUXOUT (default) 1: SENSE 0: Low (default) 1: High

0: 8/6 (default)

1: OVS 0: 6-bit (default)

1: 8-bit (high)

VALUES DESCRIPTION

eserved, undefine

VCLK polarity select specifies whether the VCLK signal is in phase or opposite phase of the RCLK and SCLK signals.

LCLK source selects the LCLK source. If bit 5 = logic 0, (default) then LCLK is internally connected to RCLK. If bit 5 = logic 1, then CLK4 as the LCLK input and an external LCLK source must be supplied. See Section 2.3.1.

RCLK enable specifies whether RCLK is output on CLK3[RCLK]. If disabled, then CLK3[RCLK] is CLK3. See Section 2.3.

MUXOUT or SENSE selects MUXOUT or SENSE on MUXOUT[SENSE]. See Sections 2.9 and 2.10.

MUXOUT level terminal. If configuration register bit CR3 = logic 0, then this terminal controls the logic level on MUXOUT.

8/6 or OVS defines the terminal as 8/6 or OVS and controls the source of the 8/6

function signal. If CR1 = 0, then 8/6[OVS] is configured as the 8/6 terminal. If CR1 = 1, then CR0 controls the 8/6 function and is configured as OVS. See Sections 2.1 and 2.7.

8/6 level. When CR1 = logic 1, this bit controls the 8/6 operation. See Section 2.1.

[LCLK] is configured

2–37

2.16.2 General-Control Register

GCR7 GCR6

Overscan enable. Specifies whether to enable the user defined overscan GCR5

Sync enable. This bit specifies whether SYNC information is to be output onto

GCR4

IRE

ifi

GCR3

Little endian/big endian select. Selects either little or big endian format for the GCR2

Split shift

GCR1

VSYNCOUT

GCR0

HSYNCOUT

The general-control register is used to control various functions of the TVP3010 palette. It can be accessed by the MPU at any time. Bit 7 of the general-control register corresponds to data bus bit 7, index = 1D (hex).

T able 2–13. General-Control Register

BIT

NAME

GCR7

0: External OVS terminal (default)

1: Internal 0: Disable (default) 1: Enable 0: Disable 1: Enable (default)

0: 0 IRE (default) 1: 7.5 IRE

0: Little-endian (default) 1: Big-endian 0: Disable (default) 1: Enable 0: Active (low) (default) 1: Active (high) 0: Active (low) (default) 1: Active (high)

VALUES DESCRIPTION

Overscan-control select. Selects external terminal control or internally generated overscan control. See Section 2.7.

Overscan enable. Specifies whether to enable the user-defined overscan screen borders.

Sync enable. This bit specifies whether SYNC information is to be output onto IOG.

Pedestal control. This bit specifies whether a 0 or 7.5 IRE blanking pedestal

s to be generated on the video outputs. 0

levels are the same. Little-endian/big-endian select. Selects either little- or big-endian format for the

pixel-bus frame-buffer interface. See Sections 2.4 and Appendix C.

-register-transfer enable. See Section 2.15.

output polarity. See Section 2.14.

spec

es that the black and blan

2–38

2.16.3 Cursor-Control Register

CCR6

p(g)(g)

CCR5

CCR4

X-wind

CCR3

CCR2

CCR1, CCR0

thick

centered about the value in the cursor position (x,y) register

The cursor-control register is used to control various on-chip cursor functions of the palette. It may be accessed by the MPU at any time. Bit 7 of the cursor-control register corresponds to data bus bit 7, index = 06 (hex).

T able 2–14. Cursor-Control Register

BIT NAME VALUES DESCRIPTION

CCR7 X Reserved

0: Disable (default) 1: Enable

0: (default) 1: 0: XGA (default) 1: X-windows

0: Color 0 (default) 1: Color 1 0: Disable (default) 1: Enable 00: 1 pixel (default) 01: 3 pixels 10: 5 pixels 11: 7 pixels

Sprite-cursor enable. This bit enables (logic 1) or disables (logic 0) the 64 × 64 sprite cursor.

Dual-cursor format. This bit specifies the display format at the intersection of

e crosshair cursor and the user-defined cursor area. See Section 2.5.5 an

the cursor intersection truth table. 64 × 64 cursor-mode select. This bit specifies whether the XGA (logic 0) or

ows format is used to interpret the data stored in the 64 ×64 cursor sprite

RAM. See Section 2.5.2. Crosshair color selection. This bit specifies whether the crosshair cursor is to

be displayed in color 1 (logical 1) or color 0 (logical 0). Crosshair cursor enable. This bit specifies whether the crosshair cursor is to

be displayed (logical 1) or not (logical 0).

Crosshair thickness. These bits specify whether the vertical and horizontal

ness of the crosshair is one, three, five, or seven pixels. The segments are

centered about the value in the cursor-position (x,y) register.

2–39

2.16.4 Cursor-Position X and Y Registers

These registers are used to specify the (x,y) coordinate of the intersection of the crosshair cursor. They are also used in conjunction with the sprite-origin register to specify the location of the 64 x 64 cursor area (see Section 2.5.3). The cursor-position X register is made up of the cursor-position X LSB (CPXL) and the cursor-position X MSB (CPXM); the cursor-position Y register is made up of the cursor-position Y LSB (CPYL) and the cursor-position Y MSB (CPYM). All registers are initialized to 00 (hex) and can be written to or read from by the MPU at any time. The cursor position is not updated until the vertical retrace interval after CPYM has been written to by the MPU.

CPXL and CPXM are cascaded to form a 12-bit cursor-position X register. Similarly, CPYL and CPYM are cascaded to form a 12-bit cursor-position Y register. Bits D4–D7 of CPXM and CPYM are always a logic zero.

CURSOR-POSITION X MSB CURSOR-POSITION X LSB

(CPXM) (CPXL)

Data Bit D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 X Position 0 0 0 0 X11 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0

Index = 01h Index = 00h

CURSOR-POSITION Y MSB CURSOR-POSITION Y LSB

(CPYM) (CPYL)

Data Bit D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Y Position 0 0 0 0 Y11 Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

Index = 03h Index = 02h

The cursor-position x value to be written is calculated as follows:

Cx = desired display screen x position V alues from 0000 (hex) to 0fff (hex) may be written into the cursor-position X register. The cursor-position Y value to be written is calculated as follows:

Cy = desired display screen y position V alues from 0000 (hex) to 0fff (hex) may be written into the cursor-position Y register. The values written into the cursor-position X and Y registers should be relative to the first displayed pixel

on the screen; i.e., (0,0).

2–40

2.16.5 Sprite-Origin X and Y Registers

These registers are used to specify the (x,y) location of the 64 x 64 sprite with respect to the crosshair location (see Section 2.5.3). The sprite-origin X and Y registers can contain values from 0 to 63 decimal. Both registers are initialized to 1F (hex), 31 (decimal), which sets the center of the crosshair at the center of the 64 × 64 sprite. Both registers may be written to or read from by the MPU at any time. The sprite origin is not updated until the vertical retrace interval after sprite-origin X and Y registers have been written by the MPU.

SPRITE-ORIGIN X

Data Bit D7 D6 D5 D4 D3 D2 D1 D0 X Origin 0 0 X5 X4 X3 X2 X1 X0

Index = 04h

SPRITE-ORIGIN Y

Data Bit D7 D6 D5 D4 D3 D2 D1 D0 Y Origin 0 0 Y5 Y4 Y3 Y2 Y1 Y0

Index = 05h

V alues from 00 (hex) to 3F (hex) may be written into the sprite-origin X and Y registers. Bits D6 and D7 are always 0.

2–41

2.16.6 Window-Start X and Y Registers

These registers are used to specify the (x,y) coordinate of the upper-left corner of the crosshair-cursor window or auxiliary window. The window-start X register is made up of the window-start X LSB (WSXL) and the window-start X MSB (WSXM); the window-start Y register is made up of the window-start Y LSB (WSYL) and the window-start Y MSB (WSYM). They are not initialized and may be written to or read from by the MPU at any time. The window start is not updated until the vertical retrace interval after WSYM has been written to by the MPU.

WSXL and WSXM are cascaded to form a 12-bit window-start X register. Similarly, WSYL and WSYM are cascaded to form a 12-bit window-start Y register. Bits D4–D7 of WSXM and WSYM are always a logical zero.

WINDOW START X MSB WINDOW START X LSB

(WSXM) (WSXL)

Data Bit D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 X Coordinate 0 0 0 0 X1 1 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0

Index = 11h Index = 10h

WINDOW START Y MSB WINDOW START Y LSB

(WSYM) (WSYL)

Data Bit D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Y Coordinate 0 0 0 0 Y1 1 Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

Index = 15h Index = 14h

The window-start x value to be written is calculated as follows:

Wx = desired display screen x position V alues from 0000 (hex) to 0fff (hex) may be written into the window-start X register. The window-start Y value to be written is calculated as follows:

Wy = desired display screen y position V alues from 0000 (hex) to 0fff (hex) may be written into the window-start Y register. The values written into the window-start X and Y registers should be relative to the first displayed pixel on

the screen; i.e., (0,0). The window-start location specified is the first location inside the window. For the crosshair cursor or

auxiliary window to be displayed, the window-start registers must specify a point on the active display .

2–42

2.16.7 Window-Stop X and Y Registers

These registers are used to specify the (x,y) coordinate of the lower-right corner of the crosshair cursor or auxiliary window. The window-stop X register is made up of the window-stop X LSB (WSPXL) and the window-stop X MSB (WSPXM); the window-stop Y register is made up of the window-stop Y LSB (WSPYL) and the window-stop Y MSB (WSPYM). They are not initialized and may be written to or read from by the MPU at any time. The window stop is not updated until the vertical retrace interval after WSPYM has been written to by the MPU.

WSPXL and WSPXM registers are cascaded to form a 12-bit window-stop X register. Similarly , WSPYL and WSPYM registers are cascaded to form a 12-bit window-stop Y register. Bits D4 – D7 of WSPXM and WSPYM are always a logical zero.

WINDOW STOP X MSB WINDOW STOP X LSB

(WSPXM) (WSPXL)

Data Bit D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 X Coordinate 0 0 0 0 X1 1 X10 X9 X8 X7 X6 X5 X4 X3 X2 X1 X0

Index = 13h Index = 12h

WINDOW STOP Y MSB WINDOW STOP Y LSB

(WSPYM) (WSPYL)

Data Bit D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Y Coordinate 0 0 0 0 Y1 1 Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

Index = 17h Index = 16h

The window-stop x value to be written is calculated as follows:

Wx = desired display screen x position V alues from 0000 (hex) to 0fff (hex) may be written into the window-stop X register. The window-stop y value to be written is calculated as follows:

Wy = desired display screen y position V alues from 0000 (hex) to 0fff (hex) may be written into the window-stop Y register. The values written into the window-stop X and Y registers should be relative to the first displayed pixel on

the screen; i.e., (0,0). The window-stop location specified is the last location inside the window. For the crosshair cursor or

auxiliary window to be displayed, the window-start registers must specify a point on the active display .

2–43

2.16.8 Cursor-Color 0, 1 RGB Registers

These registers are used to specify the two colors for the hardware cursor (see Section 2.5). They are not initialized and may be written to or read from by the MPU at any time. Note that there are six registers total, three for each color. The register format for both the cursor-color 0 and cursor-color 1 registers is shown below.

CURSOR-COLOR RED

Data Bit D7 D6 D5 D4 D3 D2 D1 D0 Red Value R7 R6 R5 R4 R3 R2 R1 R0

Index = 23h and 26h

CURSOR-COLOR GREEN

Data Bit D7 D6 D5 D4 D3 D2 D1 D0 Green Value G7 G6 G5 G4 G3 G2 G1 G0

Index = 24h and 27h

CURSOR-COLOR BLUE

Data Bit D7 D6 D5 D4 D3 D2 D1 D0 Blue Value B7 B6 B5 B4 B3 B2 B1 B0

Index = 25h and 28h

V alues 00 (hex) to FF (hex) may be written into the cursor-color registers.

2–44

2.16.9 Cursor-RAM Address Register

These registers are used to specify the address of where to write or read sprite cursor data from. The linear addressing scheme is depicted in Figure 2–6 of Section 2.5.1. The cursor-RAM register is made up of the cursor-RAM address LSB (CRAL) and the cursor-RAM address MSB (CRAM). They are not initialized and may be written to by the MPU at any time.

CRAL and CRAM are cascaded to form a 10-bit cursor-RAM address register. Bits D2–D7 of CRAM are always a logical zero.

CURSOR-RAM ADDRESS MSB CURSOR-RAM ADDRESS LSB

(CRAM) (CRAL)

Data Bit D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Address 0 0 0 0 0 0 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Index = 09h Index = 08h

Values from 0000 (hex) to 03FF (hex) may be written into the cursor-RAM address register. When the cursor-RAM address is to be written, both registers must be written with the cursor-RAM address LSB being the first.

2.16.10 Cursor-RAM Data Register

This register is used to read and write the contents of the sprite cursor locations whose address is specified in the cursor-RAM address registers. The data read from or written to this register contain four pixels of information and two bit planes per cursor pixel (see Figure 2 – 6 and Section 2.5.1). The register is not initialized and may be written to or read from by the MPU at any time. The sprite-cursor data format is shown below.

CURSOR-RAM DATA

Data Bit D7 D6 D5 D4 D3 D2 D1 D0 Data P1

Index = 0Ah

V alues from 00 (hex) to FF (hex) may be written into the cursor-RAM data register.

2–45

2.16.11 Auxiliary-Control Register

ACR7

Hori

ACR6

Hori

ACR5

Hori

ACR3

Frame buffer clocking select. Used to select self or externally clocked ACR2

Windowing function select. This is a port select enable. See equation ACR1

Windowing function select. This is an auxiliary window enable. See the

ACR0

gpy

CKC4

Color key function select. This is a complementary function bit. See the

CKC3

field

CKC2

CKC1

field

yp q

The auxiliary-control register is used to control various functions of the TVP3010 palette including the auxiliary-windowing function and horizontal zooming. It can be accessed by the MPU at any time. Bit 7 of the auxiliary-control register corresponds to data bus bit 7, index = 29 (hex).

BIT NAME VALUES DESCRIPTION

0: (default) 1: 0: (default) 1: 0: (default) 1:

ACR4 X Reserved

0: Externally clocked 1: Self clocked (default) 0: PSEL disable (default) 1: PSEL enable 0: Window disable (default) 1: Window enable 0: True function 1: Complement (default)

zontal zoom control. See Section 2.8.

Frame-buffer clocking select. Used to select self- or externally-clocked timing for the pixel port (P0–P63). See Section 2.3.2.

Windowing-function select. This is a port-select enable. See equation in Section 2.6.1.

Windowing-function select. This is an auxiliary-window enable. See the equation in Section 2.6.1.

Windowing-function select. This is a complementary function bit. See the equation in Section 2.6.1.

2.16.12 Color-Key-Control Register

The color-key-control register is used to control the operation of the color-key-switching function (see Section 2.6.2). It can be accessed by the MPU at any time. Bit 7 of the color-key-control register corresponds to data bus bit 7, index = 38 (hex).

BIT NAME VALUES DESCRIPTION

CKC7 X Reserved CKC6 X Reserved CKC5 X Reserved

CKC3

CKC2

CKC1

CKC0

2–46

0: True function 1: Complement (default) 0: Disable compare

(default) 1: Enable comparison 0: Disable compare

(default) 1: Enable comparison

Color-key-function select. This is a complementary function bit. See the equation in Section 2.6.2.

Blue-compare enable. This is used to enable or disable the direct-color blue

comparison. See the equation in Section 2.6.2.

Green-compare enable. This is used to enable or disable the direct-color green field comparison. See the equation in Section 2.6.2.

Red-compare enable. This is used to enable or disable the direct-color red

comparison. See the equation in Section 2.6.2.

Overlay/VGA-compare enable. This is used to enable or disable the direct-color overlay/VGA field comparison. See the equation in Section 2.6.2.

2.16.13 Color-Key (Red, Green, Blue, Overlay) Low and High Registers

These registers are used to specify the color comparison ranges for the four direct-color data fields when performing color-key switching. A low and a high register are provided for each of the four data fields to facilitate the range comparison. See Sections 2.6 and 2.6.2 for more details on their usage. All four low registers are initialized with 01 (hex), while all four high registers are initialized with FF (hex). The registers may be written to or read from by the MPU at any time. There are eight registers total, two for each color. The register formats for both low and high registers are shown below.

COLOR-KEY LOW

Data Bit D7 D6 D5 D4 D3 D2 D1 D0 Low Value L7 L6 L5 L4 L3 L2 L1 L0

Index = 30h, 32h, 34h, and 36h

COLOR-KEY HIGH

Data Bit D7 D6 D5 D4 D3 D2 D1 D0 High Value H7 H6 H5 H4 H3 H2 H1 H0

Index = 31h, 33h, 35h, and 37h

V alues 00 (hex) to FF (hex) may be written into the four color-key-low and four color-key-high registers.

2–47

2.16.14 Overscan-Color RGB Registers

These registers are used to specify the color for the overscan function. This function can be used to create custom screen borders (see Section 2.7). They are not initialized and may be written to or read from by the MPU at any time. The register formats for the overscan-color registers are shown below.

OVERSCAN-COLOR RED

Data Bit D7 D6 D5 D4 D3 D2 D1 D0 Red Value R7 R6 R5 R4 R3 R2 R1 R0

Index = 20h

OVERSCAN-COLOR GREEN

Data Bit D7 D6 D5 D4 D3 D2 D1 D0 Green Value G7 G6 G5 G4 G3 G2 G1 G0

Index = 21h

OVERSCAN-COLOR BLUE

Data Bit D7 D6 D5 D4 D3 D2 D1 D0 Blue Value B7 B6 B5 B4 B3 B2 B1 B0

Index = 22h

V alues 00 (hex) to FF (hex) may be written into the overscan color registers.

2–48

2.16.15 CRC LSB and MSB Registers

These registers are used to read the result of the 16-bit CRC calculation (see Section 2.9.1). They are not initialized and may be read from by the MPU at any time. Note, however, that they are only updated on the rising edge of the second HSYNC during vertical retrace.

CRCLSB and CRCMSB are cascaded to form a 16-bit CRC calculation remainder.

CRC MSB CRC LSB

Data Bit D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 CRC Remainder R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0

Index = 3Dh Index = 3Ch

2.16.16 CRC-Control Register

This write-only register is used to specify on which of the 24 DAC data lines the 16-bit CRC should be calculated (see Section 2.9.1). The register is not initialized and may be written to by the MPU at any time. The CRC control-register data format is shown below.

CRC-CONTROL REGISTER

Data Bit D7 D6 D5 D4 D3 D2 D1 D0 Select Data 0 0 0 D4 D3 D2 D1 D0

Index = 3Eh

V alues from 00 (hex) to 17 (hex) may be written into the CRC control register.

2–49

2–50

3 Electrical Characteristics

3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range

(unless otherwise noted)

Supply voltage, V Input voltage range, V

Analog output short-circuit duration to any power supply or common unlimited. . . . . . .

Operating free-air temperature range, T

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Junction temperature 175°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Case temperature for 10 seconds: FN package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to GND.

(see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

–0.5 V to VDD + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Recommended Operating Conditions

MIN NOM MAX UNIT

Supply voltages, AV Reference voltage, V High-level input voltage, V Low-level input voltage, V Output load resistance, R FS ADJUST resistor, R Operating free-air temperature, T

DD,

ref

SET

4.75 5 5.25 V

1.15 1.235 1.26 V

2.4 VDD+0.5 V

0.8 V

37.5 Ω 523 Ω

0 70 °C

3–1

3.3 Electrical Characteristics

Low level output

High level input

Low level input

I (

)

(see Note 2)

Supply current, true V

CiI

PARAMETER

High-level output voltage IOH= –800 µA 2.4 V

D(0–7), VCLK, RCLK,

Low-level output

voltage

Differential input

voltage Common-mode

input voltage High-level input

current Low-level input

current

Supply current, pseudo-color mode

see Note 2

Supply current, true-

color mode

High-impedance-state output current 10 µA

nput capacitance

†

All typical values are at VDD = 5 V, TA = 25°C.

NOTE 2: IDD is measured with dot clock running at the maximum specified frequency, SCLK frequency = dot

clock frequency/8 (in pseudo-color modes), and the palette RAM loaded with repeating full-range toggling patterns (00h/00h/00h/00h/FFh/FFh/FFh/FFh). Pseudo-color mode is also known as color indexing mode.

SENSE HSYNCOUT, VSYNCOUT IOL=15mA 0.4 SCLK IOL=18mA 0.4

ECL inputs 0.6 6 V

ECL inputs 2.85 3.15 VDD–0.5 V TTL inputs VI= 2.4 V 1

ECL inputs TTL inputs VI= 0.8 V –1 ECL inputs TVP3010-85 TVP3010-1 10 TVP3010-135 TVP3010-170 390 440 TVP3010-85 TVP3010-1 10 TVP3010-135 TVP3010-170 420 475

TTL inputs

ECL inputs

TEST

CONDITIONS

IOL= 3.2 mA 0.4

VI=4V 1

VI= 0.4 V –1

f = 1 MHz, VI= 2.4 V

f = 1 MHz, VI=4V

MIN TYP

†

MAX UNIT

250 280 270 320 330 380

270 320 320 370 370 420

3–2

3.4 Operating Characteristics

DAC)

bit

End point linearity error

LSB

Differential linearity error

LSB

Output current (see Note 3) Pipeli

VGA

Pipeli

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

esolution (each

End-point linearity error

(each DAC) Differential linearity error

(each DAC) Gray scale error 5%

Output current (see Note 3)

DAC-to-DAC matching 2% 5% DAC-to-DAC crosstalk –20 dB Output compliance –1 1.2 V Voltage reference output

voltage Output impedance 50 kΩ Output capacitance f = 1 MHz, I Sense voltage reference 300 350 400 mV Clock and data feedthrough –20 dB Glitch impulse (see Note 4) 50 pV–s

ne delay,

ne delay, pixel por

NOTES: 3. Test conditions for RS343-A video signals (unless otherwise specified) can be found in “Recommended

Operating Conditions” using external voltage reference V internal voltage reference, R

4. Glitch impulse does not include clock and data feedthrough. The – 3-dB test bandwidth is twice the clock rate.

por

8/6 high 8 8/6 low 6 8/6 high 1 8/6

low 1/4 8/6 high 1 8/6

low 1/4

White level relative to blank 17.69 19.05 20.4 mA White level relative to black

(7.5 IRE only) Black level relative to blank

(7.5 IRE only) Blank level on IOR, IOB Blank level on IOG

(with SYNC enabled) Sync level on IOG (with SYNC enabled) 0 5 50 µA One LSB (8/6 high) 69.1 µA One LSB (8/6 low) 276.4 µA

= 0 13 pF

OUT

Self-clocked timing 18 dot clock periods Externally-clocked timing 15 dot clock periods Self-clocked timing 2 RCLK + 14 dot clock periods Externally-clocked timing 1 RCLK +14 dot clock periods

= 1.235 V, R

may need to be adjusted in order to meet these limits.

SET

ref

16.74 17.62 18.5 mA

0.95 1.44 1.9 mA 0 5 50 µA

6.29 7.6 8.96 mA

1.15 1.235 1.26 V

= 523 Ω. When using the

SET

3–3

3.5 Timing Requirements (see Note 5)

tcClock

tw3Pul

tw4Pul

TVP3010

-85

MIN MAX MIN MAX MIN MAX MIN MAX

Dot clock frequency 85 110 135 170 MHz CLK0 frequency for VGA

pass-through mode (see Note 6)

11.8 9.1 7.4 7.1

cycle time

Setup time, RS(0–3) valid before RD

su1

or WR↓ Hold time, RS(0–3) valid after RD or

↓

Setup time, D(0–7)valid before WR↑ 35 35 35 35 ns

su2

Hold time, D(0–7)valid after WR↑ 0 0 0 0 ns

Setup time, VGA(0–7) and VGABL

su3

valid before CLK0↑ (see Note 7) Hold time, VGA(0–7) and VGABL

valid after CLK0↑ (see Note 7) Setup time, P(0–31) and PSEL valid

su4

before LCLK↑ (see Note 8) Hold time, P(0–31) and PSEL valid

after LCLK↑ (see Note 8) Setup time, HSYNC, VSYNC, and

su5

SYSBL

valid before VCLK↓

Hold time, HSYNC, VSYNC and

SYSBL

valid after VCLK↓

Pulse duration, RD or WR low 50 50 50 50 ns

Pulse duration, RD or WR high 30 30 30 30 ns

se duration, clock hig

se duration, clock low

Pulse duration, SFLAG high

(see Note 9) Pulse duration, SCLK high

(see Note 9)

NOTES: 5. TTL input signals are 0 to 3 V with less than 3-ns rise/fall time between the 10% and 90% levels unless

otherwise specified. ECL input signals are VDD–1.8 V to VDD– 0.8 V with less than 2-ns rise/fall time between the 20% and 80% levels. For input and output signals, timing reference points are at the 10% and 90% signal levels. Analog output loads are less than 10 pF. D(0–7) output loads are less than 50 pF. All other output loads are less than 50 pF unless otherwise specified.

6. In VGA mode, CLK0 minimum pulse duration for clock low should be greater than 4.8 ns. If VGA switching is to be performed using self-clocked timing, the maximum pixel rate cannot exceed 50 MHz.

7. Reference to CLK0 input only.

8. RCLK is delayed from SCLK in such a way that when RCLK is connected to LCLK, the timing is essentially the same as the TLC3407x family of parts.

9. This parameter applies when the split shift-register transfer (SSRT) function is enabled. See Section 2.15 for details.

TTL

11.8 9.1 7.4 5.8

ECL

10 10 10 10 ns

2 2 2 2 ns

5 5 5 5 ns

1 1 1 1 ns

TTL ECL TTL ECL

4 3.5 3 3 4 3 3 2.5 4 3.5 3 3 4 3 3 2.5

30 30 30 30 ns

15 55 15 55 15 55 15 55 ns

TVP3010

-110

85 85 85 85 MHz

TVP3010

-135

TVP3010

-170

UNIT

3–4

3.6 Switching Characteristics

PARAMETER

UNIT

TVP3010-85 TVP3010-110

MIN TYP MAX MIN TYP MAX

SCLK frequency (CL ≤ 15 pF) (see Note 10)

SCLK frequency (CL ≤ 60 pF) (see Note 10)

RCLK/VCLK frequency (see Note 10) 85 85 MHz t t t

t t

t t t

NOTES: 10. SCLK can drive an output capacitive load up to 60 pF. The worst-case transition time between the 10% and

Enable time, RD low to D(0–7) valid 40 40 ns

en1

Disable time, RD high to D(0–7) disabled 17 17 ns

dis1

Valid time, D(0–7) valid after RD high 5 5 ns

Propagation delay, SFLAG↑ to SCLK

PLH1

high (see Note 10 and 11)

Delay time, RD low to D(0–7) starting to

turn on

Delay time, selected input clock high/low

to dot clock (internal signal) high/low

Delay time, SCLK high/low to RCLK

high/low (see Note 12)

Delay time, VCLK high/low to RCLK

high/low (see Note 12)

Delay time, RCLK high/low from dot clock

high/low (internal signal)

Delay time, LCLK from RCLK t

Delay time, dot clock high to

IOR/IOG/IOB active (analog output delay

time) (seeNote13)

Analog output settling time(seeNote 14) 6 6 ns

Delay time, dot clock high to HSYNCOUT

and VSYNCOUT valid

Analog output rise time (see Note 15) 2 2 ns

Analog output skew 0 2 0 2 ns

90% levels is less than 4 ns (typical 3 ns). RCLK and VCLK can drive output capacitive loads up to 15 pF, with worst-case transition times between 10% and 90% levels less than 4 ns (typical 3 ns).

11. This parameter applies when the split shift-register transfer (SSRT) function is enabled. See Section 2.15 for details.

12. The SCLK and VCLK delay time to RCLK depends on the load that the signals drive. This parameter is measured with an RCLK to VCLK ratio of 1:1, a VCLK = RCLK load of 15 pF, and an SCLK load of 60 pF.

13. Measured from the 90% point of the rising edge of the internal dot clock signal to 50% of the full-scale transition

14. Measured from the 50% point of the full-scale transition to the point at which the output has settled within ± 1 LSB (settling time does not include clock and data feedthrough)

15. Measured between 10% and 90% of the full-scale transition

0 20 0 20 ns

5 5 ns

1 2 5 1 2 5 ns

1 3 6 1 3 6 ns

85 85 MHz

7 7 ns

RCLK–7

4 4 ns

9 9 ns

RCLK–7

3–5

3.6 Switching Characteristics (Continued)

PARAMETER

UNIT

TVP3010-135 TVP3010-170

MIN TYP MAX MIN TYP MAX

SCLK frequency (CL ≤ 15 pF) (see Note 10)

SCLK frequency (CL ≤ 60 pF) (see Note 10)

RCLK, VCLK frequency (see Note 10) 85 85 MHz t t t

t t

t t t

NOTES: 10. SCLK can drive an output capacitive load up to 60 pF. The worst-case transition time between the 10% and

Enable time, RD low to D(0–7) valid 40 40 ns

en1

Disable time, RD high to D(0–7) disabled 17 17 ns

dis1

Valid time, D(0–7) valid after RD high 5 5 ns

Propagation delay, SFLAG↑ to SCLK

PLH1

high (see Note 10 and 11)

Delay time, RD low to D(0–7) starting to

turn on

Delay time, selected input clock high/low

to dot clock (internal signal) high/low

Delay time, SCLK high/low to RCLK

high/low (see Note 12)

Delay time, VCLK high/low to RCLK

high/low (see Note 12)

Delay time, RCLK high/low from dot clock

high/low (internal signal)

Delay time, LCLK from RCLK t

Delay time, dot clock high to

IOR/IOG/IOB active (analog output delay

time) (seeNote13)

Analog output settling time(seeNote 14) 6 5 ns

Delay time, dot clock high to HSYNCOUT

and VSYNCOUT valid

Analog output rise time (see Note 15) 2 2 ns

Analog output skew 0 2 0 2 ns

90% levels is less than 4 ns (typical 3 ns). RCLK and VCLK can drive output capacitive loads up to 15 pF, with worst-case transition times between 10% and 90% levels less than 4 ns (typical 3 ns).

11. This parameter applies when the split shift-register transfer (SSRT) function is enabled. See Section 2.15 for details.

13. Measured from the 90% point of the rising edge of the internal dot clock signal to 50% of the full-scale transition

14. Measured from the 50% point of the full-scale transition to the point at which the output has settled, within ± 1 LSB (settling time does not include clock and data feedthrough)

15. Measured between 10% and 90% of the full-scale transition

0 20 0 20 ns

5 5 ns

1 2 5 1 2 5 ns

1 3 6 1 3 6 ns

85 87.5 MHz

85 85 MHz

7 7 ns

RCLK–7

4 4 ns

9 9 ns

RCLK–7

3–6

3.7 Timing Diagrams

RS0–RS2

,WR

D0–D7

su1

90% 10%

Valid

en1

90% 10%

90%

Data Out, RD Low

10%

su2

Figure 3–1. MPU Interface Timing

90% 10%

Data In,

Low

90%

10%

90% 90%

10% 10%

dis1

90%

3–7

CLK0–CLK4

Dot Clock

(internal signal)

50%

10% 10%

90%

10%

50%

10%

SCLK

VCLK

(in phase)

RCLK

LCLK

VGA(0–7)

HSYNC

, VSYNC

VGABL

(VGA mode)

P(0–31), PSEL

, VSYNC

HSYNC

OVS, SYSBL

(other modes)

IOR, IOG, IOB

su3

10%

90%

Data

90%

10%

90%

50%

su5

10%

90%

50%

90% 90%

Data

10%

50%

90%

10%

su4

10%

50%

10%

90% 90%

Data

90%

10%

3–8

HSYNCOUT

VSYNCOUT

Valid

Figure 3–2. Video Input/Output Timing

90%

Valid

SYSBL

SFLAG

90%

SCLK

PLH1

90%

Figure 3–3. SFLAG Timing (When SSRT Function is Enabled)

3–9

3–10

Appendix A

PC-Board Layout Considerations

PC-Board Considerations

It is recommended that a four-layer PC board be used with the TVP3010 video interface palette: one layer for 5-V power, one for GND, and two for signals. The layout should be optimized for the lowest noise on the TVP3010 power and ground lines by shielding the digital inputs and providing good decoupling. The lead length between groups of analog V minimize inductive ringing. The TVP3010 P(0–31) terminal assignments have been selected for minimum interconnect lengths between these inputs and the standard VRAM pixel-data outputs. The TVP3010 should be located as close as possible to the output connectors to minimize noise pickup and reflections due to impedance mismatch.

The analog outputs are susceptible to crosstalk from digital lines; digital traces must not be routed under or adjacent to the analog output traces.

For maximum performance, the analog video-output impedance, cable impedance, and load impedance should be the same. The load-resistor connection between the video outputs and GND should be as close as possible to the TVP3010 to minimize reflections. Unused analog outputs should be connected to GND.

Analog output video edges exceeding the CRT monitor bandwidth can be reflected, producing cablelength-dependent ghosts. Simple pulse filters can reduce high-frequency energy, thus reducing EMI and noise. The filter impedance must match the line impedance.

Ground Plane

It is recommended that only one ground plane be used for both the TVP3010 and the rest of the logic. Separate digital and analog ground planes are not needed and can potentially cause system problems.

and GND terminals (see Figure A–1) should be minimized so as to

Power Plane

Split-power planes for the TVP3010 and the rest of the logic are recommended. The TVP3010 VIP and its associated analog circuitry should have its own power plane, referred to as analog V power planes should be connected at a single point through a ferrite bead, as shown in Figures A–1 and A–2.This bead should be located as near as possible to where the power supply connects to the board. T o maximize the high-frequency power supply rejection, the video output signals should not overlay the analog power plane.

(AVDD). These two

Supply Decoupling

The bypass capacitors should be installed using the shortest leads possible. This reduces the lead inductance and is consistent with reliable operation.

For the best performance, a 0.1-µF ceramic capacitor in parallel with a 0.01-µF chip capacitor should be used to decouple each of the groups of power terminals to GND. These capacitors should be placed as close as possible to the device, as shown in Figure A–2.

If a switching power supply is used, the designer should pay close attention to reducing power supply noise and consider using a three-terminal voltage regulator for supplying power to A VDD.

A–1

COMP and REF Pins

A 0.1-µF ceramic capacitor should be connected between AVDD and COMP to avoid noise and color-smearing problems. A 0.1-µF ceramic capacitor is also recommended between GND and REF to further stabilize the output image. This 0.1-µF capacitor is needed for either internal or external voltage references. These capacitor values may depend on the board layout; experimentation may be required in order to determine optimum values.

Analog Output Protection

The TVP3010 analog output should be protected against high-energy discharges, such as those from monitor arc-over or from hot-switching ac-coupled monitors.

The diode protection circuit shown in Figure A–1 can prevent latch-up under severe discharge conditions without adversely degrading analog transition times. The IN4148/9 parts are low-capacitance, fast-switching diodes, which are also available in multiple-device packages (FSA250X or FSA270X) or surface-mountable pairs (BAV99 or MMBD7001).

A–2

COMP

TVP3010

FS ADJUST

REF

GND

IOR IOG

IOB

C1–C2 C3–C4

C12

R2 R3 R4 R5

C11 C6 – C8

To Video Connector

1N148/9

DAC

Output

GND

Optional Diode

1N148/9

C9 – C10

Protection

Circuit

To Monitor

GND

Location Description VENDOR PART NUMBER

C1, C2, C5, C6–C8, C12 0.1-µF ceramic capacitor Erie RPE110Z5U104M50V C3, C4, C9, C10 0.01-µF ceramic chip capacitor AVX 12102T103QA1018 C11 33-µF tantalum capacitor Mallory CSR13F336KM L1 Ferrite bead Fair-Rite 2743001111 R1 1000-Ω 1% metal-film resistor Dale CMF-55C R2 523-Ω 1% metal-film resistor Dale CMF-55C R3, R4, R5 75-Ω 1% metal-film resistor Dale CMF-55C D1 1.2-V voltage reference TI LM385-1.2

†

The vendor numbers above are listed only as a guide. Substitution of devices with similar characteristics do not affect the performance of the TVP3010.

‡

Or equivalent only.

NOTE: R1, D1, and the reset circuit are optional. In general, each pair of device power and GND pins

should be separately decoupled with 0.1-µF and 0.01-µF capacitors.

‡

†

Figure A–1. Typical Connection Diagram and Parts

A–3

C3 C1

C4 C2

C5 C12

Edge of Board

C8C10

TVP3010

(84-Pin PLCC)

C9C6

C11

DB15 or DB9 Connector

Analog Power

Digital Power

Figure A–2. Typical Component Placement With Split-Power Plane

A–4

Appendix B

RCLK Frequency < VCLK Frequency

The VCLK, RCLK, and SCLK outputs generated by the TVP3010 VIP are free-running clocks. The video-control signals (i.e., HSYNC relationship between video-control signals and VCLK can be expected. The TVP3010 samples and latches the blank

internal input on the falling edge of VCLK. It then looks at the internal RCLK signal to determine when to enable or disable SCLK at the output terminal. The decision is determined when the RCLK frequency is greater than or equal to the VCLK frequency . However, when the RCLK frequency is less than the VCLK frequency , the appearance of the SCLK waveform at the output terminal (when SYSBL low on the falling edge of VCLK) can vary (see Figures B–1 and B–2).

To avoid this variation in the SCLK output waveform, the RCLK and VCLK frequencies should be chosen so that HTOTAL is evenly divisible by the ratio of the VCLK frequency to the RCLK frequency:

remainder of [ HTOTAL/(VCLK frequency/RCLK frequency)] = 0

For example, if HTOT AL is even, VCLK frequency = dot clock frequency/8 and RCLK frequency = dot clock frequency/16. Then the above formula is satisfied. NOTE: When HTOTAL starts at zero, then the formula becomes:

remainder of [ (HTOTAL + 1)/(VCLK frequency/SCLK frequency) ] = 0.

VCLK

SYSBL

At Input

Terminal

RCLK

, VSYNC, and SYSBL) are normally generated from VCLK, and a fixed

is sampled

SCLK

VCLK

SYSBL

At Input

Terminal

RCLK

SCLK

Figure B–1. VCLK and SCLK Phase Relationship (Case 1)

Figure B–2. VCLK and SCLK Phase Relationship (Case 2)

B–1

B–2

Appendix C

Little-Endian and Big-Endian Data Formats

It is commonly known in the computer industry that there are two different formats for memory configuration: little-endian (Intel microprocessor-based format) and big-endian (Motorola microprocessor-based format). When the Texas Instruments programmable pixel bus was introduced on the TLC34075 video interface palette, it allowed little-endian-based graphics-board manufacturers to design a single graphics board that could be programmed to support multiple resolutions and pixel depths. The connection of the pixel bus from the video RAM to the palette device was not a problem until big-endian-based customers desired the same capability to program their graphics designs from 1 bit/pixel (bpp), 2 bpp, 4 bpp, 8 bpp, 12 bpp, 16 bpp, 24 bpp, to 32 bpp.

For this reason, the TVP3010 video interface palette supports both little- and big-endian data formats on its pixel-bus/frame-buffer interface. The device defaults to little-endian mode at reset (general-control register bit 3 set to logic 0) to be compatible with most PC-based systems. Big-endian-mode operation can be achieved by configuring the device to the big-endian mode (general-control register bit 3 set to logic 1) and externally reverse wiring the pixel bus from video RAM to the TVP3010 on the graphics board.

The differences between the big-endian and little-endian data formats are illustrated in Figure C–1. The figure shows that the data fields representing the individual pixels in the big-endian format are in the reverse order of the little-endian format. Since the TVP3010 VIP always shifts data from low-numbered data fields to high-numbered data fields, external swapping of the pixel bus (i.e., D31 connected to P0, D0 connected to P31) ensures that the pixels are displayed on the monitor in the correct sequence. However, swapping the big-endian pixel bus causes the bits within each data field to be reversed (i.e., MSB to LSB instead of LSB to MSB). When general-control register bit 3 is set to a logic 1, unique circuitry within the TVP3010 corrects the bit sequence in each data field as it is shifted into the part. This correction is bit-plane independent and occurs regardless of whether 8, 4, 2, or 1 bit/pixel are being used.

The TVP3010 also supports 12-, 16-, and 24-bit true-/direct-color for both little- and big-endian data formats on the pixel bus. By using the same wiring for big-endian operation as described above, all true-/direct-color modes are made available without hardware modification. Tables 2–8 through 2–11 give the true-/directcolor bit definitions for all modes. For example, when in one of the 16-bit true-color modes (big endian), the first RGB data word to be displayed is located in bits 16–31 of VRAM. Swapping the external pixel bus when designing the graphics board ensures the correct display sequence by causing the first RGB word to appear at pixel bus inputs P(0 – 15). However, the bit order within the word is reversed. When general-control register bit 3 is set to a logic 1, the bit sequence is automatically corrected by circuitry within the TVP3010.

C–1

Little Endian Big Endian

Monitor

Screen

4 Adjacent

Pixels

B0 B1 B2 B3

32-Bit Word

In Memory

B0 B1 B2 B3

0-7 8 -15 16 -23 24 -31 0-7 8 -15 16 -23 24 -31

B3 B2 B1 B0

LSB MSB LSB MSB

Figure C–1. Little-Endian and Big-Endian Mapping of 4-Bit/Pixel

Pseudo-Color Data in Memory to Monitor Screen

C–2

Appendix D

Examples: Register Settings

Table D–1. 8-Bit/Pixel Pseudo-Color (32-Bit Pixel Bus, 4:1)

Self-Clocked, LCLK and RCLK Enabled

Input-Clock Selection 1A xx Any clock can be chosen Output-Clock Selection 1B 52 RCLK = SCLK = /4, VCLK = /4 (VCLK could be different) General Control 1D 20 Default settings Auxiliary Control 29 09 Default settings, self-clocked, palette graphics, no zoom Color-Key Control 38 10 Default settings, pointing to palette graphics Multiplexer-Control Register 1 18 80 Pseudo-color Multiplexer-Control Register 2 19 1B 8 bpp, 4:1, 32-bit pixel bus width Configuration Register 1E 30 Enable LCLK and RCLK

INDEX

(HEX)

Table D–2. 24-Bit True Color (32-Bit Pixel Bus, 1:1) Self-Clocked, RCLK = LCLK Internal

Input-Clock Selection 1A xx Any clock can be chosen Output-Clock Selection 1B 40 RCLK = SCLK = /1, VCLK = /1 (VCLK could be different) General Control 1D 20 Default settings Auxiliary Control 29 09 Default settings, self-clocked, palette graphics, no zoom Color-Key Control 38 10 Default settings, pointing to palette graphics Multiplexer-Control Register 1 18 46 24-bit true color Multiplexer-Control Register 2 19 03 24-bit true color, 32-bit pixel bus width Configuration Register 1E 00 Default setting, RCLK internally connected to LCLK

INDEX

(HEX)

SETTING

(HEX)

SETTING

(HEX)

DESCRIPTION

T able D–3. 24-Bit Direct Color (32-Bit Pixel Bus, 1:1) Self-Clocked, No Overlay

Input-Clock Selection 1A xx Any clock can be chosen Output-Clock Selection 1B 40 RCLK = SCLK = /1, VCLK = /1 (VCLK could be different) General Control 1D 20 Default settings Auxiliary Control 29 08 Self clocked, no window, nonpalette graphics, no zoom Color-Key Control 38 00 Disabled, pointing to nonpalette graphics Multiplexer-Control Register 1 18 06 24-bit direct color Multiplexer-Control Register 2 19 1B 24-bit direct color, 32-bit pixel bus width

INDEX

(HEX)

SETTING

(HEX)

DESCRIPTION

D–1

Table D–4. 24-Bit Direct Color (32-Bit Pixel Bus, 1:1) Self-Clocked, Overlay PSEL Switched

Input-Clock Selection 1A xx Any clock can be chosen Output-Clock Selection 1B 40 RCLK = SCLK = /1, VCLK = /1 (VCLK could be different) General Control 1D 20 Default settings Auxiliary Control 29 0C Self clocked, PSEL enabled, overlay when PSEL = 1 Color-Key Control 38 00 Disabled, pointing to nonpalette graphics Multiplexer-Control Register 1 18 06 24-bit direct color Multiplexer-Control Register 2 19 1B 24-bit direct color, 32-bit pixel bus width

INDEX

(HEX)

SETTING

(HEX)

DESCRIPTION

Table D–5. 24-Bit Direct Color (32-Bit Pixel Bus, 1:1) Externally-Clocked, VGA PSEL Switched

Input-Clock Selection 1A xx Any clock can be chosen Output-Clock Selection 1B 40 RCLK = SCLK = /1, VCLK = /1 (VCLK could be different) General Control 1D 20 Default settings Auxiliary Control 29 04 Externally clocked, PSEL enabled, VGA when PSEL = 1 Color-Key Control 38 00 Disabled, pointing to nonpalette graphics Multiplexer-Control Register 1 18 06 24-bit direct color Multiplexer-Control Register 2 19 9B 24-bit direct color, 32-bit pixel bus width Configuration Register 1E 20 LCLK enabled for external timing mode

INDEX

(HEX)

SETTING

(HEX)

DESCRIPTION

T able D–6. 16-Bit Direct Color (32-Bit Pixel Bus, 2:1) Self-Clocked,

Overlay Auxiliary Window Switched

Input-Clock Selection 1A xx Any clock can be chosen Output-Clock Selection 1B 49 RCLK = SCLK = /2, VCLK = /2 (VCLK could be different) General Control 1D 20 Default settings Auxiliary Control 29 0A Self clocked, auxiliary window enabled, overlay in window Color-Key Control 38 00 Disabled, pointing to nonpalette graphics Multiplexer-Control Register 1 18 05 16-bit direct color – XGA format Multiplexer-Control Register 2 19 03 16-bit direct color, 32-bit pixel bus width

NOTE: For this mode, the auxiliary-window start and stop registers (Index 10 – 17) must be programmed with the

appropriate window coordinates (within active display). See sections 2.16.6 and 2.16.7.

INDEX

(HEX)

SETTING

(HEX)

DESCRIPTION

D–2

Appendix E

Mechanical Data

FN/S-PQCC-J **

20-PIN SHOWN

0.048 (1,22)

0.042 (1,07)

JEDEC

OUTLINE PINS**

MO-047AA

MO-047AB

MO-047AC

MO-047AD

MO-047AF 84

X 45°

913

NO. OF

MIN MAX

68MO-047AE

0.385 (9,78)

0.485

(12,32)

0.685

(17,40)

0.785

(19,94)

0.985

(25,02)

1.185

(30,10)

1319

0.050 (1,27) TYP

D / E

0.395

(10,03)

0.495

(12,57)

0.695

(17,65)

0.795

(20,19)

0.995

(25,27)

1.195

(30,35)

D1 / E

MIN MAX MIN MAX TYP

0.350 (8,89)

0.450

(11,43)

0.650

(16,51)

0.750

(19,05)

0.950

(24,13)

1.150

(29,21)

PLASTIC J-LEADED CHIP CARRIER

0.180 (4,57) MAX

0.120 (3,05) MAX

0.020 (0,51) MIN

D3 / E

D2 / E

0.356 (9,04)

0.456

(11,58)

0.656

(16,66)

0.756

(19,20)

0.956

(24,28)

1.158

(29,41)

0.290 (7,34)

0.390 (9,91)

0.590

(14,99)

0.690

(17,53)

0.890

(22,61)

1.090

(27,69)

D2 / E

0.330 (8,38)

0.430

(10,92)

0.630

(16,00)

0.730

(18,54)

0.930

(23,62)

1.130

(28,70)

D3 / E

0.200 (5,08)

0.300 (7,62)

0.500

(12,70)

0.600

(15,24)

0.800

(20,32)

1.000

(25,40)

4040005/A–10/93

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Dimensions D1 and E1 do not include mold flash protrusion. Protrusion shall not exceed 0.010 (0,25) on

any side.

D. All dimensions conform to JEDEC Specification MO-047.

E. Maximum deviation from coplanarity is 0.004 (0,10).

E–1

E–2

Misc. Control Register Bit Definitions

control or internally generated overscan con

able the user–defined overscan screen bor SYNC inf

IOG

gp g

1 1

2.10

General Control Register

The General Control register is used to control various functions of VIEWPOINT . It can be accessed by MPU at anytime. Bit 7 of General Control register corresponds to data bus bit 7. Index = 1D (hex).

Table J–1. General Control Register

Bit Name

GCR7 0: External OVS pin (default) Overscan Control Select. Selects external pin

1: Internal

GCR6 0: Disable (default) Overscan Enable. Specifies whether to en-

1: Enable

GCR5 0: Disable Sync Enable. This bit specifies whether

1: Enable (default)

GCR4 0: 0 IRE (default) Pedestal Control. This bit specifies whether a

1: 7.5 IRE

GCR3 0: Little Endian (default) Little Endian/Big Endian Select. Selects either

1: Big Endian

GCR2 0: Disable (default) Split Shift Register Transfer Enable. See Sec-

1: Enable

GCR1 0: Active low (default) VSYNCOUT Output Polarity. See Section

1: Active high

GCR0 0: Active low (default) HSYNCOUT Output Polarity. See Section

1: Active high

Values Description

trol. See Section 2.7.

ders.

0 or 7.5 IRE blanking pedestal is to be generated on the video outputs. 0 IRE specifies that the black and blank levels are the same.

Little or Big Endian format for the pixel bus frame buffer interface. See Sections 2.4 and

2.8.1.

tion 2.

–

ormation is to be output onto

E–1

Cursor Control Register

1) or disables (logic 0) the 64 x 64 sprite cur

hair cursor and the user–defined cursor area

(g )

whether the cross hair cursor is to be dis

of the cross hair is one, three, five, or seven

iti

The Cursor Control register is used to control various on–chip cursor function of VIEWPOINT. It may be accessed by MPU at any time. Bit 7 of the Cursor Control register corresponds to data bus bit 7. Index = 06 (hex).

Table J–2. Cursor Control Register

Bit Name

CCR7 X Reserved

CCR6 0: Disable (default) Sprite Cursor Enable. This bit enables (logic

1: Enable

CCR5 0: (default) Dual Cursor Format. This bit specifies the dis-

CCR4 0: XGA (default) 64 x 64 Cursor Mode Select. This bit specifies

1: X–Windows

CCR3 0: Color 0 (default) Cross Hair Color Selection. This bit specified

1: Color 1

CCR2 0: Disable (default) Cross Hair Cursor Enable. This bit specifies

1: Enable

CCR1, CCR0 00: 1 pixel (default) Cross Hair Thickness. These bits specify

01: 3 pixels 10: 5 pixels 11: 7 pixels

Values Description

sor.

play format at the intersection of the cross hair cursor and the user–defined cursor area. See Section 2.5.5 and the cursor intersection truth table.

whether the XGA (logic 0) or X–windows format is used to interpret the data stored in the 64 x 64 cursor sprite RAM. See Section 2.5.2.

whether the cross hair cursor is to be displayed in color 1 (logical 1) or color 0 (logical

0).

played (logical 1) or not (logical 0).

whether the vertical and horizontal thickness of the cross hair is one, three, five, or seven pixels. The segments are centered about the value in the Cursor Pos

on (x,y) register.

E–2

Cursor Position (x, y) Register

These registers are used to specify the (x,y) coordinate of the intersection of the cross hair cursor. They are also used in conjunction with the Sprite Origin register to specify the location of the 64 x 64 cursor area (see 2.5.3). The Cursor Position X register is made up of the Cursor Position X LSB (CPXL) and the Cursor Position X MSB (CPXM); the Cursor Position Y register is made up of the Cursor Position Y LSB (CPYL) and the Cursor Position Y MSB (CPYM). All registers are initialized to 00 (hex), and may be written to or read from by the MPU at any time. The Cursor Position is not updated until the vertical retrace interval after CPYM has been written to by the MPU.

CPXL and CPXM are cascaded to form a 12–bit Cursor Position X register. Similarly, CPYL and CPYM are cascaded to form a 12–bit Cursor Position Y register. Bits D4–D7 of CPXM and CPYM are always a logical zero.

T able J–3.

Cursor Position X MSB Cursor Position X LSB

(CPXM) (CPXL)

Data bit D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 X Address 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0

Index = 01h Index = 00h

T able J–4.

Cursor Position Y MSB Cursor Position Y LSB

(CPYM) (CPYL)

Data bit D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Y Address 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0

Index = 03h Index = 02h

The Cursor Position X value to be written is calculated as follows:

Cx = desired display screen x position V alues from 0000 (hex) to 0fff (hex) may be written into the Cursor Position X register. The Cursor Position Y value to be written is calculated as follows:

Cy = desired display screen y position V alues from 0000 (hex) to 0fff (hex) may be written into the Cursor Position Y register. The values written into the Cursor Position X and Y registers should be relative to the first displayed pixel

on the screen; i.e. (0,0).

E–3

Sprite Origin (x, y) Register

These registers are used to specify the (x,y) location of the 64 x 64 Sprite with respect to the cross hair location (see 2.5.3). The Sprite Origin X and Y registers can contain values from 0 to 63 decimal. Both registers are initialized to 1F (hex), 31 (decimal), which sets the center of the cross–hair at the center of the 64 X 64 sprite. Both registers may be written to or read from by the MPU at any time. The Sprite Origin is not updated until the vertical retrace interval after Sprite Origin X and Y registers have been written by the MPU.

T able J–5.

Sprite Origin X

Data bit D7 D6 D5 D4 D3 D2 D1 D0 X Origin 0 0 Y5 4 3 2 1 0

Index = 04h

T able J–6.

Sprite Origin Y

Data bit D7 D6 D5 D4 D3 D2 D1 D0 Y Origin 0 0 5 4 3 2 1 0

Index = 05h

V alues from 00 (hex) to 3F (hex) may be written into the Sprite Origin X and Y registers. Bits D6 and D7 are always 0.

E–4

Window Start (x, y) Register

These registers are used to specify the (x,y) coordinate of the upper left corner of the cross hair cursor window or auxiliary window. The Window Start X register is made up of the Window Start X LSB (WSXL) and the Window Start X MSB (WSXM); the Window Start Y register is made up of the Window Start Y LSB (WSYL) and the Window Start Y MSB (WSYM). They are not initialized and may be written to or read from by the MPU at any time. The Window Start is not updated until the vertical retrace intrval after WSYM has been written to by the MPU.

WSXL and WSXM are cascaded to form a 12–bit Window Start X register. Similarly, WSYL and WSYM are cascaded to form a 12–bit Window Start Y register. Bits D4–D7 of WSXM and WSYM are always a logical zero.

T able J–7.

Window Start X MSB Window Start X LSB

(WSXM) (WSXL)

Data bit D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 X Address 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0

Index = 1 1h Index = 10h

T able J–8.

Window Start Y MSB Window Start Y LSB

(WSYM) (WSYL)

Data bit D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Y Address 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0

Index = 15h Index = 14h

The Window Start X value to be written is calculated as follows:

Wx = desired display screen x position V alues from 0000 (hex) to 0fff (hex) may be written into the Window Start X register. The Window Start Y value to be written is calculated as follows:

Wy = desired display screen y position V alues from 0000 (hex) to 0fff (hex) may be written into the Window Start Y register. The values wirtten into the Window Start X and Y registers should be relative to the first displayed pixel on

the screen; i.e. (0,0). Note that the Window Start location specified is the first location inside the window. For the cross hair cursor

or auxiliary window to be displayed, the Window Start registers must specify a point on the active display .

E–5

Window Stop (x, y) Register

These registers are used to specify the (x,y) coordinate of the lower right corner of the cross hair cursor or auxiliary window. The Window Stop X register is made up of the Window Stop X LSB (WSPXL) and the Window Stop X MSB (WSPXM); the Window Stop Y register is made up of the Window Stop Y LSB (WSPYL) and the Window Stop Y MSB (WSPYM). They are not initialized and may be written to or read from by the MPU at any time. The Window Stop is not updated until the vertical retrace interval after WSPYM has been written to by the MPU.

WSPXL and WSPXM registers are cascaded to form a 12–bit Window Stop X register. Similarly, WSPYL and WSPYM registers are cascaded to form a 12–bit Window Stop Y register. Bits D4–D7 of WSPXM and WSPYM are always a logical zero.

T able J–9.

Window Stop X MSB Cursor Position X LSB

(WSPXM) (WSPXL)

Data bit D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 X Address 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0

Index = 13h Index = 12h

T able J–10.

Cursor Position X MSB Cursor Position X LSB

(WSPYM) (WSPYL)

Data bit D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 X Address 0 0 0 0 11 10 9 8 7 6 5 4 3 2 1 0

Index = 17h Index = 16h

The Window Stop X value to be written is calculated as follows:

Wx = desired display screen x position V alues from 0000 (hex) to 0fff (hex) may be written into the Window Stop X register. The Window Stop Y value to be written is calculated as follows:

Wy = desired display screen y position V alues from 0000 (hex) to 0fff (hex) may be written into the Window Stop Y register. The values wirtten into the Window Stop X and Y registers should be relative to the first displayed pixel on

the screen; i.e. (0,0). Note that the Window Stop location specified is the last location inside of the window. For the cross hair

cursor or auxiliary window to be displayed, the Window Start registers must specify a point on the active display.

E–6

Cursor Color 0, 1 RGB Registers

These registers are used to specify the two colors for the hardware cursor (see 2.5). They are not initialized and may be written to or read from by the MPU at any time. Note that there are 6 registers total, three for each color. The register format for both the Cursor color 0 and Cursor color 1 registers is shown below.

T able J–11.

Cursor Color RED

Data bit D7 D6 D5 D4 D3 D2 D1 D0 Red Value 7 6 5 4 3 2 1 0

Index = 23h and 26h

T able J–12.

Cursor Color GREEN

Data bit D7 D6 D5 D4 D3 D2 D1 D0 Green

V alue

7 6 5 4 3 2 1 0

Index = 24h and 27h

T able J–13.

Cursor Color BLUE

Data bit D7 D6 D5 D4 D3 D2 D1 D0 Blue V al-

V alues 00 (hex) to FF (hex) may be written into the Cursor Color registers.

7 6 5 4 3 2 1 0

Index = 25h and 28h

E–7

Cursor RAM Address (LS, MS) Register

These registers are used to specify the address of where to write or read sprite cursor data from. The linear addressing scheme is depicted in Figure 4 of section 2.5.1. The Cursor RAM register is made up of the Cursor RAM LS (CRLS) and the Cursor RAM MS (CRMS). They are not initialized and may be written to by the MPU at any time.

CRLSL and CRMS are cascaded to form a 10–bit Cursor RAM Address register. Bits D2–D7 of CRMS are always a logical zero.

T able J–14.

Cursor RAM MS Address Cursor RAM LS Address

(CRMS) (CRLS)

Data bit D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 Address 0 0 0 0 0 0 9 8 7 6 5 4 3 2 1 0

Index = 09h Index = 08h

Index = 09 (hex) Index = 08 (hex)

V alues from 0000 (hex) to 03FF (hex) may be written into the Cursor RAM Address register. Note that when the cursor RAM address is to be written, both registers must be written with the Cursor RAM

LS Address being the first.

Cursor RAM Data Register

This register is used to read and write the contents of the sprite cursor locations whose address is specified in the Cursor RAM Address registers. The data read from or written to this register will contain 4 pixels of information, 2 bit planes per cursor pixel (see Figure 4 & section 2.5.1). The register is not initialized and may be written to or read from by the MPU at any time. The Sprite cursor data format is shown below.

T able J–15.

Cursor RAM Data

Data bit D7 D6 D5 D4 D3 D2 D1 D0 Data P1

Index = 0Ah

V alues from 00 (hex) to 3F (hex) may be written into the Cursor RAM Data register.

E–8

Auxiliary Control Register

Self or Externally Clocked timing for the Enabl

Function Bit. See the equation in Section

The Auxiliary Control register is used to control various functions of VIEWPOINT including the Auxiliary Windowing function and Horizontal zooming. It can be accessed by MPU at anytime. Bit 7 of Auxiliary Control register corresponds to data bus bit 7. Index = 29 (hex).

Bit Name

ARC7 0: default Horizontal Zoom Control. See Section 2.8.

ACR6 0: default Horizontal Zoom Control. See Section 2.8.

ACR5 0: default Horizontal Zoom Control. See Section 2.8.

ACR4 X Reserved

ACR3 0: Externally clocked Frame Buffer Clocking Select. Used to select

1: Self clocked (default)

ACR2 0: PSEL disable (default) Windowing Function Select. Port Select En-

1: PSEL enable

ACR1 0: Window disable (default) Windowing Function Select. Auxiliary Window

1: Window enable

ACR0 0: True function Windowing Function Select. Complementary

1: Complement (default)

Values Description

Frame Buffer interface. See Section 2.3.2.

able. See equation in Section 2.6.1.

e. See the equation in Section 2.6.1.

2.6.1.

E–9

Color Key Control Register

able the direct color BLUE field comparison

disable the direct color GREEN field compari

able the direct color RED field comparison

disable the direct color Overlay field compari

The Color Key Control register is used to control the operation of the Color Key Switching function (See section 2.6.2) It can be accessed by MPU at anytime. Bit 7 of Color Key Control register corresponds to data bus bit 7. Index = 38 (hex).

Bit Name

CKC7 X Reserved

CKC6 X Reserved

CKC5 X Reserved

CKC4 0: True function Color Key Function Select. Complementary

1: Complement (default)

CKC3 0: Disable compare (default) BLUE Compare Enable. Used to enable dis-

1: Enable comparison

CKC2 0: Disable compare (default) GREEN Compare Enable. Used to enable

1: Enable comparison

CKC1 0: Disable compare (default) RED Compare Enable. Used to enable dis-

1: Enable comparison

CKC0 0: Disable compare (default) Overlay Compare Enable. Used to enable

1: Enable comparison

Values Description

unction bit. See the equation in Section 2.6.2.

See the equation in Section 2.6.2.

son. See the equation in Section 2.6.2.

See the equation in Section 2.6.2.

son. See the equation in Section 2.6.2.

E–10

Color Key (Red, Green, Blue, Overlay) Low and High Registers

These registers are used to specify the color comparison ranges for the four Direct Color data fields when performing color key switching. A Low and a High register are provided for each of the four data fields to facilitate the range comparison. See section 2.6 and 2.6.2 for more details on their useage. All four Low registers are initiallized with 01 (hex), while all four High registers are initiallized with FF (hex). The registers may be written to or read from by the MPU at any time. Note that there are 8 registers total, two for each color. The register format for both Low and High registers is shown below.

T able J–16.

Color Key Low

Data bit D7 D6 D5 D4 D3 D2 D1 D0 Low Value 7 6 5 4 3 2 1 0

Index = 30h, 32h, 34h, 36h

T able J–17.

Color Key High

Data bit D7 D6 D5 D4 D3 D2 D1 D0 High V al-

7 6 5 4 3 2 1 0

Index = 31h, 33h, 35h, 37h

V alues 00 (hex) to FF (hex) may be written into the 4 Color Key Low and 4 Color Key High registers.

E–11

Overscan Color RGB Registers

These registers are used to specify the color for the overscan function. This function can be used to create custom screen borders (see 2.7). They are not initialized and maybe written to or read from by the MPU at any time. The register format for both the Overscan color registers is shown below.

T able J–18.

Overscan Color RED

Data bit D7 D6 D5 D4 D3 D2 D1 D0 RED Val-

Data bit D7 D6 D5 D4 D3 D2 D1 D0 GREEN

V alue

7 6 5 4 3 2 1 0

Index = 20h

T able J–19. Overscan Color GREEN

7 6 5 4 3 2 1 0

Index = 21h

T able J–20.

Overscan Color BLUE

Data bit D7 D6 D5 D4 D3 D2 D1 D0 BLUE Val-

V alues 00 (hex) to FF (hex) may be written into the Overscan Color registers.

E–12

7 6 5 4 3 2 1 0

Index = 22h

CRC LSB and MSB Registers

These registers are used to read the result of the 16–bit CRC calculation (see section 2.9). They are not initialized and may be read from by the MPU at any time. One must note, however, that they are only updated on the rising edge of the second HSYNC during vertical retrace.

CRCLSB and CRCMSB are cascaded to form a 16–bit CRC calculation remainder.

T able J–21.

CRCMSB CRCLSB

Data bit D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 CRC re-

mainder

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Index = 3Dh Index = 3Ch

CRC Control Register

This write only register is used to specify which of the 24 DAC data lines the 16–bit CRC should be calculated on (see section 2.9). The register is not initialized and maybe written to by the MPU at any time. The CRC Control register data format is shown below.

T able J–22.

CRC Control Register

Data bit D7 D6 D5 D4 D3 D2 D1 D0 Select

Data

V alues from 00 (hex) to 23 (hex) may be written into the CRC Control register.

0 0 0 4 3 2 1 0

Index = 3Eh

E–13

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TEXAS INSTRUMENTS TVP3010 Technical data

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