TEXAS INSTRUMENTS TVP3010 Technical data

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TVP3010

Data Manual

Video Interface Palette

SLAS082

September 1994

IMPORTANT NOTICE

Texas Instruments Incorporated (TI) reserves the right to make changes to its
products or to discontinue any semiconductor product or service without notice,
and advises its customers to obtain the latest version of relevant information to
verify, before placing orders, that the information being relied on is current.

TI warrants performance of its semiconductor products and related software to
current specifications in accordance with TI’s standard warranty. Testing and
other quality control techniques are utilized to the extent TI deems necessary to
support this warranty. Specific testing of all parameters of each device is not
necessarily performed, except those mandated by government requirements.

Please be aware that TI products are not intended for use in life-support
appliances, devices, or systems. Use of TI product in such applications requires
the written approval of the appropriate TI officer. Certain applications using
semiconductor devices may involve potential risks of personal injury, property
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TI assumes no liability for applications assistance, customer product design,
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Nor does TI warrant or represent that any license, either express or implied, is
granted under any patent right, copyright, mask work right, or other intellectual
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in which such semiconductor products or services might be or are used.

Copyright

SLAS082, December 1993

 1993, Texas Instruments Incorporated

Printed in the U.S.A.

Contents

Section Title Page

1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Features 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Functional Block Diagram 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Terminal Assignments 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Ordering Information 1–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Terminal Functions 1–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Detailed Description 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 MPU Interface 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Color Palette 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1 Writing to Color-Palette RAM 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.2 Reading From Color-Palette RAM 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.3 Palette-Page Register 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.4 Read Masking 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Clock Selection and Output-Clock (SCLK, RCLK, and VCLK) Generation 2–5. . . .

2.3.1 RCLK, SCLK, VCLK 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.3.2 Frame-Buffer Clocking: Self- or Externally Clocked 2–7. . . . . . . . . . . . . . . . . .

2.4 Multiplexing Scheme 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.1 Little-Endian and Big-Endian Data Format 2–11. . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.2 VGA Pass-Through Mode 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.3 Pseudo-Color Mode 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.4 Direct-Color Mode 2–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.5 True-Color Mode 2–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4.6 Multiplex-Control Registers 2–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 On-Chip Cursor 2–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.1 Cursor RAM 2–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.2 Two-Color 64 × 64 Cursor 2–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.3 64 × 64 Cursor Positioning 2–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.4 Crosshair Cursor 2–25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.5 Dual-Cursor Positioning 2–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 Auxiliary Window, Port Select, and Color-Key Switching 2–27. . . . . . . . . . . . . . . . . . . .

2.6.1 Windowing Control 2–28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.2 Color-Key-Switching Control 2–29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 Overscan 2–30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8 Horizontal Zooming 2–31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9 Test Functions 2–32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9.1 16-Bit CRC 2–32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9.2 Sense Comparator Output and Test Register 2–32. . . . . . . . . . . . . . . . . . . . . . .

2.9.3 Identification Code 2–33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iii

Contents (Continued)

Section Title Page

2.10 MUXOUT [SENSE] Output 2–33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 1 Reset 2–33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.1 Power-On Reset 2–33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.2 Software Reset 2–33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.12 Frame-Buffer Interface 2–33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.13 Analog Output Specifications 2–34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.14 Video Control: Horizontal Sync, Vertical Sync, and Blank 2–36. . . . . . . . . . . . . . . . . .

2.15 Split Shift-Register-T ransfer VRAMs 2–36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16 Control-Register Definitions 2–37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.1 Configuration Register 2–37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.2 General-Control Register 2–38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.3 Cursor-Control Register 2–39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.4 Cursor-Position X and Y Registers 2–40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.5 Sprite-Origin X and Y Registers 2–41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.6 Window-Start X and Y Registers 2–42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.7 Window-Stop X and Y Registers 2–43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.8 Cursor-Color 0, 1 RGB Registers 2–44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.9 Cursor-RAM Address Register 2–45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.10 Cursor-RAM Data Register 2–45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.11 Auxiliary Control Register 2–46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.12 Color-Key-Control Register 2–46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.13 Color-Key (Red, Green, Blue, Overlay) Low and High Registers 2–47. . . .

2.16.14 Overscan-Color RGB Registers 2–48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.15 CRC LSB and MSB Registers 2–49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.16.16 CRC-Control Register 2–49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Electrical Characteristics 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range 3–1. . . .

3.2 Recommended Operating Conditions 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Electrical Characteristics 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Operating Characteristics 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 Timing Requirements 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6 Switching Characteristics 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.7 Timing Diagrams 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Appendix A PC Board Layout Considerations A–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Appendix B RCLK Frequency < VCLK Frequency B–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Appendix C Little-Endian and Big-Endian Data Formats C–1. . . . . . . . . . . . . . . . . . . . . . .

Appendix D Examples: Register Settings D–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Appendix E Mechanical Data E–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iv

List of Illustrations

Figure Title Page

1–1 Functional Block Diagram 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–2 Terminal Assignments 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–1 Dot Clock/VCLK/RCLK/SCLK Relationship 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 SCLK/VCLK Control Timing

(SSRT Disabled, RCLK/SCLK Frequency = VCLK Frequency) 2–9. . . . . . . . . . . . . . . .

2–3 SCLK/VCLK Control Timing

(SSRT Enabled, RCLK/SCLK Frequency = VCLK Frequency) 2–10. . . . . . . . . . . . . . . . .

2–4 SCLK/VCLK Control Timing

(SSRT Disabled, RCLK/SCLK Frequency = 4 x VCLK Frequency) 2–10. . . . . . . . . . . . .

2–5 SCLK/VCLK Control Timing

(SSRT Enabled, RCLK/SCLK Frequency = 4 x VCLK Frequency) 2–11. . . . . . . . . . . . .

2–6 Cursor-RAM Organization 2–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–7 Common Sprite-Origin Settings 2–25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–8 Dual-Cursor Positioning 2–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–9 One Possible Custom Cursor Creation 2–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–10 VGA in the Auxiliary Window 2–29. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–11 Multiple VGA Windows Using Port Select (PSEL) 2–29. . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–12 Overscan 2–31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–13 Equivalent Circuit of the Current Output (IOG) 2–34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–14 Composite Video Output (With 7.5 IRE, 8-Bit Output) 2–35. . . . . . . . . . . . . . . . . . . . . . . .

2–15 Composite Video Output (With 0 IRE, 8-Bit Output) 2–35. . . . . . . . . . . . . . . . . . . . . . . . . .

2–16 Split Shift-Register-Transfer Timing 2–36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1 MPU Interface Timing 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 Video Input/Output Timing 3–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–3 SFLAG Timing (When SSRT Function is Enabled) 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . .

A–1 Typical Connection Diagram and Parts A–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A–2 Typical Component Placement With Split-Power Plane A–4. . . . . . . . . . . . . . . . . . . . . . .

B–1 VCLK and SCLK Phase Relationship (Case 1) B–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

B–2 VCLK and SCLK Phase Relationship (Case 2) B–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C–1 Little-Endian and Big-Endian Mapping of 8-Bit/Pixel Pseudo-Color Data in

Memory to Monitor Screen C–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

v

List of Tables

Table Title Page

2–1 Direct Register Map 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 Indirect Register Map (Extended Registers) 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–3 Allocation of Palette-Page Register Bits 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–4 Input-Clock-Selection Register 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–5 Output-Clock-Selection Register Format 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–6 Multiplex Mode and Bus-Width Selection 2–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–7 Pseudo-Color Mode Pixel-Latching Sequence 2–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–8 Direct-Color Mode Pixel-Latching Sequence (Little-Endian) 2–19. . . . . . . . . . . . . . . . . . .

2–9 Direct-Color Mode Pixel-Latching Sequence (Big-Endian) 2–20. . . . . . . . . . . . . . . . . . . .

2–10 True-Color Mode Pixel-Latching Sequence (Little-Endian) 2–21. . . . . . . . . . . . . . . . . . . .

2–11 True-Color Mode Pixel-Latching Sequence (Big-Endian) 2–22. . . . . . . . . . . . . . . . . . . . . .

2–12 Configuration Register 2–37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–13 General-Control Register 2–38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–14 Cursor-Control Register 2–39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D–1 8-Bit/Pixel Pseudo-Color (32-Bit Pixel Bus, 4:1) Self-Clocked, LCLK

and RCLK Enabled D–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D–2 24-Bit True Color (32-Bit Pixel Bus, 1:1) Self-Clocked, RCLK = LCLK Internal D–1. . .

D–3 24-Bit Direct Color (32-Bit Pixel Bus, 1:1) Self-Clocked, No Overlay D–1. . . . . . . . . . . .

D–4 24-Bit Direct Color (32-Bit Pixel Bus, 1:1) Self-Clocked,

Overlay PSEL Switched D–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D–5 24-Bit Direct Color (32-Bit Pixel Bus, 1:1) Externally-Clocked, VGA PSEL Switched

Overlay Auxiliary Window Switched D–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

D–6 16-Bit Direct Color (32-Bit Pixel Bus, 2:1) Self-Clocked,

Overlay Auxiliary Window Switched D–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vi

1 Introduction

The TVP3010 palette is an advanced Video Interface Palette (VIP) from Texas Instruments implemented
in the EPIC 0.8-micron CMOS process. Maximum flexibility is provided by the pixel multiplexing scheme.
The scheme accommodates 64-, 32-, 16-, 8-, and 4-bit pixel buses without any circuit modification. This
enables the system to be easily reconfigured for varying amounts of available video RAM. The device
supports selection of little- or big-endian data format for the pixel-bus/frame-buffer interface. Data can be
split into 1, 2, 4, or 8 bit planes for pseudo-color mode or split into 12-, 16- or 24-bit true-color and direct-color
modes. For the 24-bit direct color modes, an 8-bit overlay plane is available. The 16-bit direct- and true-color
modes can be configured to IBM XGA
An additional 12-bit mode (4, 4, 4, 4) is supported with 4 bits for each color and overlay. An on-chip, IBM
XGA-compatible hardware cursor is incorporated so that further increases in graphics system performance
are possible. The device is also software compatible with the IMSG176/8 and Bt476/8 color palettes.

An internal frequency doubler is incorporated, allowing convenient and cost-effective clock source
alternatives to be utilized. An auxiliary windowing function and a pixel-port-select function are provided so
that overlay or VGA graphics can be displayed on top of direct color inside or outside a specified auxiliary
window. Color-keyed switching of direct color and overlay is also supported.

Clocking is provided through one of five TTL inputs, CLK0–CLK4, and is software selectable. Additionally ,
CLK1/CLK2 and CLK3/CLK4 can be selected as differential ECL clock sources. The video, shift clock, and
reference clock outputs provide a software-selected divide ratio of the chosen clock input. The reference
clock can optionally be provided as an output on CLK3, and a data latch clock can optionally be input on
CLK4.

The TVP3010 has three 256-by-8 color lookup tables with triple 8-bit video digital-to-analog converters
(DACs) capable of directly driving a doubly terminated 75-Ω line. The lookup tables are designed with a
dual-ported RAM architecture that enables ultra-high speed operation. Sync generation is incorporated on
the green output channel. Horizontal sync and vertical sync are fed through the device and optionally
inverted to indicate screen resolution to the monitor. A palette-page register is used to provide the additional
bits of palette address when 1, 2, or 4 bit planes are used. This allows the screen colors to be changed with
only one microprocessor interface unit (MPU) write cycle.

The device features a separate VGA bus that allows data from the feature connector of most VGA-supported
personal computers to be fed directly into the palette without the need for external data multiplexing. This
allows a replacement graphics board to remain downwards compatible by utilizing the existing graphics
circuitry often located on the motherboard.

The TVP3010 VIP is highly system integrated. It can be connected to the serial port of VRAM devices without
external buffer logic and connected to many graphics engines directly. The split shift-register transfer
function, which is supported by VRAM, is also supported by the TVP3010.

The system-integration concept is carried to manufacturing test and field diagnosis. To support these,
several highly integrated test functions have been designed to enable simplified testing of the palette, the
graphics board, and the graphics system.

The 32-bit TVP3010 is pin compatible with the TLC3407X VIP, allowing convenient performance upgrades
when using devices in the TI Video Interface Palette family.

The TVP3010 includes circuits that are patented and circuit designs that have
patents pending.



(5, 6, 5), T ARGA (5, 5, 5, 1), or (6, 6, 4) as another existing format.

NOTE:

EPIC is a trademark of Texas Instruments Incorporated.
XGA is a registered trademark of IBM.
TARGA is a registered trademark of Truevision Incorporated.

1–1

1.1 Features

• Second-Generation Video Interface Palette

• Supports System Resolutions of:

– 1600 × 1280 × 1, 2, 4, 8, 16 Bits/Pixel @ 60-Hz Refresh Rate
– 1280 × 1024 × 1, 2, 4, 8, 16 Bits/Pixel @ 60-Hz and 72-Hz Refresh Rate
– 1024 × 768 × 1, 2, 4, 8, 16, 24 Bits/Pixel @ 60-Hz and 72-Hz Refresh Rate
– And lower resolutions

• Direct-Color Modes:
– 24-Bit/Pixel with 8-Bit Overlay

– 16-Bit/Pixel (5, 6, 5) XGA Configuration
– 16-Bit/Pixel (6, 6, 4) Configuration
– 15-Bit/Pixel With 1 Bit Overlay (5, 5, 5, 1) TARGA Configuration
– 12-Bit/Pixel With 4 Bit Overlay (4, 4, 4, 4)

• True-Color Modes:
– 24-Bit/Pixel With Gamma Correction

– 16-Bit/Pixel (5, 6, 5) XGA Configuration With Gamma Correction
– 16-Bit/Pixel (6, 6, 4) Configuration with Gamma Correction
– 15-Bit/Pixel (5, 5, 5) TARGA Configuration With Gamma Correction
– 12-Bit/Pixel (4, 4, 4) With Gamma Correction

• RCLK/SCLK/LCLK Data Latching Mechanism Allows Flexible Control of VRAM Timing

• Direct Interfacing to Video RAM

• Support for Split Shift-Register Transfers

• 64-Bit-Wide Pixel Bus

• On-Chip Hardware Cursor:

– 64 × 64 × 2 Cursor (XGA Functionally Compatible)
– Full-Window Crosshair
– Dual-Cursor Mode

• 85-,110-,135-, and 170-MHz Versions

• Supports Overscan for Creation of Custom Screen Borders

• Versatile Pixel Bus Interface Supports Little- and Big-Endian Data Formats

• Windowed Overlay and VGA Capability

• Color-Keyed Switching of Direct Color and Overlay

• On-Chip Clock Selection

• Internal Frequency Doubler

• Triple 8-Bit D/A Converters

• Analog Output Comparators

• Triple 256 × 8 Color Palette RAMs

• RS-343A Compatible Outputs

• Direct VGA Pass-Through Capability

• Palette-Page Register

• Horizontal Zooming Capability

• Software Downward Compatible With IMSG176/8 and Bt476/8

• Directly Interfaces to Graphics Processors

• EPIC 0.8-µm CMOS Process

1–2

1.2 Functional Block Diagram

True-Color

32 32

P(0–31)

VGA(0–7)

D(0–7)

RS(0–2)

WR

RD

32

8

3

Input

Latch

Input

Latch

MPU

Registers

and

Control

Logic

88

32

Multiplexer

Pseudo-

Color

MUX

1:1
2:1
4:1

8:1
16:1
32:1

Clock Select

2
4
8

and

Control

8–8–8
6–6–4
5–6–5
5–5–5
4–4–4

2

24
16
16
15

12

Read

8

Mask

Frequency

Doubler

12-24

Stuffing

Logic

Page

8 8

Reg

8 24

Color-Key

Switch

24 24

8
8

8
8

8
8

64 × 64

Cursor

Control

RAM

and

Direct-Color

Pipeline Delay

256 × 8

Red

8

RAM

256 × 8

Green

8

RAM

256 × 8

Blue

8

RAM

1 × 24

Cursor

Color 0

1 × 24

Cursor

Color 1

1 × 24

Overscan

Auxiliary Window

V

ref

1.235 V

24

8

8

8

Output

24

24

24

2

and

Port Select

REF

MUX

FS ADJUST

DAC

8

DAC

8

DAC

8

Test Function

and

Sense Comparator

Video-Signal

Control

COMP

IOR

IOG

IOB

MUXOUT [SENSE]
HSYNCOUT

VSYNCOUT

CLK0

SFLAG

CLK1/CLK2

VCLK

SCLK

CLK4 [LCLK]

CLK3 [RCLK]

8/6 [OVS]

Figure 1–1. Functional Block Diagram

RS3 [PSEL]

VSYNC

HSYNC

VGABL

SYSBL

1–3

1.3 Terminal Assignments

P19

P18

P20

P21

P22

P23

P24

10 9 8 7 611 5

P17

12

P16

13

P15

14

P14

15

P13

16

P12

17

P11

18

P10

19

P9

20
21

P8

22

P7

23

P6

24

P5

25

P4

26

P3

27

P2

28

P1

29

P0

30

WR

31

RD

32

RS0

33

34 35

37 38 39 40

36

P27

P26

3214

P28

84 83

P25

41 42 43 44 45

P30

P29

82 81 80 79

46 47 48 49

P31

DD

DV

GND

SCLK

78 77 76 75

VCLK

CLK0

CLK1COMP

50 51 52 53

CLK2

74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54

CLK3[RCLK]

[LCLK]

CLK4
VGA7
VGA6
VGA5
VGA4
VGA3
VGA2
VGA1
VGA0
8/6[OVS]
MUXOUT

[SENSE]
SFLAG
VGABL
SYSBL
VSYNC
HSYNC
AV

DD

GND
AV

DD

GND

1–4

RS1

D0D1D2D3D4

RS2

RS3[PSEL]

D7

D5

D6

DD

GND

DV

IOR

IOG

VSYNCOUT

HSYNCOUT

IOB

Figure 1–2. Terminal Assignments

REF

FS ADJUST

1.4 Ordering Information

I/O

DESCRIPTION

TVP3010 – XXX XX

Pixel Clock Frequency Indicator

MUST CONTAIN THREE CHARACTERS:

–85: 85-MHz pixel clock

–110: 110-MHz pixel clock
–135: 135-MHz pixel clock
–170: 170-MHz pixel clock

Package

MUST CONTAIN TWO LETTERS:

FN: square plastic J-leaded chip carrier (formed leads)

1.5 Terminal Functions

TERMINAL

NAME NO.

AV

DD

CLK0 77 I

CLK1, CLK2 75, 76 I

CLK3[RCLK] 74 I/O Dot clock 3 TTL input or reference clock output. When configured as

CLK4[LCLK] 73 I Dot clock 4 TTL input or pixel-port latch clock. This terminal can be

COMP 52 I Compensation. COMP provides compensation for the internal

DV

DD

D(0–7) 36–43 I/O

FS ADJUST 51 I Full-scale adjustment. A resistor connected between this terminal and

NOTE: All unused inputs should be tied to a logic level and not be allowed to float.

55, 57 Analog power. All AVDD terminals must be connected.

(TTL

compatible)

(TTL/ECL

compatible)

45, 81 Digital power. All DVDD terminals must be connected.

(TTL

compatible)

Dot clock 0 input. CLK0 can be selected to drive the dot clock at
frequencies up to 140 MHz. When VGA mode is active, the default clock
source is CLK0. The maximum frequency in VGA mode is 85 MHz.

Dual-mode dot clock input. These inputs are essentially ECL­compatible inputs, but two TTL clocks may be used on the CLK1 and
CLK2 if so selected in the input clock select register. These inputs may
be selected as the dot clock up to the device limit while in the ECL mode
or up to 140 MHz in the TTL mode.

CLK3, this terminal is similar to CLK0 and can be selected to drive the
dot clock at frequencies up to 140 MHz. When configured as RCLK, this
terminal outputs the reference clock signal, which is similar to the SCLK
signal but not gated off during blank. This signal can be used for
pixel-port timing reference or other system synchronization. The
terminal defaults to CLK3 after reset.

configured to drive dot clock frequencies up to 140 MHz, or it can be
configured as a latch clock input to latch pixel-port input data. This
terminal defaults to CLK4 after reset, and LCLK is internally connected
to RCLK to latch pixel-port data.

reference amplifier . A 0.1-µF ceramic capacitor is required between this
terminal and A VDD. The COMP capacitor must be as close to the device
as possible to avoid noise pick up.

MPU interface data bus. These terminals are used to transfer data in
and out of the register map and palette/overlay RAM.

ground controls the full-scale range of the DACs.

1–5

1.5 Terminal Functions (Continued)

I/O

DESCRIPTION

TERMINAL

NAME NO.

GND 44, 54, 56, 80 Ground. All GND terminals must be connected. The GNDs are

HSYNCOUT 46 O

(TTL

compatible)

IOR, IOG, IOB 48, 49, 50 O Analog current outputs. These outputs can drive a 37.5-Ω load

MUXOUT [SENSE] 63 O

(TTL

compatible)

P(0–31) 1–29, 82–84 I

(TTL

compatible)

REF 53 Voltage reference for DACs. An internal voltage reference of

RD 31 I

(TTL

compatible)

RS(0–2) 32–34 I

(TTL

compatible)

RS3, [PSEL] 35 I

(TTL

compatible)

SCLK 79 O

(TTL

compatible)

NOTE: All unused inputs should be tied to a logic level and not be allowed to float.

connected internally .
Horizontal sync output after pipeline delay . For system mode the

output can be programmed, but for the VGA mode the output
carries the same polarity as the input.

directly (doubly terminated 75-Ω line), thus eliminating the
requirement for any external buffering.

Multiplexer output control or DAC comparator output signal.
When this terminal is configured as a multiplexer output control,
it is software programmable through the configuration register.
When the multiplexer control register is set to VGA mode, this
output terminal and corresponding configuration register bit are
set low to indicate to external devices that VGA pass through
mode is being used. Alternatively, this terminal can be configured
as the DAC comparator output. In this case, the terminal is low
if one or more of the DAC output analog levels is above the
internal comparator reference of 350 mV " 50 mV.

Pixel input port. The port can be used in various modes as shown
in the multiplexer control register. All the unused terminals need
to be tied to GND.

nominally 1.235 V is provided, which requires an external 0.1-µF
ceramic capacitor between REF and analog GND. However, the
internal reference voltage can be overdriven by an externally
supplied reference voltage. Typical connection is shown in
Appendix A.

Read strobe input. A logic 0 on this terminal initiates a read from
the register map. Reads are performed asynchronously and are
initiated on the low-going edge of RD

Register-select inputs. These terminals specify the location in the
register map that is to be accessed (see Table 2–1).

Register-select input or port-select input. When configured as the
RS3 input, this terminal has no effect. When configured as the
port select input, this terminal allows the creation of VGA or
overlay windows in a direct color background on a pixel-by-pixel
basis.

Shift-clock output. SCLK is selected as a division of the dot clock
input. The output signals are gated off during blank, although
SCLK is still used internally to synchronize with the activation of
blank

.

(see Figure 3–1).

1–6

1.5 Terminal Functions (Continued)

I/O

DESCRIPTION

TERMINAL

NAME NO.

SFLAG 62 I

SYSBL 60 I

HSYNC,
VSYNC

VCLK 78 O

VGABL 61 I

VGA(0–7) 65–72 I

VSYNCOUT 47 O

WR 30 I

8/6 [OVS] 64 I

NOTE: All unused inputs should be tied to a logic level and not be allowed to float.

58, 59 I

(TTL

compatible)

(TTL

compatible)

(TTL

compatible)

(TTL

compatible)

(TTL

capability)

(TTL

capability)

(TTL

capability)

(TTL

capability)

(TTL

capability)

Split shift-register-transfer flag. The TVP3010 VIP detects a low­to-high transition on this terminal during a blank sequence and
immediately generates an SCLK pulse. This early SCLK pulse
replaces the first SCLK pulse in the normal sequence.

System blank input. SYSBL is active (low).

Horizontal and vertical sync inputs. These signals are used to
generate the sync level on the green current output. They are active
(low) inputs, but the HSYNCOUT and VSYNCOUT outputs can be
programmed through general control register .

Video clock output. VCLK is the user-programmable output for
synchronization to graphics processor.

VGA blank input. VGABL is active (low).

VGA pass-through bus. These buses can be selected as the pixel bus
for VGA mode, but it does not allow for any multiplexing.

Vertical sync output after pipeline delay . For system mode, the output
can be programmed but for the VGA mode, the output carries the
same polarity as the input.

Write strobe input. A logic 0 on this terminal initiates a write to the
register map. As with RD
initiated on the low-going edge of WR

DAC resolution selection or overscan input. This terminal is used to
select the data bus width (8 or 6 bits) for the DAC and is essentially
provided in order to maintain compatibility with the IMSG176. When
this terminal is a logical 1, 8-bit bus transfers are used with D7 the MSB
and D0 the LSB. For 6-bit bus operation, while the color palette still has
the 8-bit information D5 shifts to the bit 7 position with D0 shifted to the
bit 2 position and the two LSBs are filled with zeros at the output
multiplexer to DAC. The palette holding register zeroes the two MSBs
when it is read in the 6-bit mode. The terminal can also be configured
to function as the overscan input facilitating the creation of custom
screen borders. This terminal defaults to 8/6

, write transfers are asynchronous and

, (see Figure 3–1).

after reset.

1–7

1–8

2 Detailed Description

The 32-bit TVP3010 is pin compatible with the TLC34076 but offers advanced features. To facilitate the
enhanced functionality , some terminals have dual functions. The dual-function terminals are controlled by
the configuration register discussed in Section 2.16.1. At reset, all terminals default to the TLC34076
terminal functions.

2.1 MPU Interface

The processor interface is controlled via read and write strobes (RD, WR), three register-select terminals
[RS(0–2)], and the 8/6
path to the color-palette RAM and is provided in order to maintain compatibility with the IMSG176. Since

[OVS] terminal is a dual-function terminal, two bits are provided in the configuration register to control

the 8/6
this function. Configuration register bit 1 determines whether the 8/6
If configuration register bit 1 is set to logic 0 (default), then 8/6 operation is controlled by the terminal. With

held low, data on the lowest six bits of the data bus are internally shifted up by two bits to occupy the

8/6
upper six bits at the output multiplexer and the bottom two bits are then zeroed. This operation is carried
out in order to utilize the maximum range of the DACs.

The direct register map is shown in Table 2–1. Extended registers can be accessed through the index
register. The index register map is shown in Table 2–2. In general, the index register must first be loaded
with the target address value. Successive reads or writes from and to the data register then access the target
location. The MPU interface operates asynchronously, with data transfers being synchronized by internal
logic.

RS3 is a don’t care for register addressing but is used as the PSEL input. See
Section 2.6.

RS2 RS1 RS0 REGISTER ADDRESSED BY MPU R/W DEFAULT (HEX)

0 0 0 Palette-Address Register – W rite Mode R/W XX
0 0 1 Color-Palette Holding Register R/W XX
0 1 0 Pixel Read Mask R/W FF
0 1 1 Palette-Address Register – Read Mode R/W XX
1 0 0 Reserved XX
1 0 1 Reserved XX
1 1 0 Index Register R/W XX
1 1 1 Data Register R/W XX

-select terminal. The 8/6 terminal is used to select between an 8- or 6-bit-wide data

[OVS] terminal operates as 8/6 or OVS.

NOTE:

T able 2–1. Direct Register Map

T able 2–2. Indirect Register Map (Extended Registers)

INDEX REGISTER

(HEX)

00 R/W 00 Cursor-Position X LSB
01 R/W 00 Cursor-Position X MSB
02 R/W 00 Cursor-Position Y LSB
03 R/W 00 Cursor-Position Y MSB

NOTE: Reserved registers should be avoided; otherwise, circuit behavior could deviate

from that specified. Reserved-undefined registers are nonexistent locations on
the register map.

R/W

DEFAULT

(HEX)

REGISTER ADDRESSED

BY INDEX REGISTER

2–1

T able 2–2. Indirect Register Map (Extended Registers) (Continued)

INDEX REGISTER

(HEX)

04 R/W 1F Sprite-Origin X
05 R/W 1F Sprite-Origin Y
06 R/W 00 Cursor-Control Register
07 Reserved
08 W XX Cursor-RAM Address LSB

09 W XX Cursor-RAM Address MSB
0A R/W XX Cursor-RAM Data
0B Reserved

0C–0F Reserved-Undefined

10 R/W XX Window-Start X LSB

11 R/W XX Window-Start X MSB

12 R/W XX Window-Stop X LSB

13 R/W XX Window-Stop X MSB

14 R/W XX Window-Start Y LSB

15 R/W XX Window-Start Y MSB

16 R/W XX Window-Stop Y LSB

17 R/W XX Window-Stop Y MSB

18 R/W 80 Multiplexer-Control Register 1

19 R/W 98 Multiplexer-Control Register 2
1A R/W 00 Input-Clock-Selection Register
1B R/W 3E Output-Clock-Selection Register
1C R/W 00 Palette-Page Register
1D R/W 20 General-Control Register
1E R/W 00 Configuration Register

1F Reserved-Undefined

20 R/W XX Overscan Color Red

21 R/W XX Overscan Color Green

22 R/W XX Overscan Color Blue

23 R/W XX Cursor Color 0, Red

24 R/W XX Cursor Color 0, Green

25 R/W XX Cursor Color 0, Blue

26 R/W XX Cursor Color 1, Red

27 R/W XX Cursor Color 1, Green

28 R/W XX Cursor Color 1, Blue

29 R/W 09 Auxiliary-Control Register

NOTE: Reserved registers should be avoided; otherwise, circuit behavior could deviate

from that specified. Reserved-undefined registers are nonexistent locations on
the register map.

R/W

DEFAULT

(HEX)

REGISTER ADDRESSED

BY INDEX REGISTER

2–2

T able 2–2. Indirect Register Map (Extended Registers) (Continued)

INDEX REGISTER

(HEX)

2A Reserved
2B Reserved
2C Reserved
2D Reserved
2E Reserved

2F Reserved

30 R/W XX Color-Key OL/VGA Low

31 R/W XX Color-Key OL/VGA High

32 R/W XX Color-Key Red Low

33 R/W XX Color-Key Red High

34 R/W XX Color-Key Green Low

35 R/W XX Color-Key Green High

36 R/W XX Color-Key Blue Low

37 R/W XX Color-Key Blue High

38 R/W 10 Color-Key Control Register

39 Reserved-Undefined
3A R/W 00 Sense Test Register
3B R XX Test Data Register
3C R XX CRC LSB
3D R XX CRC MSB
3E W XX CRC Control Register

3F R 10 ID Register
FF W XX Reset Register

NOTE: Reserved registers should be avoided; otherwise, circuit behavior could deviate

from that specified. Reserved-undefined registers are nonexistent locations on
the register map.

R/W

DEFAULT

(HEX)

REGISTER ADDRESSED

BY INDEX REGISTER

2.2 Color Palette

The color palette is addressed by an internal 8-bit address register for reading/writing data from/to the RAM.
This register is automatically incremented following a RAM transfer, allowing the entire palette to be
read/written with only one access of the address register. When the address register increments beyond
the last location in RAM, it is reset to the first location (address 0). All read and write accesses to the RAM
are asynchronous to SCLK, VCLK, and dot clock but performed within one dot clock. Therefore, they do not
cause any noticeable disturbance on the display .

The color RAM is 24 bits wide for each location and 8 bits wide for each color. Since the MPU access is eight
bits wide, the color data stored in the palette is eight bits even when the six-bit mode is chosen (8/6
If the six-bit mode is chosen, the two MSBs of color data in the palette have the values previously written.
However, if they are read back in the six-bit mode, the two MSBs are 0s to be compatible with IMSG176 and
Bt176. The output multiplexer shifts the six LSB bits to the six MSB positions and fills the two LSBs with 0s
after the color palette. The multiplexer then feeds the data to the DAC. The test register and the CRC
calculation both take data after the output multiplexer, enabling total system verification. The color-palette
access is described in the following two sections, and it is fully compatible with IMSG176/8 and Bt476/8.

= 0).

2–3

2.2.1 Writing to Color-Palette RAM

T o load the color palette, the MPU must first write to the address register (write mode) with the address where
the modification is to start. This is then followed by three successive writes to the palette holding register
with eight bits of red, green, and blue data. After the blue write cycle, the three bytes of color data are
concatenated into a 24-bit word that is then written to the RAM location specified by the address register.
The address register then increments to the next location, which the MPU may modify by simply writing
another sequence of red, green, and blue data. A block of color values in consecutive locations may be
written to by writing the start address and performing continuous red, green, and blue write cycles until the
entire block has been written.

2.2.2 Reading From Color-Palette RAM

Reading from the palette is performed by writing to the address register (read mode) with the location to be
read. This then initiates a transfer from the palette RAM into the holding register, followed by an increment
of the address register. Three successive MPU reads from the holding register produce red, green, and blue
color data (6 or 8 bits depending on the 8/6

mode) for the specified location. Following the blue read cycle,
the contents of the color-palette RAM at the address specified by the address register are copied into the
holding register and the address register is again incremented. As with writing to the palette, a block of color
values in consecutive locations may be read by writing the start address and performing continuous red,
green, and blue read cycles until the entire block has been read. Since the color-palette RAM is dual ported,
the RAM may be read during active display without disturbing the video.

2.2.3 Palette-Page Register

The palette-page register appears as an 8-bit register on the extended register map (see Section 2.1). Its
purpose is to provide high-speed color changing by removing the need for palette reloading. When using
1, 2, or 4 bit planes, the additional planes are provided from the page register. When using four bit planes,
the pixel inputs specify the lower four bits of the palette address with the upper four bits specified from the
page register. This gives the user the capability of selecting from 16 palette pages with only one chip access,
thus allowing all the screen colors to be changed at the line frequency . A bit-to-bit correspondence is used;
therefore, in the above configuration, page-register bits 7 through 4 map onto palette-address bits 7 through
4, respectively. This is illustrated in Table 2–3.

NOTE:

The additional bits from the page register are inserted after the read mask.
The palette-page register specifies the additional bit planes for the overlay field in

direct-color modes with less than 8 bits per pixel overlay .

T able 2–3. Allocation of Palette-Page Register Bits

NUMBER OF BIT PLANES MSB PALETTE-ADDRESS BITS LSB

8 M M M M M M M M
4 P7 P6 P5 P4 M M M M
2 P7 P6 P5 P4 P3 P2 M M

1 P7 P6 P5 P4 P3 P2 P1 M
Pn = n bit from page register
M = bit from pixel port

2.2.4 Read Masking

The read-mask register is an 8-bit register used to enable or disable a bit plane from addressing the
color-palette RAM in the pseudo-color modes. Each palette address bit is logically ANDed with the
corresponding bit from the read mask register before going to the palette-page register and addressing the
palette RAM.

In order to provide maximum flexibility to control palette data, the read mask operation is performed before
the addition of the page register bits. Therefore, care must be taken in those modes that have less than eight
bits per pixel of pseudo-color or overlay data. Be aware of the palette-page register settings in these modes.

2–4

2.3 Clock Selection and Output-Clock (SCLK, RCLK, and VCLK) Generation

The TVP3010 VIP provides a maximum of five clock inputs. One of them (CLK0) is dedicated as a TTL input.
The other four can be selected as either two differential ECL input or two extra TTL inputs. The TTL inputs
can be used for video rates up to 140 MHz. The dual-mode clock input (ECL/TTL) is primarily an ECL input
but can be used as TTL-compatible inputs if the input-clock-selection register is so programmed. The clock
source used at power up is CLK0; an alternative source can be selected by software during normal
operation. This chosen clock input can be used unmodified as the dot clock (representing pixel rate to the
monitor). Alternatively, if the input-clock-selection register is programmed to use the internal frequency
doubler, the chosen clock source is used as a reference for multiplication. The device also allows for user
programming of RCLK, SCLK and VCLK outputs (reference, shift and video clocks) by using the
output-clock-selection register. The input-clock- and output-clock-selection registers are shown in Tables
2–4 and 2–5 and are located in the indirect register map (see Table 2–2).

The ECL inputs can be used as a differential or single-ended inputs. If CLK1 or CLK3 is used as a
single-ended ECL input, CLK2 or CLK4 needs to be externally terminated to set the input common-mode
signal level. This can be done with a simple resistor divided, as is the case with fully differential ECL. Care
needs to be taken when choosing the resistor values to ensure that the dc level on CLK2 or CLK4 is in the
middle of the CLK1 or CLK3 ECL-input signal range.

2.3.1 RCLK, SCLK, VCLK

The TVP3010 VIP provides user-programmable reference clock (RCLK), shift clock (SCLK), and video
(VCLK) clock outputs that can be set as divisions of the dot clock. RCLK is a continuously running reference
clock and is not disabled during blank. RCLK can be selected as divisions of 1, 2, 4, 8, 16, 32 or 64 of the
dot clock (see Table 2–5). It is provided as a clock reference and is typically connected back to the LCLK
input to latch pixel-port data. Since pixel-port data is latched on the rising edge of LCLK, the RCLK frequency
must be set as a function of the desired multiplexing ratio (that depends on the pixel bus width and number
of bit planes). See Section 2.4 and Table 2–6.

SCLK is the same as RCLK but disabled during the blank active period. SCLK is designed to be used as
the shift clock to interface directly with the VRAM. If SCLK is not used, the output can be switched off and
held low to protect against VRAM lockup due to invalid SCLK frequencies. The detailed SCLK control timing
is discussed in Section 2.3.2 and illustrated in Figures 2–2 through 2–5.

VCLK is designed to be used as the timing reference by the graphics processor or other custom-designed
control logic to generate the graphics system control signals (SYSBL
selected as divisions of 1, 2, 4, 8, 16, 32, or 64 of the dot clock and can also be held at logic 1 (see T able 2–5).
The default setup is VCLK held at logic 1 since it is not used in VGA pass-through mode. Since these control
signals are sampled by VCLK, VCLK must be enabled for these to function properly (see Figures 2–2
through 2–5).

Even though RCLK/SCLK and VCLK can be selected independently, there is still a relationship between
the two as discussed below. Many system considerations have been carefully covered in their design,
leaving maximum freedom to the user.

Internally , RCLK, SCLK, and VCLK are generated from a common clock counter that is counted at the rising
edge of the dot clock. Therefore, when VCLK is enabled, it is naturally in phase with RCLK and SCLK as
shown in Figure 2–1.

Normally, the video control signal inputs HSYNC
VCLK when in a non-VGA mode. If the configuration register is programmed for opposite VCLK polarity,
these video control signals are latched on the rising edge of VCLK.

The internal clock counter is initialized any time the output-clock-selection register is written with 3F (hex).
This provides a simple mechanism to synchronize multiple palettes or system devices by providing a known
phase relationship for the various system clocks. It is left up to the user to provide some means of disabling
the dot clock input to the part while this reset is occurring if multiple parts are to be synchronized.

, VSYNC, and SYSBL are latched on the falling edge of

, HSYNC, and VSYNC). VCLK can be

2–5

The reset default divide ratio for RCLK is 64:1 with SCLK held at logic 0 and VCLK held at logic 1. When
choosing certain video timing parameters, exercise caution if the selected RCLK frequency is less than the
selected VCLK frequency . Refer to Appendix B for a more detailed discussion.

Dot Clock

(dot clock/4 as an example)

RCLK = SCLK

(dot clock/2 as an example)

VCLK

Figure 2–1. Dot Clock/VCLK/RCLK/SCLK Relationship

The input-clock-selection register is used to select the desired input clock source. T able 2–4 details how to
program the various options.

T able 2–4. Input-Clock-Selection Register

INPUT-CLOCK-SELECT REGISTER

†

CLK0 is chosen at reset as required for VGA pass-through.

NOTES: 1. Register bits 3 and 7 are don’t-care bits.

(HEX) (see Note 1)

00 Select CLK0 as TTL clock source
01 Select CLK1 as TTL clock source
02 Select CLK2 as TTL clock source
03 Select CLK3 as TTL clock source
04 Select CLK4 as TTL clock source
06 Select CLK3/CLK4 as ECL clock source up to 140 MHz
07 Select CLK1/CLK2 as ECL clock source up to device limit
10 Select CLK0 as doubled TTL clock source
11 Select CLK1 as doubled TTL clock source
12 Select CLK2 as doubled TTL clock source
13 Select CLK3 as doubled TTL clock source
14 Select CLK4 as doubled TTL clock source
16 Select CLK3/CLK4 as doubled ECL clock source
17 Select CLK1/CLK2 as doubled ECL clock source

2. Register bits 5 and 6 are reserved.

3. When the clocks are selected from one input clock source to another, a minimum of 30 ns is needed
before the new clocks are stabilized and running.

FUNCTION (see Note 2)

†

2–6

The output-clock-selection register is used to program the desired divided-down frequencies for the

FUNCTION

(

7)

reference/shift and video clocks.

Table 2–5. Output-Clock-Selection Register Format

OUTPUT-CLOCK-SELECTION-REGISTER BITS (see Note 4)

6 543210

0 0 0 x x x VCLK/1 output ratio
0 0 1 x x x VCLK/2 output ratio
0 1 0 x x x VCLK/4 output ration
0 1 1 x x x VCLK/8 output ratio
1 0 0 x x x VCLK/16 output ratio
1 0 1 x x x VCLK/32 output ratio
1 1 0 x x x VCLK/64 output ratio
1 1 1 x x x VCLK output held at logic 1
x x x 0 0 0 RCLK/1 output ratio (see Notes 4 and 7)
x x x 0 0 1 RCLK/2 output ratio (see Notes 4 and 7)
x x x 0 1 0 RCLK/4 output ratio (see Notes 4 and 7)
x x x 0 1 1 RCLK/8 output ratio (see Notes 4 and 7)
x x x 1 0 0 RCLK/16 output ratio (see Notes 4 and 7)
x x x 1 0 1 RCLK/32 output ratio (see Notes 4 and 7)

x x x 1 1 0 RCLK/64 output ratio (see Notes 4 and 7)
0 x x x 1 1 0 RCLK/64, SCLK output held at logic 0
0 x x x 1 1 1 RCLK, SCLK outputs held at logic 0
x 1 1 1 1 1 1 Clock counter reset (6)

†

These lines indicate the reset conditions as required for VGA pass-through.

NOTES: 4. Register bit 6 enables (logic 1) and disables (default – logic 0) the SCLK output buffer. Register

bit 7 is a don’t care bit.

5. When the clocks are selected from one mode to the other, a minimum of 30 ns is needed before
the new clocks are stabilized and running.

6. When the output-clock-selection register is written with 3F (hex), the clock counter is reset,
RCLK = SCLK = logic 0, and VCLK = logic 1.

7. SCLK is the same as RCLK except that it is disabled during blank. When the RCLK divide ratio is
chosen, this sets the SCLK ratio as well.

see Notes 4, 5, 6, and

†

†

2.3.2 Frame-Buffer Clocking: Self- or Externally Clocked

The TVP3010 VIP has two pixel-data latching modes, allowing for flexibility in the frame-buffer interface
timing. For the pixel port [P(0–31)], data is always latched on the rising edge of LCLK. If auxiliary-control
register (ACR) bit 3 is set to logic 1 (default), the internal circuitry is configured for self-clocked mode. In this
mode, the RCLK or SCLK output of the palette must be used as the timing reference to present data to the
pixel port [P(0–31)]. In self-clocked mode, RCLK can be directly tied back to LCLK or LCLK can be a delayed
version of RCLK within the timing requirements of the TVP3010. The self-clocked mode of frame-buffer
latching is similar to the operation of the TLC3407X video interface palette devices.

The internal TVP3010 blank signal is generated from either VGABL
VGA port is enabled (multiplex-control register 2 (MCR2) bit 7 = logic 1) or disabled (MCR2 bit 7 = logic 0).
The rising edge of CLK0 is used to latch VGABL
is used to sample and latch the SYSBL

when the VGA port is enabled. The falling edge of VCLK

input when the VGA port is disabled. When the internal blank

becomes active, SCLK is disabled as soon as possible. For example, if SCLK is high when the sampled

goes low, SCLK is allowed to complete the clock cycle and return to the low state. SCLK then is held

SYSBL

or SYSBL, depending on whether the

2–7

low until the sampled SYSBL signal goes back high. At this time, SCLK is enabled to clock the first pixel data
valid from VRAM. The TVP3010 video blanking circuitry is designed with sufficient pipeline delay to allow
the internal sampled SYSBL

and VGABL signals to align with the pipelined RGB data to the video DACs.
The logic described above works in situations where the SCLK period is shorter than, equal to, or longer
than the VCLK period.

When in the self-clocked mode, the SCLK control timing is designed to interface directly with the external
VRAM. The shift register in the system VRAM is supposed to be updated during the blank active period.
When the SYSBL

input is sampled high by the falling edge of VCLK, the VRAM shift clock (SCLK) is restarted
to clock the VRAM and enable the first group of pixel data to appear on the pixel bus as well as at the
TVP3010 pixel input port. The second SCLK causes the VRAM shift register to shift out the second group
of data. At the same time, LCLK latches the first group of pixel data into the VIP (refer to Figure 2–2 for a
detailed timing diagram).

The RCLK/SCLK phase relationship is designed such that timing specifications are satisfied for the case
where SCLK is driving a typical 2-MB VRAM load and RCLK is connected to LCLK. If an external buffer is
required on SCLK so that it can drive a larger load, a similar buffer can be placed on RCLK to match the
signal delay before connecting to LCLK. However, the delay from LCLK to RCLK cannot exceed one RCLK
period –7 ns. Please refer to the timing parameter specifications for more details.

When the VRAM split shift-register operation is performed (see Figure 2–3), the SCLK timing is adjusted
to work with the SFLAG input. Basically, the split shift-register operation inserts an SCLK during the blank
period. This causes the first group of pixel data to appear at the pixel port during blank and allows the first
group of data to be displayed as soon as the palette comes out of blank. Figures 2–3 and 2–5 show the case
when the SSRT (split shift-register transfer) function is enabled. When a rising edge occurs on the SFLAG
input, one SCLK with a minimum 15-ns pulse duration is generated after the specified delay. Since this is
designed to meet VRAM timing requirements, the SSRT-generated SCLK replaces the first SCLK in the
regular shift register transfer case as described above. Refer to Section 2.15 for a detailed explanation of
the SSRT function.

Externally clocked timing can be chosen for the pixel bus [P(0–31)] by setting auxiliary control register bit 3
to a logic 0. In externally clocked mode, the RCLK or SCLK output of the palette is not used as the timing
reference to present data to the pixel bus. Instead, pixel data is presented to the palette with a synchronous
clock and all palette timing is referenced to this clock. In this mode, the external clock should be connected
to LCLK and the selected clock input. (If the VGA port is enabled, the CLK0 input is selected independent
of the input clock selection register.)

The externally clocked frame-buffer interface mode is intended for applications where windowed or
pixel-by-pixel switching between the VGA port and the pixel port is desired in non-VRAM-based graphics
systems. In such applications, the VGA port is enabled (multiplex-control register bit 7 set to logic 1) and
the appropriate direct-color mode is set in the multiplex-control register. The auxiliary window, port select,
and/or color-key switching functions are then configured and enabled to perform the desired switching. By
setting the frame-buffer interface to the externally clocked mode, the pixel port and VGA port timing and
pipeline delay are made the same. Also, since the VGA port is enabled, all video control signal timing is
referenced to CLK0, utilizing the VGABL

, HSYNC, and VSYNC inputs.

The externally clocked frame-buffer interface timing can also be used in non-VGA switching applications,
utilizing only the pixel port or only the VGA port. In either case, it is recommended that VGA video-control
signals be used (i.e., VGABL

, HSYNC, VSYNC). In this way, all pixel data and video control signals are

referenced to CLK0 and video blank and sync are aligned with pixel data.

NOTE:

If the pixel port is used in externally clocked mode (ACR3 = 0), RCLK must be set
to DOT/1 in the output-clock-selection register and a 1:1 multiplexing mode must
be selected in the multiplexer control registers (see T able 2–6). The external clock

2–8

should be connected to the LCLK input as well as the selected clock input. If the
VGA port is also enabled (MCRB7 = 1), CLK0 is selected as the input clock
independent of the input-clock-selection register setting.

VGA switching can only be performed using a 1:1 multiplexing mode.
Overlay switching can only be performed using a 1:1 multiplexing mode if the pixel

port is set for externally clocked mode. If the pixel port is self-clocked, any of the
multiplex ratios available in Table 2–6 may be used.

If VGA switching is to be performed using externally clocked mode (ACR3 = 0), the
full VGA port frequency of 85 MHz may be utilized provided that the VGA port and
the pixel port are both synchronized to the CLK0 input clock.

If VGA switching is to be performed using self-clocked mode (ACR3 = 1), the
maximum pixel rate cannot exceed 50 MHz. This is because of internal delay from
the CLK0 input to the RCLK output. For external clocked timing, the LCLK input
needs to be enabled on terminal 73 by programming the configuration register
bit 5 to logic 1.

VGA data pipeline delay is adjusted within the TVP3010 VIP depending on whether
self- or externally-clocked frame-buffer interface timing is used (see Section 2.3.2).
If the TVP3010 palette is programmed for self-clocked timing, three additional dot
clock pipeline delays are inserted into the internal VGA data path and into the
internal blanking signal. The additional pipeline delay accounts for the difference
between VGABL

or SYSBL and the pixel data inputs [P(0–31)] when used in the
self- and externally-clocked modes. This is so the VGA and pixel-port data remain
synchronous in time when doing auxiliary window, port select, or color-keyed
switching (see Section 2.6). If externally clocked timing is used, the VGA port and
the pixel port are already synchronous since both data and blanking are presented
to the palette during the same CLK0 clock cycle.

VCLK

In Phase

SYSBL

at Input Terminal

Internal Delayed

LCLK = RCLK

Blank

(internal signal

before dot clock

pipeline delay)

Pixel Data

at Input Terminal

SCLK

LD

Latch Last Group

of Pixel Data

Last Group of Pixel Data

Latch First Group of Pixel Data

1st

2nd

3rd

Group

Group

Group

4th

Group

Figure 2–2. SCLK/VCLK Control Timing

(SSRT Disabled, RCLK/SCLK Frequency = VCLK Frequency)

5th

Group

Latch Last Group
of Pixel Data

6th

Group

2–9

VCLK

In Phase

at Input Terminal

SYSBL

SFLAG Input

LD

Internal Delayed

LCLK = RCLK

Blank

(internal signal

before dot clock

pipeline delay)

Pixel Data

at Input Terminal

SCLK

VCLK

In Phase

Latch Last Group

of Pixel Data

Last

Group

1st Group of

SCLK Between Split Shift-Register and Regular Shift-Register Transfer

Pixel Data

Latch First Group of Pixel Data

2nd

3rd

Group

Group

4th

Group

5th

Group

Figure 2–3. SCLK/VCLK Control Timing

(SSRT Enabled, RCLK/SCLK Frequency = VCLK Frequency)

Latch Last Group
of Pixel Data

6th

Group

at Input Terminal

Internal Delayed

LCLK = RCLK

(internal signal

before dot clock

pipeline delay)

Pixel Data

at Input Terminal

2–10

SYSBL

Latch Last Group

of Pixel Data

LD

Latch first Group of Pixel Data

Blank

1st

Last Group of Pixel Data

Group

2nd

Group

SCLK

Figure 2–4. SCLK/VCLK Control Timing

(SSRT Disabled, RCLK/SCLK Frequency = 4 x VCLK Frequency)

3rd

Group

4th

Group

5th

Group

6th

Group

7th

Group

VCLK

In Phase

at Input Terminal

Internal Delayed

before dot clock

at Input Terminal

SYSBL

SFLAG Input

LD

LCLK = RCLK

Blank

(internal signal

pipeline delay)

Pixel Data

SCLK

Latch Last Group
of Pixel Data

Last

Group

First Group of Pixel Data

SCLK Between Split Shift-Register Transfer and Regular Shift-Register Transfer

2nd

Group

Latch Second Group
of Pixel Data

Latch First Group of Pixel Data

4th

5th

Group

3rd

Group

Group

6th

Group

7th

Group

Figure 2–5. SCLK/VCLK Control Timing

(SSRT Enabled, RCLK/SCLK Frequency = 4 x VCLK Frequency)

2.4 Multiplexing Scheme

The TVP3010 palette offers a highly versatile multiplexing scheme as illustrated in T ables 2–6 through 2–1 1.
The multiplexing scheme allows the pixel bus to be programmed to 1, 2, 4, 8, 12, 16, 24, or 32 bits/pixel with
pixel bus widths ranging from 1 bit to 32 bits. The use of on-chip multiplexing allows graphics systems to
be designed that can support multiple pixel depths and resolutions with no hardware modification. It also
allows the system to be configured to the amount of RAM available. For example, if only 256K bytes of
memory are available, an 800-by-600 mode with 4 bit planes (four bits per pixel) could be implemented using
an 8-bit-wide pixel bus. If at a later date another 256K bytes are added to another 8 bits of the pixel bus,
the user has the option of using 8 bit planes at the same resolution or 4 bit planes at a 1024-by-768
resolution. When a further 512K bytes are added to the remaining 16 bits of the pixel bus, the user has the
option of 8 bit planes at 1024-by-768 or 4 bit planes at 1280-by-1024. The TVP3010 palette can also be
configured for direct-color or true-color operation. All of the above could be achieved without any board-level
hardware modification and without any increase in the speed of the pixel bus.

Multiplexing of the pixel bus is controlled by and programmed through multiplex-control registers 1 and 2.
T able 2–6 details the multiplex-control register settings for each mode of operation (see also Sections 2.4.2
through 2.4.6).

2.4.1 Little-Endian and Big-Endian Data Format

The TVP3010 pixel bus supports both little- and big-endian data formats for all pseudo-color, direct-color,
and true-color modes of operation. The data-format select is controlled by general-control register bit 3 (see
Section 2.16.2). When general-control register (GCR) bit 3 is set to 0 (default), then the format is set to little
endian. When GCR bit 3 is set to 1, then the format is set to big endian.

In a big-endian design, the external VRAM data bus bits must be connected in reverse order to the VIP pixel
bus; i.e., D31 connected to P0, D0 connected to P31, etc. This ensures that the least significant channel

2–11

always provides the first pixel to be displayed in the pseudo-color or true-color multiplexing modes. The
difference between little- and big-endian data formats and how they affect the pixel bus operation is
discussed in detail in Appendix C.

2.4.2 VGA Pass-Through Mode

The VGA pass-through mode is used to emulate the VGA modes of most personal computers. The
advantage of this mode is that it can take data presented on the feature connector of most VGA-compatible
PC systems into the device on a separate bus, thus requiring no external multiplexing. This feature is
particularly useful in systems where the existing graphics circuitry is on the motherboard. In this instance,
it enables a drop-in graphics card to be implemented that maintains compatibility with all existing software.
This is accomplished by using the on-board VGA circuitry but routing the emerging bit-plane data through
the TVP3010 palette. VGA pass-through is the default mode at power up or reset.

Since this mode is designed with the feature connector philosophy, all data latching and control timing is
referenced to CLK0. When the VGA port is enabled (MCR2 bit 7 = 1), CLK0 is selected as the input clock
source independent of the input-clock-selection register. The VGA port always operates as in the externally
clocked mode of the pixel port [P(0–31)]; it receives the VGA data [VGA(0–7)] and the VGA blank (VGABL
both of which are referenced to an external clock (CLK0). CLK0 also latches the VGABL
VSYNC
on the VGA port since LCLK only latches data on the pixel port [P(0–31)].

VGA data pipeline delay is adjusted within the TVP3010 palette depending on whether self- or externally­clocked frame-buffer interface timing is used (see Section 2.3.2). If TVP3010 is programmed for self-clocked
timing, additional dot clock pipeline delay is inserted into the internal VGA data path. The purpose is so that
the VGA and pixel port data can remain synchronous when doing auxiliary window, port select, or
color-keyed switching (see Section 2.6). The additional VGA pipeline delay accounts for the dot clock to
RCLK pipeline delay within the palette.

video-control signals when in the VGA pass-through mode. External signals on LCLK have no effect

, HSYNC, and

),

2.4.3 Pseudo-Color Mode

In pseudo-color mode (sometimes called color indexing), the pixel-bus inputs are used to address the
palette-RAM LUT (color lookup table). The data in each RAM location is comprised of 24 bits (8 bits for each
of the red, green, and blue color DACs). The pseudo-color mode is further grouped into 4 submodes,
depending on the data bits per pixel. In each submode, a pixel bus width of 4, 8, 16, or 32 bits may be used.
Data should always be presented on the least significant bits of the pixel bus; i.e., when 16 bits are used,
the pixel data must be presented on P(15 –0), 8 bits on P(7–0), and 4 bits on P(3–0). See Tables 2–6
through 2–11 for more details.

Submode 1 uses a single bit plane to address the color palette. The pixel port bit is fed into bit 0 of the palette
address, with the 7 high-order address bits defined by the palette-page register (see Section 2.2.3). This
mode has uses in high-resolution monochrome applications such as desktop publishing. This mode allows
the maximum amount of multiplexing with 32:1 ratio, thus giving a pixel bus rate of only 4 MHz at a screen
resolution of 1280-by-1024. Although only a single bit is used, alteration of the palette-page register at the
line frequency allows 256 different colors to be displayed per screen with two colors per line.

Submode 2 uses two bit planes to address the color palette. The two bits are fed into the low-order address
bits of the palette with the six high-order address bits being defined by the palette-page register (see
Section 2.2.3). This mode allows a maximum multiplex ratio of 16:1 on the pixel bus and is essentially a
four-color alternative to submode 1.

Submode 3 uses four bit planes to address the color palette. The four bits are fed into the low-order address
bits of the palette with the four high-order address bits being defined by the palette-page register (see
Section 2.2.3). This mode provides 16 pages of 16 colors and can be used at multiplex ratios of /1 to /8.

Submode 4 uses eight bit planes to address the color palette. Since all eight bits of palette address are
specified from the pixel port, the page register is not used. This mode allows dot clock-to-LCLK ratios of 1:1

2–12

(8-bit bus), 2:1 (16-bit bus), or 4:1 (32-bit bus). Therefore, in a 32-bit configuration, a 1024-by-768 pixel
screen can be implemented with an external data rate of only 16 MHz.

NOTE:

If externally clocked frame-buffer timing is used (ACR3 = logic 0, see
Section 2.3.2), only multiplex ratios of 1:1 can be used. See Table 2–6.

The auxiliary window, port select, and color-key switching functions must be
disabled and set for palette graphics when in the pseudo-color mode. This is the
default condition at reset. See Section 2.6

2.4.4 Direct-Color Mode

In direct-color mode, 24, 16, 15, or 12 bits of data can be transferred directly to the RGB DACs but with the
same amount of pipeline delay as the overlay data and the control signals (blank and SYNCs). Depending
on which direct-color mode is selected, overlay is provided by utilizing the remaining bits of the pixel bus
to address the palette RAM. This results in a 24-bit RAM output that is then used as overlay information to
the DACs. The overlay capability is designed to work with the auxiliary window, port select, and color-key
switching functions to provide overlay in specific windows or on a pixel-by-pixel basis on the direct-color
display as discussed in Section 2.6. See Tables 2–6, 2–8, and 2–9 for more details on selecting the
direct-color modes.

The default condition after reset is for the auxiliary window and port select functions to be disabled
(ACR1 = ACR2 = logic 0). The color-key comparisons, which are controlled by the color-key control (CKC)
register bits 0–3, are also disabled (CKC0 = CKC1 = CKC2 = CKC3 = logic 0). Also, since multiplex-control
register 2 bit 7 = logic 1 and ACR0 = CKC4 = logic 1 at reset, the default is for VGA pass through. This is
because multiplex-control register 2 bit 7 enables the VGA port and the switching functions
(switch = color key = 1, see Section 2.6) are disabled and set for palette graphics (as opposed to direct
color-palette bypass).

Submode 1 is the 24-bit direct-color mode that uses eight bits to represent each color and eight bits for
overlay. In this mode, there are basically two different configurations: either the 32-bit data is grouped as
overlay, red, green, blue, or blue, green, red, overlay.

Submode 2 is the XGA-compatible (5–6–5) 16-bit-color mode supporting five bits of red, six bits of green,
and five bits of blue data. The TVP3010 supports multiplex ratios for this mode of 1:1 and 2:1. With 2:1
multiplexing, the TVP3010 can display 1024x768 direct-color using 45-MHz VRAM without any glue logic.
Overlay is not available in this mode.

Submode 3 is the T ARGA-compatible (5–5–5) mode that uses 15 bits for color and 1 bit for overlay. It allows
5 bits for each of red, green, and blue data. The TVP3010 supports 1:1 and 2:1 multiplexing ratios in this
mode.

Submode 4 is (6–6–4) configuration. It provides six bits of red, six bits of green, and four bits of blue. The
TVP3010 also supports 1:1 and 2:1 multiplexing in this mode. Overlay is not available in this mode.

Submode 5 is (4–4–4–4) configuration. It provides 12 bits of direct color and 4 bits of overlay . It allows four
bits for each of red, green, and blue data. The TVP3010 supports 1:1 and 2:1 multiplexing ratios in this mode.

See NOTES in the following section.

2–13

2.4.5 True-Color Mode

In true-color mode, the palette RAM is partitioned into three independent 256-word × 8-bit memory blocks
that can be individually addressed by each color field of the true-color data. The independent memory blocks
provide data for a single DAC output. With this architecture, gamma correction for each color is possible.
Since the palette is used in true-color mode, there is no memory space to be used for the overlay function.
All of the true-color submodes are the same as direct color except that overlay is not available. See T ables
2–6 through 2–1 1 for more details on mode selection. See note below.

NOTE:

Since less than 8 bits are defined for each color in the various 12- or 16-bit direct­or true-color modes, the data bits for the individual colors are internally shifted to
the MSB locations and the remaining LSB locations for each color are set to logic 0
before 8-bit data is sent to the DACs.

Since the overlay information goes through the pseudo-color data path, it is subject
to read masking and the palette-page register. This is especially important for those
direct-color modes that have less than eight bits of overlay information. The overlay
information in these modes justifies to the LSB bit positions, and the remaining
MSB positions are filled with the corresponding palette-page data before
addressing the palette RAM.

In order to display true color (gamma corrected through the palette), either the
auxiliary windowing or the color-key switching function must be set for palette
graphics. For direct color, both functions must be set for direct color.

In order to use the overlay capability of the direct-color modes, the color-key
switching or port-select function must be configured and enabled. Overlay port data
in a window is also available by enabling the auxiliary window function. If either the
auxiliary windowing or the color-key switching functions point to palette graphics,
palette graphics are always displayed (not direct color).

When in the 24-bit direct-color or true-color modes, the data input works only in the
8-bit mode. In other words, if only six bits are used, the two LSB inputs for each color
need to be tied to GND. However, the palette, which is used by the overlay input,
is still governed by 8/6
accordingly. The 8/6

The definitions of direct color (palette bypass) and true color are consistent with the
IBM XGA terminology .

, and the output multiplexer selects 8 bits or 6 bits of data

is also valid in the other 16-bit modes.

2–14

2.4.6 Multiplex-Control Registers

1

2

Color

3

The pixel-port multiplexer is controlled by two 8-bit registers in the indirect register map (see Section 2.1).
The various multiplexing modes can be selected according to the following table.

T able 2–6. Multiplex Mode and Bus-Width Selection

DATA

MODE

VGA 80 98 8 8 1 NA v1

Pseudo­Color

NOTES: 8. Data bits per pixel is the number of bits of pixel port information used as color data for each displayed pixel,

SUB-

MODE

9. Multiplex ratio indicates the number of pixels per bus load or the number of pixels associated with each

10. This column is a reference to Tables 2–7 through 2–1 1, where the actual manipulation of pixel information

11. It is recommended that all unused input terminals be connected to ground to conserve power.

12. Multiplex-control register 2 bit 7 enables (logic 1) and disables (logic 0 ) the VGA port. If auxiliary-window

MULTIPLEX-

CONTROL

REGISTER 1

(HEX)

80 00 1 4 4 NA s1
80 01 1 8 8 NA s2
80 02 1 16 16 NA s3
80 03 1 32 32 NA s4
80 08 2 4 2 NA s6
80 09 2 8 4 NA s7
80 0A 2 16 8 NA s8
80 0B 2 32 16 NA s9
80 10 4 4 1 NA s11
80 11 4 8 2 NA s12
80 12 4 16 4 NA s13
80 13 4 32 8 NA s14
80 19 8 8 1 NA s16

4

often referred to as the number of bit planes.

LCLK (load clock) pulse. For example, with a 32-bit pixel bus width and 8 bit planes, each bus load consists
of four pixels. In a typical implementation, the LCLK signal is either connected to or derived from RCLK.
Therefore, the RCLK divide ratio must be chosen as a function of the multiplex mode selected. The RCLK
divide ratio is not automatically set by mode selection but must be programmed in the output clock selection
register by the user.

and pixel latching sequences are illustrated for each of the multiplexing modes.

or port-select switching is to be done involving the VGA port, this bit needs to be set to a logic 1 as well as
programming for the correct direct-color mode. For example, if auxiliary windowing is to be done with
direct-color submode 1 (32-bit pixel bus) and VGA, instead of programming 1B (hex), multiplex-control
register 2 should be programmed to 9B (hex). If only VGA pass-through is desired, the values should be
programmed for VGA mode as indicated in Table 2–6. If only VGA pass-through is desired, the values
should be programmed as indicated in Table 2–6 for VGA mode.

80 1A 8 16 2 NA s17
80 1B 8 32 4 NA s18

MULTIPLEX-

CONTROL

REGISTER 2

(HEX)

BITS

PER

PIXEL

(see

Note 8)

PIXEL-

BUS

WIDTH

MULTI-

PLEX

RATIO

(see

Note 9)

OVERLA Y

BITS

PER

PIXEL

TABLE

REFERENCE

(see

Note 10)

2–15

T able 2–6. Multiplex Mode and Bus-Width Selection (Continued)

1

(5–6–5)

(5–5–5)

16-bi

12-bi

DATA

BITS

PER

PIXEL

(see

Note 8)

PIXEL-

BUS

WIDTH

1

2

3

4

t

5

t

MULTIPLEX-

CONTROL

REGISTER 1

(HEX)

06 1B 24 32 1 8 d1
07 1B 24 32 1 8 d3
05 02 16 16 1 NA d5

05 03 16 32 2 NA d6
04 02 15 16 1 1 d8
04 03 15 32 2 1 d9
03 02 16 16 1 NA d11
03 03 16 32 2 NA d12
01 12 12 16 1 4 d14
01 13 12 32 2 4 d15

MODE

Direct

NOTES: 9. Data bits per pixel is the number of bits of pixel port information used as color data for each displayed pixel,

SUB-

MODE

24-bit

XGA

TARGA

(6–6–4)

(4–4–4)

often referred to as the number of bit planes.

10. Multiplex ratio indicates the number of pixels per bus load or the number of pixels associated with each
LCLK (load clock) pulse. For example, with a 32-bit pixel bus width and 8 bit planes, each bus load consists
of four pixels. In a typical implementation, the LCLK signal is either connected to or derived from RCLK.
Therefore, the RCLK divide ratio must be chosen as a function of the multiplex mode selected. The RCLK
divide ratio is not automatically set by mode selection but must be programmed in the output clock selection
register by the user.

11. This column is a reference to Tables 2–8 through 2–1 1, where the actual manipulation of pixel information
and pixel latching sequences are illustrated for each of the multiplexing modes.

12. It is recommended that all unused input terminals be connected to ground to conserve power.

13. Multiplex-control register 2 bit 7 enables (logic 1) and disables (logic 0 ) the VGA port. If auxiliary-window
or port-select switching is to be done involving the VGA port, this bit needs to be set to a logic 1 as well as
programming for the correct direct-color mode. For example, if auxiliary windowing is to be done with
direct-color submode 1 (32-bit pixel bus) and VGA, instead of programming 1B (hex), multiplex-control
register 2 should be programmed to 9B (hex). If only VGA pass-through is desired, the values should be
programmed for VGA mode as indicated in Table 2–6. If only VGA pass-through is desired, the values
should be programmed as indicated in Table 2–6 for VGA mode.

MULTIPLEX-

CONTROL

REGISTER 2

(HEX)

MULTI-

PLEX

RATIO

(see

Note 9)

OVERLA Y

BITS

PER

PIXEL

TABLE

REFERENCE

(see

Note 10)

2–16