TEXAS INSTRUMENTS TV5150A Technical data

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Data M anua

May 2004 HPA Digital Audio Video

SLES098

IMPORTANT NOTICE

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Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless

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Contents

Section Title Page

1 Introduction 1−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Features 1−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Product Family 1−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Applications 1−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Related Products 1−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Ordering Information 1−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.6 Functional Block Diagram 1−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.7 Terminal Assignments 1−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.8 Terminal Functions 1−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Functional Description 2−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Analog Front End 2−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Composite Processing Block Diagram 2−1. . . . . . . . . . . . . . . . . . . . . . . . . .

2.3 Adaptive Comb Filtering 2−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Color Low-Pass Filter 2−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5 Luminance Processing 2−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6 Chrominance Processing 2−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.7 Timing Processor 2−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.8 VBI Data Processor 2−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9 VBI FIFO and Ancillary Data in Video Stream 2−4. . . . . . . . . . . . . . . . . . .

2.10 Raw Video Data Output 2−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11 Output Formatter 2−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.12 Synchronization Signals 2−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.13 AVID Cropping 2−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.14 Embedded Syncs 2−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15 I

2.16 Clock Circuits 2−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.17 Genlock Control and RTC 2−12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.18 Reset and Power Down 2−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.19 Internal Control Registers 2−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.20 Register Definitions 2−16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C Host Interface 2−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.1 I

2.15.2 I

2.17.1 TVP5150A Genlock Control Interface 2−12. . . . . . . . . . . . . . . . . .

2.17.2 RTC Mode 2−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C Write Operation 2−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C Read Operation 2−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.2.1 Read Phase 1 2−10. . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.2.2 Read Phase 2 2−11. . . . . . . . . . . . . . . . . . . . . . . . . . .

2.15.2.3 I

C Timing Requirements 2−11. . . . . . . . . . . . . . . . .

iii

2.20.1 Video Input Source Selection #1 Register 2−16. . . . . . . . . . . . . .

2.20.2 Analog Channel Controls Register 2−17. . . . . . . . . . . . . . . . . . . .

2.20.3 Operation Mode Controls Register 2−17. . . . . . . . . . . . . . . . . . . .

2.20.4 Miscellaneous Control Register 2−18. . . . . . . . . . . . . . . . . . . . . . .

2.20.5 Autoswitch Mask Register 2−20. . . . . . . . . . . . . . . . . . . . . . . . . . .

2.20.6 Color Killer Threshold Control Register 2−20. . . . . . . . . . . . . . . .

2.20.7 Luminance Processing Control #1 Register 2−21. . . . . . . . . . . .

2.20.8 Luminance Processing Control #2 Register 2−22. . . . . . . . . . . .

2.20.9 Brightness Control Register 2−22. . . . . . . . . . . . . . . . . . . . . . . . . .

2.20.10 Color Saturation Control Register 2−22. . . . . . . . . . . . . . . . . . . . .

2.20.11 Hue Control Register 2−23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.20.12 Contrast Control Register 2−23. . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.20.13 Outputs and Data Rates Select Register 2−23. . . . . . . . . . . . . . .

2.20.14 Luminance Processing Control #3 Register 2−24. . . . . . . . . . . .

2.20.15 Configuration Shared Pins Register 2−25. . . . . . . . . . . . . . . . . . .

2.20.16 Active Video Cropping Start Pixel MSB Register 2−25. . . . . . . .

2.20.17 Active Video Cropping Start Pixel LSB Register 2−26. . . . . . . . .

2.20.18 Active Video Cropping Stop Pixel MSB Register 2−26. . . . . . . .

2.20.19 Active Video Cropping Stop Pixel LSB Register 2−26. . . . . . . . .

2.20.20 Genlock and RTC Register 2−27. . . . . . . . . . . . . . . . . . . . . . . . . . .

2.20.21 Horizontal Sync (HSYNC) Start Register 2−28. . . . . . . . . . . . . . .

2.20.22 Vertical Blanking Start Register 2−29. . . . . . . . . . . . . . . . . . . . . . .

2.20.23 Vertical Blanking Stop Register 2−29. . . . . . . . . . . . . . . . . . . . . . .

2.20.24 Chrominance Control #1 Register 2−30. . . . . . . . . . . . . . . . . . . . .

2.20.25 Chrominance Control #2 Register 2−31. . . . . . . . . . . . . . . . . . . . .

2.20.26 Interrupt Reset Register B 2−32. . . . . . . . . . . . . . . . . . . . . . . . . . .

2.20.27 Interrupt Enable Register B 2−33. . . . . . . . . . . . . . . . . . . . . . . . . .

2.20.28 Interrupt Configuration Register B 2−34. . . . . . . . . . . . . . . . . . . . .

2.20.29 Video Standard Register 2−34. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.20.30 Cb Gain Factor Register 2−34. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.20.31 Cr Gain Factor Register 2−35. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.20.32 Macrovision On Counter Register 2−35. . . . . . . . . . . . . . . . . . . . .

2.20.33 Macrovision Off Counter Register 2−35. . . . . . . . . . . . . . . . . . . . .

2.20.34 656 Revision Select Register 2−35. . . . . . . . . . . . . . . . . . . . . . . . .

2.20.35 MSB of Device ID Register 2−35. . . . . . . . . . . . . . . . . . . . . . . . . . .

2.20.36 LSB of Device ID Register 2−36. . . . . . . . . . . . . . . . . . . . . . . . . . .

2.20.37 ROM Major Version Register 2−36. . . . . . . . . . . . . . . . . . . . . . . . .

2.20.38 ROM Minor Version Register 2−36. . . . . . . . . . . . . . . . . . . . . . . . .

2.20.39 Vertical Line Count MSB Register 2−36. . . . . . . . . . . . . . . . . . . . .

2.20.40 Vertical Line Count LSB Register 2−36. . . . . . . . . . . . . . . . . . . . .

2.20.41 Interrupt Status Register B 2−37. . . . . . . . . . . . . . . . . . . . . . . . . . .

2.20.42 Interrupt Active Register B 2−37. . . . . . . . . . . . . . . . . . . . . . . . . . .

2.20.43 Status Register #1 2−38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.20.44 Status Register #2 2−39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.20.45 Status Register #3 2−39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.20.46 Status Register #4 2−40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.20.47 Status Register #5 2−40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.20.48 Closed Caption Data Registers 2−41. . . . . . . . . . . . . . . . . . . . . . .

2.20.49 WSS Data Registers 2−41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.20.50 VPS Data Registers 2−42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.20.51 VITC Data Registers 2−42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.20.52 VBI FIFO Read Data Register 2−42. . . . . . . . . . . . . . . . . . . . . . . .

2.20.53 Teletext Filter and Mask Registers 2−43. . . . . . . . . . . . . . . . . . . .

2.20.54 Teletext Filter Control Register 2−44. . . . . . . . . . . . . . . . . . . . . . . .

2.20.55 Interrupt Status Register A 2−45. . . . . . . . . . . . . . . . . . . . . . . . . . .

2.20.56 Interrupt Enable Register A 2−46. . . . . . . . . . . . . . . . . . . . . . . . . .

2.20.57 Interrupt Configuration Register A 2−47. . . . . . . . . . . . . . . . . . . . .

2.20.58 VDP Configuration RAM Register 2−47. . . . . . . . . . . . . . . . . . . . .

2.20.59 VDP Status Register 2−49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.20.60 FIFO Word Count Register 2−49. . . . . . . . . . . . . . . . . . . . . . . . . . .

2.20.61 FIFO Interrupt Threshold Register 2−50. . . . . . . . . . . . . . . . . . . .

2.20.62 FIFO Reset Register 2−50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.20.63 Line Number Interrupt Register 2−50. . . . . . . . . . . . . . . . . . . . . . .

2.20.64 Pixel Alignment Registers 2−50. . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.20.65 FIFO Output Control Register 2−51. . . . . . . . . . . . . . . . . . . . . . . .

2.20.66 Full Field Enable Register 2−51. . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.20.67 Line Mode Registers 2−52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.20.68 Full Field Mode Register 2−53. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Electrical Specifications 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature

Range 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Recommended Operating Conditions 3−1. . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.1 Crystal Specifications 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Electrical Characteristics 3−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.1 DC Electrical Characteristics 3−2. . . . . . . . . . . . . . . . . . . . . . . . .

3.3.2 Analog Processing and A/D Converters 3−2. . . . . . . . . . . . . . . .

3.3.3 Timing 3−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.3.1 Clocks, Video Data, Sync Timing 3−3. . . . . . . . . . .

3.3.3.2 I

C Host Port Timing 3−4. . . . . . . . . . . . . . . . . . . . .

4 Example Register Settings 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 Example 1 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.1 Assumptions 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.2 Recommended Settings 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Example 2 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.1 Assumptions 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2.2 Recommended Settings 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Application Information 5−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 Application Example 5−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 Mechanical Data 6−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Illustrations

Figure Title Page

1−1 Functional Block Diagram 1−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−1 Composite Processing Block Diagram 2−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−2 8-bit 4:2:2, Timing With 2x Pixel Clock (SCLK) Reference 2−6. . . . . . . . . . . .

2−3 Horizontal Synchronization Signals 2−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−4 AVID Application 2−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−5 Reference Clock Configurations 2−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−6 GLCO Timing 2−12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−7 RTC Timing 2−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−8 Configuration Shared Pins 2−19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−9 Horizontal Sync 2−28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−1 Clocks, Video Data, and Sync Timing 3−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3−2 I

5−1 Application Example 5−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C Host Port Timing 3−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Tables

Table Title Page

1−1 Terminal Functions 1−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−1 Data Types Supported by the VDP 2−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−2 Ancillary Data Format and Sequence 2−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−3 Summary of Line Frequencies, Data Rates, and Pixel Counts 2−5. . . . . . . .

2−4 EAV and SAV Sequence 2−8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−5 Write Address Selection 2−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−6 I

2−7 Read Address Selection 2−10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−8 Reset and Power Down Modes 2−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−9 Registers Summary 2−14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−10 Analog Channel and Video Mode Selection 2−16. . . . . . . . . . . . . . . . . . . . . . . .

2−11 Digital Output Control 2−18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−12 Clock Delays (SCLKs) 2−28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−13 VBI Configuration RAM For Signals With Pedestal 2−48. . . . . . . . . . . . . . . . . .

C Terminal Description 2−9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1 Introduction

Macrovision is a trademark of Macrovision Corporation. O

The TVP5150A device is an ultralow power NTSC/PAL/SECAM video decoder. Available in a space saving 32-pin TQFP package, the TVP5150A decoder converts NTSC, PAL, and SECAM video signals to 8-bit ITU-R BT.656 format. Discrete syncs are also available. The optimized architecture of the TVP5150A decoder allows for ultralow-power consumption. The decoder consumes 115 mW of power in typical operation and consumes less than 1 mW in power-down mode, considerably increasing battery life in portable applications. The decoder uses just one crystal for all supported standards. The TVP5150A decoder can be programmed using an I decoder uses a 1.8-V supply for its analog and digital supplies, and a 3.3-V supply for its I/O.

The TVP5150A decoder converts baseband analog video into digital YCbCr 4:2:2 component video. Composite and S-video inputs are supported. The TVP5150A decoder includes one 9-bit analog-to-digital converter (ADC) with 2x sampling. Sampling is ITU-R BT.601 (27.0 MHz, generated from the 14.31818-MHz crystal or oscillator input) and is line-locked. The output formats can be 8-bit 4:2:2 or 8-bit ITU-R BT.656 with embedded synchronization.

The TVP5150A decoder utilizes Texas Instruments patented technology for locking to weak, noisy, or unstable signals. A Genlock/real-time control (RTC) output is generated for synchronizing downstream video encoders.

Complementary 4-line adaptive comb filtering is available for both the luma and chroma data paths to reduce both cross-luma and cross-chroma artifacts; a chroma trap filter is also available.

C serial interface. The

Video characteristics including hue, contrast, brightness, saturation, and sharpness may be programmed using the industry standard I

C serial interface. The TVP5150A decoder generates synchronization, blanking, lock, and clock

signals in addition to digital video outputs. The TVP5150A decoder includes methods for advanced vertical blanking interval (VBI) data retrieval. The VBI data processor slices, parses, and performs error checking on teletext, closed caption, and other data in several formats.

The TVP5150A decoder detects copy-protected input signals according to the Macrovision standard and detects Type 1, 2, 3, and colorstripe pulses.

The main blocks of the TVP5150A decoder include:

• Robust sync detector

• ADC with analog processor

• Y/C separation using 4-line adaptive comb filter

• Chrominance processor

• Luminance processor

• Video clock/timing processor and power-down control

• Output formatter

• I

C interface

• VBI data processor

• Macrovision detection for composite and S-video

1.1 Features

• Accepts NTSC (M, 4.43), PAL (B, D, G, H, I, M, N), and SECAM (B, D, G, K, K1, L) video data

• Supports ITU-R BT.601 standard sampling

• High-speed 9-bit ADC

• Two composite inputs or one S-video input

ther trademarks are the property of their respective owners.

1−1

• Fully differential CMOS analog preprocessing channels with clamping and automatic gain control (AGC) for best signal-to-noise (S/N) performance

• Ultralow power consumption: 115 mW typical

• 32-pin TQFP package

• Power-down mode: <1 mW

• Brightness, contrast, saturation, hue, and sharpness control through I

• Complementary 4-line (3-H delay) adaptive comb filters for both cross-luminance and cross-chrominance noise reduction

• Patented architecture for locking to weak, noisy, or unstable signals

• Single 14.31818-MHz crystal for all standards

• Internal phase-locked loop (PLL) for line-locked clock and sampling

• Subcarrier Genlock output for synchronizing color subcarrier of external encoder

• Standard programmable video output format:

− ITU-R BT.656, 8-bit 4:2:2 with embedded syncs

− 8-bit 4:2:2 with discrete syncs

• Macrovision copy protection detection

• Advanced programmable video output formats:

− 2x oversampled raw VBI data during active video

− Sliced VBI data during horizontal blanking or active video

• VBI modes supported

− Teletext (NABTS, WST)

− Closed-caption decode with FIFO, and extended data services (EDS)

− Wide screen signaling, video program system, CGMS, vertical interval time code

− Gemstar 1x/2x electronic program guide compatible mode

− Custom configuration mode that allows the user to program the slice engine for unique VBI data signals

• Power-on reset

1.2 Product Family

This data manual covers three devices in the TVP5150A product family: the TVP5150APBS, the TVP5150AM1PBS, and the TVP5150AM1ZQC. The hardware for these three devices is identical. The following software changes are the differences between these two devices. For the remainder of this document, unless otherwise noted, TVP5150A refers to all three devices.

• TVP5150APBS

− ROM version 3.21

− SECAM is masked from the autoswitch process in the default mode of register 0x04

− Only supports ITU-R BT656.4 timing

• TVP5150AM1PBS/TVP5150AM1ZQC

− ROM version 4.00

− SECAM is unmasked from the autoswitch process in the default mode of register 0x04

− Addition of register 0x30 to select ITU-R BT656.3 or ITU-R BT656.4 timing

1−2

1.3 Applications

The following is a partial list of suggested applications:

• Digital television

• PDA

• Notebook PCs

• Cell phones

• Video recorder/players

• Internet appliances/web pads

• Handheld games

1.4 Related Products

• TVP5146 NTSC/PAL/SECAM 4x10-Bit Digital Video Decoder With Macrovision Detection, YPbPr/RGB Inputs, 5-Line Comb Filter and SCART/Digital RGB Overlay SupportDecoder With Robust Sync Detector,

Literature Number SLES084

1.5 Ordering Information

0°C to 70°C TVP5150APBS Tray 0°C to 70°C TVP5150APBSR Tape and reel 0°C to 70°C TVP5150AM1PBS Tray 0°C to 70°C TVP5150AM1PBSR Tape and reel 0°C to 70°C TVP5150AM1ZQC Tray 0°C to 70°C TVP5150AM1ZQCR Tape and reel

PACKAGED DEVICES

32TQFP-PBS

PACKAGE OPTION

1−3

1.6 Functional Block Diagram

MACROVISION

DETECTION

AIP1A AIP1B

M U X

AGC

A/D

Y/C SEPARATION

LUMINANCE

PROCESSING

CHROMINANCE

PROCESSING

VBI / DATA SLICER

OUTPUT

FORMATTER

YOUT[7:0] YCbCr 8-BIT 4:2:2

SCL

SDA

INTERFACE

XTAL1 XTAL2

PCLK/SCLK

I2C

HOST PROCESSOR

PDN

FID/GLCO VSYNC/PALI INTERQ/GPCL/VBLK

LINE AND

CHROMA PLLS

SYNC PROCESSOR

HSYNC AVID

Figure 1−1. Functional Block Diagram

1−4

1.7 Terminal Assignments

NAME

I/O

DESCRIPTION

TQFP PACKAGE

(TOP VIEW)

CH_AVDD

CH_AGND

REFM

32 26 25

31 30 29 28 27

AIP1A AIP1B

PLL_AGND

PLL_AVDD

XTAL1/OSC

XTAL2

AGND

RESETB

1 2 3 4 5 6 7 8

10 11 12 13 1491516

REFP

PDN

INTREQ/GPCL/VBLK

AVID

HSYNC

24 23 22 21 20 19 18 17

VSYNC/PALI FID/GLCO SDA SCL DVDD DGND YOUT0 YOUT1

ZQC PACKAGE

(BOTTOM VIEW)

G F E D C B A

23456

YOUT6

YOUT5

YOUT4

YOUT3

YOUT2

IO_DVDD

PCLK/SCLK

YOUT7/I2CSEL

1.8 Terminal Functions

Table 1−1. Terminal Functions

TERMINAL

NUMBER

PBS ZQC

Analog Section

AGND 7 E1 I Substrate. Connect to analog ground.

AIP1A 1 A1 I

AIP1B 2 B1 I

CH_AGND 31 A3 I Analog ground CH_AVDD 32 A2 I Analog supply. Connect to 1.8-V analog supply.

B2, B3, B6, C4,

NC −

PLL_AGND 3 C2 I PLL ground. Connect to analog ground. PLL_AVDD 4 C1 I PLL supply. Connect to 1.8-V analog supply.

C5, D3−D6,

E2−E5, F2, F5,

I/O DESCRIPTION

Analog input. Connect to the video analog input via 0.1-µF capacitor . The maximum input range is 0−0.75 VPP, and may require an attenuator to reduce the input amplitude to the desired level. If not used, connect to AGND via 0.1-µF capacitor. Refer to Figure 5−1.

− No connect

1−5

Table 1−1. Terminal Functions (Continued)

NAME

I/O

DESCRIPTION

TERMINAL

NUMBER

PBS ZQC

Analog Section (continued)

REFM 30 A4 I REFP 29 B4 I A/D reference supply. Connect to analog ground through 1-µF capacitor. Refer to Figure 5−1.

Digital Section

AVID 26 A6 O

DGND 19 E6 I Digital ground DVDD 20 E7 I Digital supply. Connect to 1.8-V digital supply

FID/GLCO 23 C6 O

HSYNC 25 A7 O Horizontal synchronization signal

INTREQ/GPCL/ VBLK

IO_DVDD 10 G2 I Digital supply. Connect to 3.3 V. PCLK/SCLK 9 G1 O System clock at either 1x or 2x the frequency of the pixel clock.

PDN 28 A5 I

RESETB 8 F1 I SCL 21 D7 I/O I2C serial clock (open drain)

SDA 22 C7 I/O I2C serial data (open drain)

VSYNC/PALI 24 B7 O

XTAL1/OSC XTAL2

YOUT[6:0]

YOUT7/I2CSEL 11 F3 I/O

27 B5 I/O

56D2D1I

12 13 14 15 16 17 18

I/O DESCRIPTION

A/D reference ground. Connect to analog ground through 1-µF capacitor. Also, it is recommended to connect directly to REFP through 1-µF capacitor. Refer to Figure 5−1.

Active video indicator. This signal is high during the horizontal active time of the video output. AVID toggling during vertical blanking intervals is controlled by bit 2 of the active video cropping start pixel LSB register at address 12h (see Section 2.20.17).

FID: Odd/even field indicator or vertical lock indicator. For the odd/even indicator, a 1 indicates the odd field. GLCO: This serial output carries color PLL information. A slave device can decode the information to allow chroma frequency control from the TVP5150A decoder. Data is transmitted at the SCLK rate in Genlock mode. In RTC mode, SCLK/4 is used.

INTREQ: Interrupt request output. GPCL/VBLK: General-purpose control logic. This terminal has two functions:

1. GPCL: General-purpose output. In this mode the state of GPCL is directly programmed via I2C.

2. VBLK: Vertical blank output. In this mode the GPCL terminal indicates the vertical blanking interval of the output video. The beginning and end times of this signal are programmable via I2C.

Power-down terminal (active low). Puts the decoder in standby mode. Preserves the value of the registers.

Active-low reset. RESETB can be used only when PDN = 1. When RESETB is pulled low, it resets all the registers and restarts the internal microprocessor.

VSYNC: Vertical synchronization signal PALI: PAL line indicator or horizontal lock indicator For the PAL line indicator:

1 = Indicates a noninverted line 0 = Indicates an inverted line

External clock reference. The user may connect XTAL1 to an oscillator or to one terminal of a crystal oscillator. The user may connect XTAL2 to the other terminal of the crystal oscillator or not connect XTAL2 at all. One single 14.31818-MHz crystal or oscillator is needed for ITU-R BT.601 sampling, for

all supported standards.

G3 F4 G4 G5

I/O Output decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync. G6 G7 F7

I2CSEL: Determines address for I2C (sampled during reset). A pullup or pulldown register is needed (>1 kΩ) to program the terminal to the desired address.

1 = Address is 0xBA 0 = Address is 0xB8

YOUT7: MSB of output decoded ITU-R BT.656 output/YCbCr 4:2:2 output.

1−6

2 Functional Description

2.1 Analog Front End

The TVP5150A decoder has an analog input channel that accepts two video inputs, which are ac-coupled. The decoder supports a maximum input voltage range of 0.75 V; therefore, an attenuation of one-half is needed for most input signals with a peak-to-peak variation of 1.5 V. The maximum parallel termination before the input to the device is 75 Ω. Please refer to the applications diagram in Figure 5−1 for the recommended configuration. The two analog input ports can be connected as follows:

• Two selectable composite video inputs or

• One S-video input

An internal clamping circuit restores the ac-coupled video signal to a fixed dc level. The programmable gain amplifier (PGA) and the AGC circuit work together to make sure that the input signal is

amplified sufficiently to ensure the proper input range for the ADC. The ADC has 9 bits of resolution and runs at a maximum speed of 27 MHz. The clock input for the ADC comes from

the PLL.

2.2 Composite Processing Block Diagram

The composite processing block processes NTSC/PAL/SECAM signals into the YCbCr color space. Figure 2−1 explains the basic architecture of this processing block.

Figure 2−1 illustrates the luminance/chrominance (Y/C) separation process in the TVP5150A decoder. The composite video is multiplied by subcarrier signals in the quadrature modulator to generate the color difference signals Cb and Cr . Cb and Cr are then low-pass (LP) filtered to achieve the desired bandwidth and to reduce crosstalk.

An adaptive 4-line comb filter separates CbCr from Y. Chroma is remodulated through another quadrature modulator and subtracted from the line-delayed composite video to generate luma. Contrast, brightness, hue, saturation, and sharpness (using the peaking filter) are programmable via I

The Y/C separation is bypassed for S-video input. For S-video, the remodulation path is disabled.

2.3 Adaptive Comb Filtering

The 4-line comb filter can be selectively bypassed in the luma or chroma path. If the comb filter is bypassed in the luma path, then chroma notch filters are used. TI’s patented adaptive 4-line comb filter algorithm reduces artifacts such as hanging dots at color boundaries and detects and properly handles false colors in high frequency luminance images such as a multiburst pattern or circle pattern.

2.4 Color Low-Pass Filter

In some applications, it is desirable to limit the Cb/Cr bandwidth to avoid crosstalk. This is especially true in case of video signals that have asymmetrical Cb/Cr sidebands. The color LP filters provided limit the bandwidth of the Cb/Cr signals.

Color LP filters are needed when the comb filtering turns off, due to extreme color transitions in the input image. Please refer to Sec t ion 2.20.25, Chrominance Control #2 Register, for the response of these filters. The filters have three options that allow three different frequency responses based on the color frequency characteristics of the input video.

2−1

Gain Factor

Composite

Line

Delay

SECAM Luma

SECAM Color Demodulation

Peak

Detector

−

LPF ↓ 2

Bandpass

Color

Burst

Accumulator

(Cb)

Quadrature

Modulation

4-Line

Adaptive

Comb

Filter

Peaking

Notch

Filter

Notch

Filter

+Delay

Delay

Contrast

Brightness

Saturation

Adjust

Cb Cr

Delay

Composite

Quadrature Modulation

Color

LPF ↓ 2

Burst

Accumulator

(Cr)

Filter

Delay

Figure 2−1. Composite Processing Block Diagram

2.5 Luminance Processing

The luma component is derived from the composite signal by subtracting the remodulated chroma information. A line delay exists in this path to compensate for the line delay in the adaptive comb filter in the color processing chain. The luma information is then fed into the peaking circuit, which enhances the high frequency components of the signal, thus improving sharpness.

2.6 Chrominance Processing

For NTSC/PAL formats, the color processing begins with a quadrature demodulator. The Cb/Cr signals then pass through the gain control stage for chroma saturation adjustment. An adaptive comb filter is applied to the demodulated signals to separate chrominance and eliminate cross-chrominance artifacts. An automatic color killer circuit is also included in this block. The color killer suppresses the chroma processing when the color burst of the video signal is weak or not present. The SECAM standard is similar to PAL except for the modulation of color which is FM instead of QAM.

2−2

2.7 Timing Processor

The timing processor is a combination of hardware and software running in the internal microprocessor that serves to control horizontal lock to the input sync pulse edge, AGC and offset adjustment in the analog front end, vertical sync detection, and Macrovisiont detection.

2.8 VBI Data Processor

The TVP5150A VBI data processor (VDP) slices various data services like teletext (WST, NABTS), closed caption (CC), wide screen signaling (WSS), etc. These services are acquired by programming the VDP to enable standards in the VBI. The results are stored in a FIFO and/or registers. The teletext results are stored in a FIFO only. Table 2−1 lists a summary of the types of VBI data supported according to the video standard. It supports ITU-R BT. 601 sampling for each.

Table 2−1. Data Types Supported by the VDP

LINE MODE

BITS [3:0]

0000b x x Reserved 0000b 1 WST SECAM 6 Teletext, SECAM 0001b x x Reserved 0001b 1 WST PAL B 6 Teletext, PAL, System B 0010b x x Reserved 0010b 1 WST PAL C 6 Teletext, PAL, System C

0011b x x Reserved

0011b 1 WST, NTSC B 6 Teletext, NTSC, System B 0100b x x Reserved 0100b 1 NABTS, NTSC C 6 Teletext, NTSC, System C 0101b x x Reserved 0101b 1 NABTS, NTSC D 6 Teletext, NTSC, System D (Japan)

0110b x x Reserved

0110b 1 CC, PAL 6 Closed caption PAL

0111b x x Reserved

0111b 1 CC, NTSC 6 Closed caption NTSC 1000b x x Reserved 1000b 1 WSS, PAL 6 Wide-screen signal, PAL 1001b x x Reserved 1001b 1 WSS, NTSC 6 Wide-screen signal, NTSC 1010b x x Reserved 1010b 1 VITC, PAL 6 Vertical interval timecode, PAL

1011b x x Reserved

1011b 1 VITC, NTSC 6 Vertical interval timecode, NTSC

1100b x x Reserved

1100b 1 VPS, PAL 6 Video program system, PAL

1101b x x Reserved

1110b x x Reserved

1111b x Active Video Active video/full field

SAMPLING

RATE (0Dh)

BIT 7

NAME DESCRIPTION

2−3

At powerup the host interface is required to program the VDP-configuration RAM (VDP-CRAM) contents with the

Ancillary data preamble

1 word

N word

lookup table (see Section 2.20.58). This is done through port address C3h. Each read from or write to this address will auto increment an internal counter to the next RAM location. To access the VDP-CRAM, the line mode registers (D0h−FCh) must be programmed with FFh to avoid a conflict with the internal microprocessor and the VDP in both writing and reading. Full field mode must also be disabled.

Available VBI lines are from line 6 to line 27 of both field 1 and field 2. Each line can be any VBI mode. Output data is available either through the VBI-FIFO (B0h) or through dedicated registers at 90h−AFh, both of which

are available through the I

C port.

2.9 VBI FIFO and Ancillary Data in Video Stream

Sliced VBI data can be output as ancillary data in the video stream in the ITU-R BT.656 mode. VBI data is output during the horizontal blanking period following the line from which the data was retrieved. Table 2−2 shows the header format and sequence of the ancillary data inserted into the video stream. This format is also used to store any VBI data into the FIFO. The size of FIFO is 512 bytes. Therefore, the FIFO can store up to 11 lines of teletext data with the NTSC NABTS standard.

Table 2−2. Ancillary Data Format and Sequence

BYTE

NO.

0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 3 NEP EP 0 1 0 DID2 DID1 DID0 Data ID (DID) 4 NEP EP F5 F4 F3 F2 F1 F0 Secondary data ID (SDID) 5 NEP EP N5 N4 N3 N2 N1 N0 Number of 32 bit data (NN) 6 Video line # [7:0] Internal data ID0 (IDID0) 7 0 0 0 Data

8 1. Data Data byte

9 2. Data Data byte 10 3. Data Data byte 11 4. Data Data byte

: : :

4(N+2)−1 1 0 0 0 0 0 0 0 Fill byte

(MSB)

NEP EP CS[5:0] Check sum

D6 D5 D4 D3 D2 D1 D0

(LSB)

Ancillary data preamble

Match#1Match#2Video line # [9:8] Internal data ID1 (IDID1)

error

m−1. Data Data byte

m. Data Data byte

DESCRIPTION

1st word

Nth word

EP: Even parity for D0−D5 NEP: Negated even parity DID: 91h: Sliced data of VBI lines of first field

SDID: This field holds the data format taken from the line mode register of the corresponding line. NN: Number of Dwords beginning with byte 8 through 4(N+2). This value is the number of Dwords where

IDID0: Transaction video line number [7:0]

2−4

53h: Sliced data of line 24 to end of first field 55h: Sliced data of VBI lines of second field 97h: Sliced data of line 24 to end of second field

each Dword is 4 bytes.

IDID1: Bit 0/1 = Transaction video line number [9:8]

Bit 2 = Match 2 flag Bit 3 = Match 1 flag

Bit 4 = 1 if an error was detected in the EDC block. 0 if not. CS: Sum of D0−D7 of DID through last data byte. Fill byte: Fill bytes make a multiple of 4 bytes from byte 0 to last fill byte. For teletext modes, byte 8 is the sync pattern

byte. Byte 9 is 1. Data (the first data byte).

2.10 Raw Video Data Output

The TVP5150A decoder can output raw A/D video data at 2x sampling rate for external VBI slicing. This is transmitted as an ancillary data block during the active horizontal portion of the line and during vertical blanking.

2.11 Output Formatter

The YCbCr digital output can be programmed as 8-bit 4:2:2 or 8-bit ITU-R BT.656 parallel interface standard.

Table 2−3. Summary of Line Frequencies, Data Rates, and Pixel Counts

STANDARDS

NTSC (M, 4.43), ITU-R BT.601 15.73426 858 720 27.00 PAL (B, D, G, H, I), ITU-R BT.601 15.625 864 720 27.00 PAL (M), ITU-R BT.601 15.73426 858 720 27.00 PAL (N), ITU-R BT.601 15.625 864 720 27.00 SECAM, ITU-R BT.601 15.625 864 720 27.00

HORIZONTAL

LINE RATE (kHz)

PIXELS PER

LINE

ACTIVE PIXELS

PER LINE

SCLK FREQUENCY

(MHz)

2.12 Synchronization Signals

External (discrete) syncs are provided via the following signals:

• VSYNC (vertical sync)

• FID/VLK (field indicator or vertical lock indicator)

• GPCL/VBLK (general-purpose I/O or vertical blanking indicator)

• PALI/HLK (PAL switch indicator or horizontal lock indicator)

• HSYNC (horizontal sync)

• AVID (active video indicator)

VSYNC, FID, PALI, and VBLK are software-set and programmable to the SCLK pixel count. This allows any possible alignment to the internal pixel count and line count. The default settings for a 525-/625-line video output are given as an example below.

2−5

Composite

Video

VSYNC

FID

GPCL/VBLK

525-Line

525

1234567891011 202122

Composite

Video

VSYNC

FID

GPCL/VBLK

Composite

Video

VSYNC

FID

GPCL/VBLK

↔

VBLK Start

262 263 264 265 266 267 268 269 270 271 272 273 282 283 284

↔

VBLK Start

625-Line

310 311 312 313 314 315 316 317 318 319 320 333 334 335 336

↔

VBLK Start

↔

VBLK Stop

↔

VBLK Stop

↔

VBLK Stop

6226236246251234567 20212223

Composite

Video

VSYNC

FID

GPCL/VBLK

↔

VBLK Start

NOTE: Line numbering conforms to ITU-R BT.470.

Figure 2−2. 8-bit 4:2:2, Timing With 2x Pixel Clock (SCLK) Reference

2−6

↔

VBLK Stop

NTSC 601 1436

ITU-R BT.656 timing.

PAL 601 1436 SECAM

ITU 656 Datastream

HSYNC

1436 1437 1438 1439 1440 1441 … 1479 1480 …

359

AVID

1437 1437

718

1438 1438

359

1439 1439

719

1440 1440

1441 1441

…

1455

…

1459

…

↔

HSYNC Start

1456 1460

…

1583

…

1587 1607 1608

…

1584 1588

…

1711

…

1723

…

1719 1720

…

1713

1712

1725

1724

1721 1722 1723

1714 1726

1715 1727

17241725172617

3 3

Y 1

↔

AVID Stop

↔

AVID Start

NOTE: AVID rising edge occurs 4 SCLK cycles early when in the ITU-R BT.656 output mode.

Figure 2−3. Horizontal Synchronization Signals

2.13 AVID Cropping

AVID or active video cropping provides a means to decrease bandwidth of the video output. This is accomplished by horizontally blanking a number of AVID pulses and by vertically blanking a number of lines per frame. The horizontal AVID cropping is controlled using registers 11h and 12h for start pixels MSB and LSB, respectively.

Registers 13h and 14h provide access to stop pixels MSB and LSB, respectively. The vertical AVID cropping is controlled using the vertical blanking (VBLK) start and stop registers at addresses 18h and 19h. Figure 2−4 shows an AVID application.

2−7

VBLK Stop

VBLK Start

Active Video Area

AVID Cropped

Area

AVID Start

VSYNC

HSYNC

AVID Stop

Figure 2−4. AVID Application

2.14 Embedded Syncs

Standards with embedded syncs insert SAV and EAV codes into the datastream at the beginning and end of horizontal blanking. These codes contain the V and F bits which also define vertical timing. F and V change on EAV . Table 2−4 gives the format of the SAV and EAV codes.

H equals 1 always indicates EAV. H equals 0 always indicates SAV. The alignment of V and F to the line and field counter varies depending on the standard. Please refer to ITU-R BT.656 for more information on embedded syncs.

The P bits are protection bits:

P3 = V xor H P2 = F xor H P1 = F xor V P0 = F xor V xor H

Table 2−4. EAV and SAV Sequence

8-BIT DATA

D7 (MSB) D6 D5 D4 D3 D2 D1 D0

Preamble 1 1 1 1 1 1 1 1 Preamble 0 0 0 0 0 0 0 0 Preamble 0 0 0 0 0 0 0 0 Status word 1 F V H P3 P2 P1 P0

2−8

2.15 I2C Host Interface

The I2C standard consists of two signals, serial input/output data line (SDA) and input/output clock line (SCL), which carry information between the devices connected to the bus. A third signal (I2CSEL) is used for slave address selection. Although the I

Both SDA and SCL must be connected to a positive supply voltage via a pullup resistor. When the bus is free, both lines are high. The slave address select terminal (I2CSEL) enables the use of two TVP5150A decoders tied to the

same I

C bus. At power up, the status of the I2CSEL is polled. Depending on the write and read addresses to be used for the TVP5150A decoder, it can either be pulled low or high through a resistor. This terminal is multiplexed with YOUT7 and hence must not be tied directly to ground or IO_DVDD. Table 2−6 summarizes the terminal functions of

the I

C-mode host interface.

Data transfer rate on the bus is up to 400 kbits/s. The number of interfaces connected to the bus is dependent on the bus capacitance limit of 400 pF. The data on the SDA line must be stable during the high period of the SCL except for start and stop conditions. The high or low state of the data line can only change with the clock signal on the SCL line being low. A high-to-low transition on the SDA line while the SCL is high indicates an I low-to-high transition on the SDA line while the SCL is high indicates an I

C system can be multimastered, the TVP5150A decoder functions as a slave device only.

Table 2−5. Write Address Selection

I2CSEL WRITE ADDRESS

0 B8h 1 BAh

T able 2−6. I2C Terminal Description

SIGNAL TYPE DESCRIPTION

I2CSEL (YOUT7) I Slave address selection

SCL I/O (open drain) Input/output clock line SDA I/O (open drain) Input/output data line

C stop condition.

C start condition. A

Every byte placed on the SDA must be 8 bits long. The number of bytes which can be transferred is unrestricted. Each byte must be followed by an acknowledge bit. The acknowledge-related clock pulse is generated by the I

C master.

2.15.1 I2C Write Operation

Data transfers occur utilizing the following illustrated formats.

C master initiates a write operation to the TVP5150A decoder by generating a start condition (S) followed by

An I the TVP5150A I receiving an acknowledge from the TVP5150A decoder, the master presents the subaddress of the register, or the first of a block of registers it wants to write, followed by one or more bytes of data, MSB first. The TVP5150A decoder acknowledges each byte after completion of each transfer. The I generating a stop condition (P).

Step 1 0

I2C Start (master) S

Step 2 7 6 5 4 3 2 1 0

I2C General address (master) 1 0 1 1 1 0 X 0

Step 3 9

I2C Acknowledge (slave) A

Step 4 7 6 5 4 3 2 1 0

I2C Write register address (master) addr addr addr addr addr addr addr addr

C address (as shown below), in MSB first bit order, followed by a 0 to indicate a write cycle. After

C master terminates the write operation by

2−9

Step 5

I2C Acknowledge (slave) A

Step 6 7 6 5 4 3 2 1 0

I2C Write data (master) Data Data Data Data Data Data Data Data

†

Step 7

I2C Acknowledge (slave) A

Step 8 0

I2C Stop (master) P

†

Repeat steps 6 and 7 until all data have been written.

2.15.2 I2C Read Operation

The read operation consists of two phases. The first phase is the address phase. In this phase, an I2C master initiates a write operation to the TVP5150A decoder by generating a start condition (S) followed by the TVP5150A I

C address, in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving acknowledges from the TVP5150A decoder, the master presents the subaddress of the register or the first of a block of registers it wants to read. After the cycle is acknowledged, the master terminates the cycle immediately by generating a stop condition (P).

Table 2−7. Read Address Selection

I2CSEL READ ADDRESS

0 B9h 1 BBh

The second phase is the data phase. In this phase, an I2C master initiates a read operation to the TVP5150A decoder by generating a start condition followed by the TVP5150A I first bit order, followed by a 1 to indicate a read cycle. After an acknowledge from the TVP5150A decoder, the I master receives one or more bytes of data from the TVP5150A decoder. The I

C address (as shown below for a read operation), in MSB

C master acknowledges the transfer

at the end of each byte. After the last data byte desired has been transferred from the TVP5150A decoder to the master, the master generates a not acknowledge followed by a stop.

2.15.2.1Read Phase 1

Step 1 0

I2C Start (master) S

Step 2 7 6 5 4 3 2 1 0

I2C General address (master) 1 0 1 1 1 0 X 0

Step 3 9

I2C Acknowledge (slave) A

Step 4 7 6 5 4 3 2 1 0

I2C Read register address (master) addr addr addr addr addr addr addr addr

Step 5 9

I2C Acknowledge (slave) A

Step 6 0

I2C Stop (master) P

2−10

2.15.2.2Read Phase 2

Step 7 0

I2C Start (master) S

Step 8 7 6 5 4 3 2 1 0

I2C General address (master) 1 0 1 1 1 0 X 1

Step 9 9

I2C Acknowledge (slave) A

Step 10 7 6 5 4 3 2 1 0

I2C Read data (slave) Data Data Data Data Data Data Data Data

†

Step 11

I2C Not acknowledge (master) A

Step 12 0

I2C Stop (master) P

†

Repeat steps 10 and 11 for all bytes read. Master does not acknowledge the last read data received.

2.15.2.3I2C Timing Requirements

The TVP5150A decoder requires delays in the I2C accesses to accommodate its internal processor’s timing. In accordance with I period to the I

C specifications, the TVP5150A decoder holds the I2C clock line (SCL) low to indicate the wait

C master. If the I2C master is not designed to check for the I2C clock line held-low condition, then the maximum delays must always be inserted where required. These delays are of variable length; maximum delays are indicated in the following diagram:

Normal register writing address 00h−8Fh (addresses 90h−FFh do not require delays)

Start

Slave address

(B8h)

Ack Subaddress Ack

Data

(XXh)

Ack Wait 64 µs Stop

The 64-µs delay is for all registers that do not require a reinitialization. Delays may be more for some registers.

2.16 Clock Circuits

An internal line-locked PLL generates the system and pixel clocks. A 14.31818-MHz clock is required to drive the PLL. This may be input to the TVP5150A decoder on terminal 5 (XTAL1), or a crystal of 14.31818-MHz fundamental resonant frequency may be connected across terminals 5 and 6 (XTAL2). Figure 2−5 shows the reference clock configurations. For the example crystal circuit shown (a parallel-resonant crystal with 14.31818-MHz fundamental frequency), the external capacitors must have the following relationship:

= CL2 = 2C

where C

STRAY

configurations.

− C

STRAY

is the terminal capacitance with respect to ground. Figure 2−5 shows the reference clock

TVP5150A

XTAL1

XTAL2

14.31818-MHz TTL Clock

TVP5150A

XTAL1

XTAL2

14.31818-MHz Crystal

Figure 2−5. Reference Clock Configurations

2−11

2.17 Genlock Control and RTC

A Genlock control (GLCO) function is provided to support a standard video encoder to synchronize its internal color oscillator for properly reproduced color with unstable timebase sources like VCRs.

The frequency control word of the internal color subcarrier digital control oscillator (DTO) and the subcarrier phase reset bit are transmitted via terminal 23 (GLCO). The frequency control word is a 23-bit binary number . The frequency of the DTO can be calculated from the following equation:

ctrl

dto

sclk

where F SCLK.

is the frequency of the DTO, F

dto

is the 23-bit DTO frequency control, and F

ctrl

is the frequency of the

sclk

2.17.1 TVP5150A Genlock Control Interface

A write of 1 to bit 4 of the chrominance control register at I2C subaddress 1Ah causes the subcarrier DTO phase reset bit to be sent on the next scan line on GLCO. The active low reset bit occurs 7 SCLKs after the transmission of the last bit of DCO frequency control. Upon the transmission of the reset bit, the phase of the TVP5150A internal subcarrier DCO is reset to zero.

A Genlock slave device can be connected to the GLCO terminal and uses the information on GLCO to synchronize its internal color phase DCO to achieve clean line and color lock.

Figure 2−6 shows the timing diagram of the GLCO mode.

SCLK

GLCO

>128 SCLK

Start Bit DCO Reset Bit

MSB

22 21

1 SCLK

23-Bit Frequency Control

LSB

7 SCLK23 SCLK

1 SCLK

2−12

Figure 2−6. GLCO Timing

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