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Macrovision is a trademark of Macrovision Corporation.
O
The TVP5150A device is an ultralow power NTSC/PAL/SECAM video decoder. Available in a space saving 32-pin
TQFP package, the TVP5150A decoder converts NTSC, PAL, and SECAM video signals to 8-bit ITU-R BT.656
format. Discrete syncs are also available. The optimized architecture of the TVP5150A decoder allows for
ultralow-power consumption. The decoder consumes 115 mW of power in typical operation and consumes less than
1 mW in power-down mode, considerably increasing battery life in portable applications. The decoder uses just one
crystal for all supported standards. The TVP5150A decoder can be programmed using an I
decoder uses a 1.8-V supply for its analog and digital supplies, and a 3.3-V supply for its I/O.
The TVP5150A decoder converts baseband analog video into digital YCbCr 4:2:2 component video. Composite and
S-video inputs are supported. The TVP5150A decoder includes one 9-bit analog-to-digital converter (ADC) with 2x
sampling. Sampling is ITU-R BT.601 (27.0 MHz, generated from the 14.31818-MHz crystal or oscillator input) and
is line-locked. The output formats can be 8-bit 4:2:2 or 8-bit ITU-R BT.656 with embedded synchronization.
The TVP5150A decoder utilizes Texas Instruments patented technology for locking to weak, noisy, or unstable
signals. A Genlock/real-time control (RTC) output is generated for synchronizing downstream video encoders.
Complementary 4-line adaptive comb filtering is available for both the luma and chroma data paths to reduce both
cross-luma and cross-chroma artifacts; a chroma trap filter is also available.
2
C serial interface. The
Video characteristics including hue, contrast, brightness, saturation, and sharpness may be programmed using the
industry standard I
2
C serial interface. The TVP5150A decoder generates synchronization, blanking, lock, and clock
signals in addition to digital video outputs. The TVP5150A decoder includes methods for advanced vertical blanking
interval (VBI) data retrieval. The VBI data processor slices, parses, and performs error checking on teletext, closed
caption, and other data in several formats.
The TVP5150A decoder detects copy-protected input signals according to the Macrovision standard and detects
Type 1, 2, 3, and colorstripe pulses.
The main blocks of the TVP5150A decoder include:
•Robust sync detector
•ADC with analog processor
•Y/C separation using 4-line adaptive comb filter
•Chrominance processor
•Luminance processor
•Video clock/timing processor and power-down control
•Output formatter
2
•I
C interface
•VBI data processor
•Macrovision detection for composite and S-video
1.1Features
•Accepts NTSC (M, 4.43), PAL (B, D, G, H, I, M, N), and SECAM (B, D, G, K, K1, L) video data
•Supports ITU-R BT.601 standard sampling
•High-speed 9-bit ADC
•Two composite inputs or one S-video input
ther trademarks are the property of their respective owners.
1−1
•Fully differential CMOS analog preprocessing channels with clamping and automatic gain control (AGC)
for best signal-to-noise (S/N) performance
•Ultralow power consumption: 115 mW typical
•32-pin TQFP package
•Power-down mode: <1 mW
•Brightness, contrast, saturation, hue, and sharpness control through I
2
C
•Complementary 4-line (3-H delay) adaptive comb filters for both cross-luminance and cross-chrominance
noise reduction
•Patented architecture for locking to weak, noisy, or unstable signals
•Single 14.31818-MHz crystal for all standards
•Internal phase-locked loop (PLL) for line-locked clock and sampling
•Subcarrier Genlock output for synchronizing color subcarrier of external encoder
•Standard programmable video output format:
−ITU-R BT.656, 8-bit 4:2:2 with embedded syncs
−8-bit 4:2:2 with discrete syncs
•Macrovision copy protection detection
•Advanced programmable video output formats:
−2x oversampled raw VBI data during active video
−Sliced VBI data during horizontal blanking or active video
•VBI modes supported
−Teletext (NABTS, WST)
−Closed-caption decode with FIFO, and extended data services (EDS)
−Wide screen signaling, video program system, CGMS, vertical interval time code
−Gemstar 1x/2x electronic program guide compatible mode
−Custom configuration mode that allows the user to program the slice engine for unique VBI data signals
•Power-on reset
1.2Product Family
This data manual covers three devices in the TVP5150A product family: the TVP5150APBS, the TVP5150AM1PBS,
and the TVP5150AM1ZQC. The hardware for these three devices is identical. The following software changes are
the differences between these two devices. For the remainder of this document, unless otherwise noted, TVP5150A
refers to all three devices.
•TVP5150APBS
−ROM version 3.21
−SECAM is masked from the autoswitch process in the default mode of register 0x04
−Only supports ITU-R BT656.4 timing
•TVP5150AM1PBS/TVP5150AM1ZQC
−ROM version 4.00
−SECAM is unmasked from the autoswitch process in the default mode of register 0x04
−Addition of register 0x30 to select ITU-R BT656.3 or ITU-R BT656.4 timing
1−2
1.3Applications
The following is a partial list of suggested applications:
•Digital television
•PDA
•Notebook PCs
•Cell phones
•Video recorder/players
•Internet appliances/web pads
•Handheld games
1.4Related Products
•TVP5146 NTSC/PAL/SECAM 4x10-Bit Digital Video Decoder With Macrovision Detection, YPbPr/RGB
Inputs, 5-Line Comb Filter and SCART/Digital RGB Overlay SupportDecoder With Robust Sync Detector,
Literature Number SLES084
1.5Ordering Information
T
A
0°C to 70°CTVP5150APBSTray
0°C to 70°CTVP5150APBSRTape and reel
0°C to 70°CTVP5150AM1PBSTray
0°C to 70°CTVP5150AM1PBSRTape and reel
0°C to 70°CTVP5150AM1ZQCTray
0°C to 70°CTVP5150AM1ZQCRTape and reel
PACKAGED DEVICES
32TQFP-PBS
PACKAGE OPTION
1−3
1.6Functional Block Diagram
MACROVISION
DETECTION
AIP1A
AIP1B
M
U
X
AGC
A/D
Y/C SEPARATION
LUMINANCE
PROCESSING
CHROMINANCE
PROCESSING
VBI / DATA SLICER
OUTPUT
FORMATTER
YOUT[7:0]
YCbCr 8-BIT
4:2:2
SCL
SDA
INTERFACE
XTAL1
XTAL2
PCLK/SCLK
I2C
HOST PROCESSOR
PDN
FID/GLCO
VSYNC/PALI
INTERQ/GPCL/VBLK
LINE AND
CHROMA PLLS
SYNC PROCESSOR
HSYNC
AVID
Figure 1−1. Functional Block Diagram
1−4
1.7Terminal Assignments
NAME
I/O
DESCRIPTION
TQFP PACKAGE
(TOP VIEW)
CH_AVDD
CH_AGND
REFM
3226 25
31 30 29 28 27
AIP1A
AIP1B
PLL_AGND
PLL_AVDD
XTAL1/OSC
XTAL2
AGND
RESETB
1
2
3
4
5
6
7
8
10 11 12 13 1491516
REFP
PDN
INTREQ/GPCL/VBLK
AVID
HSYNC
24
23
22
21
20
19
18
17
VSYNC/PALI
FID/GLCO
SDA
SCL
DVDD
DGND
YOUT0
YOUT1
ZQC PACKAGE
(BOTTOM VIEW)
G
F
E
D
C
B
A
1
23456
7
YOUT6
YOUT5
YOUT4
YOUT3
YOUT2
IO_DVDD
PCLK/SCLK
YOUT7/I2CSEL
1.8Terminal Functions
Table 1−1. Terminal Functions
TERMINAL
NUMBER
PBSZQC
Analog Section
AGND7E1ISubstrate. Connect to analog ground.
AIP1A1A1I
AIP1B2B1I
CH_AGND31A3IAnalog ground
CH_AVDD32A2IAnalog supply. Connect to 1.8-V analog supply.
B2, B3, B6, C4,
NC−
PLL_AGND3C2IPLL ground. Connect to analog ground.
PLL_AVDD4C1IPLL supply. Connect to 1.8-V analog supply.
C5, D3−D6,
E2−E5, F2, F5,
F6
I/ODESCRIPTION
Analog input. Connect to the video analog input via 0.1-µF capacitor . The maximum input range
is 0−0.75 VPP, and may require an attenuator to reduce the input amplitude to the desired level.
If not used, connect to AGND via 0.1-µF capacitor. Refer to Figure 5−1.
Analog input. Connect to the video analog input via 0.1-µF capacitor . The maximum input range
is 0−0.75 VPP, and may require an attenuator to reduce the input amplitude to the desired level.
If not used, connect to AGND via 0.1-µF capacitor. Refer to Figure 5−1.
−No connect
1−5
Table 1−1. Terminal Functions (Continued)
NAME
I/O
DESCRIPTION
TERMINAL
NUMBER
PBS ZQC
Analog Section (continued)
REFM30A4I
REFP29B4IA/D reference supply. Connect to analog ground through 1-µF capacitor. Refer to Figure 5−1.
Digital Section
AVID26A6O
DGND19E6IDigital ground
DVDD20E7IDigital supply. Connect to 1.8-V digital supply
FID/GLCO23C6O
HSYNC25A7OHorizontal synchronization signal
INTREQ/GPCL/
VBLK
IO_DVDD10G2IDigital supply. Connect to 3.3 V.
PCLK/SCLK9G1OSystem clock at either 1x or 2x the frequency of the pixel clock.
PDN28A5I
RESETB8F1I
SCL21D7I/OI2C serial clock (open drain)
SDA22C7I/OI2C serial data (open drain)
VSYNC/PALI24B7O
XTAL1/OSC
XTAL2
YOUT[6:0]
YOUT7/I2CSEL11F3I/O
27B5I/O
56D2D1I
12
13
14
15
16
17
18
I/ODESCRIPTION
A/D reference ground. Connect to analog ground through 1-µF capacitor. Also, it is recommended to
connect directly to REFP through 1-µF capacitor. Refer to Figure 5−1.
Active video indicator. This signal is high during the horizontal active time of the video output. AVID
toggling during vertical blanking intervals is controlled by bit 2 of the active video cropping start pixel
LSB register at address 12h (see Section 2.20.17).
FID: Odd/even field indicator or vertical lock indicator. For the odd/even indicator, a 1 indicates the odd
field.
GLCO: This serial output carries color PLL information. A slave device can decode the information to
allow chroma frequency control from the TVP5150A decoder. Data is transmitted at the SCLK rate in
Genlock mode. In RTC mode, SCLK/4 is used.
INTREQ: Interrupt request output.
GPCL/VBLK: General-purpose control logic. This terminal has two functions:
1. GPCL: General-purpose output. In this mode the state of GPCL is directly programmed via I2C.
2. VBLK: Vertical blank output. In this mode the GPCL terminal indicates the vertical blanking interval
of the output video. The beginning and end times of this signal are programmable via I2C.
Power-down terminal (active low). Puts the decoder in standby mode. Preserves the value of the
registers.
Active-low reset. RESETB can be used only when PDN = 1.
When RESETB is pulled low, it resets all the registers and restarts the internal microprocessor.
VSYNC: Vertical synchronization signal
PALI: PAL line indicator or horizontal lock indicator
For the PAL line indicator:
1 = Indicates a noninverted line
0 = Indicates an inverted line
External clock reference. The user may connect XTAL1 to an oscillator or to one terminal of a crystal
oscillator. The user may connect XTAL2 to the other terminal of the crystal oscillator or not connect
XTAL2 at all. One single 14.31818-MHz crystal or oscillator is needed for ITU-R BT.601 sampling, for
I2CSEL: Determines address for I2C (sampled during reset). A pullup or pulldown register is needed
(>1 kΩ) to program the terminal to the desired address.
1 = Address is 0xBA
0 = Address is 0xB8
YOUT7: MSB of output decoded ITU-R BT.656 output/YCbCr 4:2:2 output.
1−6
2 Functional Description
2.1Analog Front End
The TVP5150A decoder has an analog input channel that accepts two video inputs, which are ac-coupled. The
decoder supports a maximum input voltage range of 0.75 V; therefore, an attenuation of one-half is needed for most
input signals with a peak-to-peak variation of 1.5 V. The maximum parallel termination before the input to the device
is 75 Ω. Please refer to the applications diagram in Figure 5−1 for the recommended configuration. The two analog
input ports can be connected as follows:
•Two selectable composite video inputs or
•One S-video input
An internal clamping circuit restores the ac-coupled video signal to a fixed dc level.
The programmable gain amplifier (PGA) and the AGC circuit work together to make sure that the input signal is
amplified sufficiently to ensure the proper input range for the ADC.
The ADC has 9 bits of resolution and runs at a maximum speed of 27 MHz. The clock input for the ADC comes from
the PLL.
2.2Composite Processing Block Diagram
The composite processing block processes NTSC/PAL/SECAM signals into the YCbCr color space. Figure 2−1
explains the basic architecture of this processing block.
Figure 2−1 illustrates the luminance/chrominance (Y/C) separation process in the TVP5150A decoder. The
composite video is multiplied by subcarrier signals in the quadrature modulator to generate the color difference
signals Cb and Cr . Cb and Cr are then low-pass (LP) filtered to achieve the desired bandwidth and to reduce crosstalk.
An adaptive 4-line comb filter separates CbCr from Y. Chroma is remodulated through another quadrature modulator
and subtracted from the line-delayed composite video to generate luma. Contrast, brightness, hue, saturation, and
sharpness (using the peaking filter) are programmable via I
The Y/C separation is bypassed for S-video input. For S-video, the remodulation path is disabled.
2
C.
2.3Adaptive Comb Filtering
The 4-line comb filter can be selectively bypassed in the luma or chroma path. If the comb filter is bypassed in the
luma path, then chroma notch filters are used. TI’s patented adaptive 4-line comb filter algorithm reduces artifacts
such as hanging dots at color boundaries and detects and properly handles false colors in high frequency luminance
images such as a multiburst pattern or circle pattern.
2.4Color Low-Pass Filter
In some applications, it is desirable to limit the Cb/Cr bandwidth to avoid crosstalk. This is especially true in case of
video signals that have asymmetrical Cb/Cr sidebands. The color LP filters provided limit the bandwidth of the Cb/Cr
signals.
Color LP filters are needed when the comb filtering turns off, due to extreme color transitions in the input image.
Please refer to Sec t ion 2.20.25, Chrominance Control #2 Register, for the response of these filters. The filters have
three options that allow three different frequency responses based on the color frequency characteristics of the input
video.
2−1
Gain Factor
Composite
Composite
Line
Delay
SECAM Luma
SECAM Color
Demodulation
Peak
Detector
−
Cb
LPF ↓ 2
Bandpass
Color
Burst
Accumulator
(Cb)
X
Quadrature
Modulation
4-Line
Adaptive
Comb
Filter
Peaking
Notch
Filter
Notch
Filter
LP
Filter
+Delay
Delay
Contrast
Brightness
Saturation
Adjust
CbCr
Delay
Y
Y
Cb
Cr
Composite
Quadrature
Modulation
Cr
Color
LPF ↓ 2
Burst
Accumulator
(Cr)
LP
Filter
Delay
Figure 2−1. Composite Processing Block Diagram
2.5Luminance Processing
The luma component is derived from the composite signal by subtracting the remodulated chroma information. A line
delay exists in this path to compensate for the line delay in the adaptive comb filter in the color processing chain. The
luma information is then fed into the peaking circuit, which enhances the high frequency components of the signal,
thus improving sharpness.
2.6Chrominance Processing
For NTSC/PAL formats, the color processing begins with a quadrature demodulator. The Cb/Cr signals then pass
through the gain control stage for chroma saturation adjustment. An adaptive comb filter is applied to the demodulated
signals to separate chrominance and eliminate cross-chrominance artifacts. An automatic color killer circuit is also
included in this block. The color killer suppresses the chroma processing when the color burst of the video signal is
weak or not present. The SECAM standard is similar to PAL except for the modulation of color which is FM instead
of QAM.
2−2
2.7Timing Processor
The timing processor is a combination of hardware and software running in the internal microprocessor that serves
to control horizontal lock to the input sync pulse edge, AGC and offset adjustment in the analog front end, vertical
sync detection, and Macrovisiont detection.
2.8VBI Data Processor
The TVP5150A VBI data processor (VDP) slices various data services like teletext (WST, NABTS), closed caption
(CC), wide screen signaling (WSS), etc. These services are acquired by programming the VDP to enable standards
in the VBI. The results are stored in a FIFO and/or registers. The teletext results are stored in a FIFO only. Table 2−1
lists a summary of the types of VBI data supported according to the video standard. It supports ITU-R BT. 601
sampling for each.
Table 2−1. Data Types Supported by the VDP
LINE MODE
REGISTER (D0h−FCh)
BITS [3:0]
0000bxxReserved
0000b1WST SECAM 6Teletext, SECAM
0001bxxReserved
0001b1WST PAL B 6Teletext, PAL, System B
0010bxxReserved
0010b1WST PAL C 6Teletext, PAL, System C
0011bxxReserved
0011b1WST, NTSC B 6Teletext, NTSC, System B
0100bxxReserved
0100b1NABTS, NTSC C 6Teletext, NTSC, System C
0101bxxReserved
0101b1NABTS, NTSC D 6Teletext, NTSC, System D (Japan)
0110bxxReserved
0110b1CC, PAL 6Closed caption PAL
0111bxxReserved
0111b1CC, NTSC 6Closed caption NTSC
1000bxxReserved
1000b1WSS, PAL 6Wide-screen signal, PAL
1001bxxReserved
1001b1WSS, NTSC 6Wide-screen signal, NTSC
1010bxxReserved
1010b1VITC, PAL 6Vertical interval timecode, PAL
At powerup the host interface is required to program the VDP-configuration RAM (VDP-CRAM) contents with the
Ancillary data preamble
1 word
N word
lookup table (see Section 2.20.58). This is done through port address C3h. Each read from or write to this address
will auto increment an internal counter to the next RAM location. To access the VDP-CRAM, the line mode registers
(D0h−FCh) must be programmed with FFh to avoid a conflict with the internal microprocessor and the VDP in both
writing and reading. Full field mode must also be disabled.
Available VBI lines are from line 6 to line 27 of both field 1 and field 2. Each line can be any VBI mode.
Output data is available either through the VBI-FIFO (B0h) or through dedicated registers at 90h−AFh, both of which
are available through the I
2
C port.
2.9VBI FIFO and Ancillary Data in Video Stream
Sliced VBI data can be output as ancillary data in the video stream in the ITU-R BT.656 mode. VBI data is output during
the horizontal blanking period following the line from which the data was retrieved. Table 2−2 shows the header format
and sequence of the ancillary data inserted into the video stream. This format is also used to store any VBI data into
the FIFO. The size of FIFO is 512 bytes. Therefore, the FIFO can store up to 11 lines of teletext data with the NTSC
NABTS standard.
Table 2−2. Ancillary Data Format and Sequence
BYTE
NO.
000000000
111111111
211111111
3NEPEP010DID2DID1DID0Data ID (DID)
4NEPEPF5F4F3F2F1F0Secondary data ID (SDID)
5NEPEPN5N4N3N2N1N0Number of 32 bit data (NN)
6Video line # [7:0]Internal data ID0 (IDID0)
7000Data
Match#1Match#2Video line # [9:8]Internal data ID1 (IDID1)
error
m−1. DataData byte
m. DataData byte
DESCRIPTION
1st word
Nth word
EP:Even parity for D0−D5NEP: Negated even parity
DID: 91h: Sliced data of VBI lines of first field
SDID: This field holds the data format taken from the line mode register of the corresponding line.
NN: Number of Dwords beginning with byte 8 through 4(N+2). This value is the number of Dwords where
IDID0: Transaction video line number [7:0]
2−4
53h: Sliced data of line 24 to end of first field
55h: Sliced data of VBI lines of second field
97h: Sliced data of line 24 to end of second field
each Dword is 4 bytes.
IDID1: Bit 0/1 = Transaction video line number [9:8]
Bit 2 = Match 2 flag
Bit 3 = Match 1 flag
Bit 4 = 1 if an error was detected in the EDC block. 0 if not.
CS:Sum of D0−D7 of DID through last data byte.
Fill byte:Fill bytes make a multiple of 4 bytes from byte 0 to last fill byte. For teletext modes, byte 8 is the sync pattern
byte. Byte 9 is 1. Data (the first data byte).
2.10 Raw Video Data Output
The TVP5150A decoder can output raw A/D video data at 2x sampling rate for external VBI slicing. This is transmitted
as an ancillary data block during the active horizontal portion of the line and during vertical blanking.
2.11 Output Formatter
The YCbCr digital output can be programmed as 8-bit 4:2:2 or 8-bit ITU-R BT.656 parallel interface standard.
Table 2−3. Summary of Line Frequencies, Data Rates, and Pixel Counts
STANDARDS
NTSC (M, 4.43), ITU-R BT.60115.7342685872027.00
PAL (B, D, G, H, I), ITU-R BT.60115.62586472027.00
PAL (M), ITU-R BT.60115.7342685872027.00
PAL (N), ITU-R BT.60115.62586472027.00
SECAM, ITU-R BT.60115.62586472027.00
HORIZONTAL
LINE RATE (kHz)
PIXELS PER
LINE
ACTIVE PIXELS
PER LINE
SCLK FREQUENCY
(MHz)
2.12 Synchronization Signals
External (discrete) syncs are provided via the following signals:
•VSYNC (vertical sync)
•FID/VLK (field indicator or vertical lock indicator)
•GPCL/VBLK (general-purpose I/O or vertical blanking indicator)
•PALI/HLK (PAL switch indicator or horizontal lock indicator)
•HSYNC (horizontal sync)
•AVID (active video indicator)
VSYNC, FID, PALI, and VBLK are software-set and programmable to the SCLK pixel count. This allows any possible
alignment to the internal pixel count and line count. The default settings for a 525-/625-line video output are given
as an example below.
NOTE: AVID rising edge occurs 4 SCLK cycles early when in the ITU-R BT.656 output mode.
Figure 2−3. Horizontal Synchronization Signals
2.13 AVID Cropping
AVID or active video cropping provides a means to decrease bandwidth of the video output. This is accomplished
by horizontally blanking a number of AVID pulses and by vertically blanking a number of lines per frame. The
horizontal AVID cropping is controlled using registers 11h and 12h for start pixels MSB and LSB, respectively.
Registers 13h and 14h provide access to stop pixels MSB and LSB, respectively. The vertical AVID cropping is
controlled using the vertical blanking (VBLK) start and stop registers at addresses 18h and 19h. Figure 2−4 shows
an AVID application.
2−7
VBLK Stop
VBLK Start
Active Video Area
AVID Cropped
Area
AVID Start
VSYNC
HSYNC
AVID Stop
Figure 2−4. AVID Application
2.14 Embedded Syncs
Standards with embedded syncs insert SAV and EAV codes into the datastream at the beginning and end of horizontal
blanking. These codes contain the V and F bits which also define vertical timing. F and V change on EAV . Table 2−4
gives the format of the SAV and EAV codes.
H equals 1 always indicates EAV. H equals 0 always indicates SAV. The alignment of V and F to the line and field
counter varies depending on the standard. Please refer to ITU-R BT.656 for more information on embedded syncs.
The P bits are protection bits:
P3 = V xor H
P2 = F xor H
P1 = F xor V
P0 = F xor V xor H
Table 2−4. EAV and SAV Sequence
8-BIT DATA
D7 (MSB)D6D5D4D3D2D1D0
Preamble11111111
Preamble00000000
Preamble00000000
Status word1FVHP3P2P1P0
2−8
2.15 I2C Host Interface
The I2C standard consists of two signals, serial input/output data line (SDA) and input/output clock line (SCL), which
carry information between the devices connected to the bus. A third signal (I2CSEL) is used for slave address
selection. Although the I
Both SDA and SCL must be connected to a positive supply voltage via a pullup resistor. When the bus is free, both
lines are high. The slave address select terminal (I2CSEL) enables the use of two TVP5150A decoders tied to the
2
same I
C bus. At power up, the status of the I2CSEL is polled. Depending on the write and read addresses to be used
for the TVP5150A decoder, it can either be pulled low or high through a resistor. This terminal is multiplexed with
YOUT7 and hence must not be tied directly to ground or IO_DVDD. Table 2−6 summarizes the terminal functions of
2
the I
C-mode host interface.
Data transfer rate on the bus is up to 400 kbits/s. The number of interfaces connected to the bus is dependent on
the bus capacitance limit of 400 pF. The data on the SDA line must be stable during the high period of the SCL except
for start and stop conditions. The high or low state of the data line can only change with the clock signal on the SCL
line being low. A high-to-low transition on the SDA line while the SCL is high indicates an I
low-to-high transition on the SDA line while the SCL is high indicates an I
2
C system can be multimastered, the TVP5150A decoder functions as a slave device only.
Table 2−5. Write Address Selection
I2CSELWRITE ADDRESS
0B8h
1BAh
T able 2−6. I2C Terminal Description
SIGNALTYPEDESCRIPTION
I2CSEL (YOUT7)ISlave address selection
SCLI/O (open drain)Input/output clock line
SDAI/O (open drain)Input/output data line
2
2
C stop condition.
C start condition. A
Every byte placed on the SDA must be 8 bits long. The number of bytes which can be transferred is unrestricted. Each
byte must be followed by an acknowledge bit. The acknowledge-related clock pulse is generated by the I
2
C master.
2.15.1 I2C Write Operation
Data transfers occur utilizing the following illustrated formats.
2
C master initiates a write operation to the TVP5150A decoder by generating a start condition (S) followed by
An I
the TVP5150A I
receiving an acknowledge from the TVP5150A decoder, the master presents the subaddress of the register, or the
first of a block of registers it wants to write, followed by one or more bytes of data, MSB first. The TVP5150A decoder
acknowledges each byte after completion of each transfer. The I
generating a stop condition (P).
C address (as shown below), in MSB first bit order, followed by a 0 to indicate a write cycle. After
2
C master terminates the write operation by
2−9
Step 5
I2C Acknowledge (slave)A
Step 676543210
I2C Write data (master)DataDataDataDataDataDataDataData
†
Step 7
I2C Acknowledge (slave)A
Step 80
I2C Stop (master)P
†
Repeat steps 6 and 7 until all data have been written.
9
9
2.15.2 I2C Read Operation
The read operation consists of two phases. The first phase is the address phase. In this phase, an I2C master initiates
a write operation to the TVP5150A decoder by generating a start condition (S) followed by the TVP5150A I
2
C address,
in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving acknowledges from the TVP5150A
decoder, the master presents the subaddress of the register or the first of a block of registers it wants to read. After
the cycle is acknowledged, the master terminates the cycle immediately by generating a stop condition (P).
Table 2−7. Read Address Selection
I2CSELREAD ADDRESS
0B9h
1BBh
The second phase is the data phase. In this phase, an I2C master initiates a read operation to the TVP5150A decoder
by generating a start condition followed by the TVP5150A I
first bit order, followed by a 1 to indicate a read cycle. After an acknowledge from the TVP5150A decoder, the I
master receives one or more bytes of data from the TVP5150A decoder. The I
2
C address (as shown below for a read operation), in MSB
2
C master acknowledges the transfer
2
at the end of each byte. After the last data byte desired has been transferred from the TVP5150A decoder to the
master, the master generates a not acknowledge followed by a stop.
I2C Read data (slave)DataDataDataDataDataDataDataData
†
Step 11
I2C Not acknowledge (master)A
Step 120
I2C Stop (master)P
†
Repeat steps 10 and 11 for all bytes read. Master does not acknowledge the last read data received.
9
2.15.2.3I2C Timing Requirements
The TVP5150A decoder requires delays in the I2C accesses to accommodate its internal processor’s timing. In
accordance with I
period to the I
2
C specifications, the TVP5150A decoder holds the I2C clock line (SCL) low to indicate the wait
2
C master. If the I2C master is not designed to check for the I2C clock line held-low condition, then the
maximum delays must always be inserted where required. These delays are of variable length; maximum delays are
indicated in the following diagram:
Normal register writing address 00h−8Fh (addresses 90h−FFh do not require delays)
Start
Slave address
(B8h)
AckSubaddressAck
Data
(XXh)
AckWait 64 µsStop
The 64-µs delay is for all registers that do not require a reinitialization. Delays may be more for some registers.
2.16 Clock Circuits
An internal line-locked PLL generates the system and pixel clocks. A 14.31818-MHz clock is required to drive the PLL.
This may be input to the TVP5150A decoder on terminal 5 (XTAL1), or a crystal of 14.31818-MHz fundamental
resonant frequency may be connected across terminals 5 and 6 (XTAL2). Figure 2−5 shows the reference clock
configurations. For the example crystal circuit shown (a parallel-resonant crystal with 14.31818-MHz fundamental
frequency), the external capacitors must have the following relationship:
C
= CL2 = 2C
L1
where C
STRAY
configurations.
− C
L
STRAY
,
is the terminal capacitance with respect to ground. Figure 2−5 shows the reference clock
TVP5150A
XTAL1
XTAL2
5
6
14.31818-MHz
TTL Clock
TVP5150A
XTAL1
XTAL2
14.31818-MHz
Crystal
5
6
C
L1
C
L2
Figure 2−5. Reference Clock Configurations
2−11
2.17 Genlock Control and RTC
A Genlock control (GLCO) function is provided to support a standard video encoder to synchronize its internal color
oscillator for properly reproduced color with unstable timebase sources like VCRs.
The frequency control word of the internal color subcarrier digital control oscillator (DTO) and the subcarrier phase
reset bit are transmitted via terminal 23 (GLCO). The frequency control word is a 23-bit binary number . The frequency
of the DTO can be calculated from the following equation:
F
ctrl
F
dto
=
x
F
23
sclk
2
where F
SCLK.
is the frequency of the DTO, F
dto
is the 23-bit DTO frequency control, and F
ctrl
is the frequency of the
sclk
2.17.1 TVP5150A Genlock Control Interface
A write of 1 to bit 4 of the chrominance control register at I2C subaddress 1Ah causes the subcarrier DTO phase reset
bit to be sent on the next scan line on GLCO. The active low reset bit occurs 7 SCLKs after the transmission of the
last bit of DCO frequency control. Upon the transmission of the reset bit, the phase of the TVP5150A internal
subcarrier DCO is reset to zero.
A Genlock slave device can be connected to the GLCO terminal and uses the information on GLCO to synchronize
its internal color phase DCO to achieve clean line and color lock.
Figure 2−6 shows the timing diagram of the GLCO mode.
SCLK
GLCO
>128 SCLK
Start BitDCO Reset Bit
MSB
2221
1 SCLK
23-Bit Frequency Control
LSB
0
7 SCLK23 SCLK
1 SCLK
2−12
Figure 2−6. GLCO Timing
2.17.2 RTC Mode
Figure 2−7 shows the timing diagram of the RTC mode. Clock rate for the RTC mode is 4 times slower than the GLCO
clock rate. For PLL frequency control, the upper 22 bits are used. Each frequency control bit is 2 clock cycles long.
The active low reset bit occurs 6 CLKs after the transmission of the last bit of PLL frequency control.
RTC
128 CLK
Start
Bit
16 CLK
2 CLK
M
S
B
210
44 CLK
22-Bit Fsc Frequency Control
L
S
B
2 CLK
1 CLK
PAL
Switch
3 CLK
1 CLK
Reset
Bit
Figure 2−7. RTC Timing
2.18 Reset and Power Down
Terminals 8 (RESETB) and 28 (PDN) work together to put the TVP5150A decoder into one of the two modes.
Table 2−8 shows the configuration.
Table 2−8. Reset and Power Down Modes
PDNRESETBCONFIGURATION
00Reserved (unknown state)
01Powers down the decoder
10Resets the decoder
11Normal operation
2.19 Internal Control Registers
The TVP5150A decoder is initialized and controlled by a set of internal registers which set all device operating
parameters. Communication between the external controller and the TVP5150A decoder is through I
shows the summary of these registers. The reserved registers must not be written. Reserved bits in the defined
registers must be written with 0s, unless otherwise noted. The detailed programming information of each register is
described in the following sections.
2
C. Table 2−9
2−13
Table 2−9. Registers Summary
REGISTER FUNCTIONADDRESSDEFAULTR/W
Video input source selection #100h00hR/W
Analog channel controls01h15hR/W
Operation mode controls02h00hR/W
Miscellaneous controls03h01hR/W
Autoswitch mask:
TVP5150A04hFChR/W
TVP5150AM104hDChR/W
Reserved05h00hR/W
Color killer threshold control06h10hR/W
Luminance processing control #107h60hR/W
Luminance processing control #208h00hR/W
Brightness control09h80hR/W
Color saturation control0Ah80hR/W
Hue control0Bh00hR/W
Contrast control0Ch80hR/W
Outputs and data rates select0Dh47hR/W
Luminance processing control #30Eh00hR/W
Configuration shared pins0Fh08hR/W
Reserved10h
Active video cropping start MSB11h00hR/W
Active video cropping start LSB12h00hR/W
Active video cropping stop MSB13h00hR/W
Active video cropping stop LSB14h00hR/W
Genlock/RTC15h01hR/W
Horizontal sync start16h80hR/W
Reserved17h
Vertical blanking start18h00hR/W
Vertical blanking stop19h00hR/W
Chrominance processing control #11Ah0ChR/W
Chrominance processing control #21Bh14hR/W
Interrupt reset register B1Ch00hR/W
Interrupt enable register B1Dh00hR/W
Interrupt configuration register B1Eh00hR/W
Reserved1Fh−27h
Video standard28h00hR/W
Reserved29h−2Bh
Cb gain factor2ChR
Cr gain factor2DhR
Macrovision on counter2Eh0FhR/W
Macrovision off counter2Fh01hR/W
656 revision select (TVP5150AM1 only)30h00hR/W
2−14
R = Read only
W = Write only
R/W = Read and write
Table 2−9. Registers Summary (Continued)
REGISTER FUNCTIONADDRESSDEFAULTR/W
Reserved31h−7Fh
MSB of device ID80h51hR
LSB of device ID81h50hR
ROM major version:
TVP5150A82h03hR
TVP5150AM182h04hR
ROM minor version:
TVP5150A83h21hR
TVP5150AM183h00hR
Vertical line count MSB84hR
Vertical line count LSB85hR
Interrupt status register B86hR
Interrupt active register B87hR
Status register #188hR
Status register #289hR
Status register #38AhR
Status register #48BhR
Status register #58ChR
Reserved8Dh−8Fh
Closed caption data registers90h−93hR
WSS data registers94h−99hR
VPS data registers9Ah−A6hR
VITC data registersA7h−AFhR
VBI FIFO read dataB0hR
Teletext filter 1B1h−B5h00hR/W
Teletext filter 2B6h−BAh00hR/W
Teletext filter enableBBh00hR/W
ReservedBCh−BFh
Interrupt status register AC0h00hR/W
Interrupt enable register AC1h00hR/W
Interrupt configurationC2h04hR/W
VDP configuration RAM dataC3hDChR/W
Configuration RAM address low byteC4h0FhR/W
Configuration RAM address high byteC5h00hR/W
VDP status registerC6hR
FIFO word countC7hR
FIFO interrupt thresholdC8h80hR/W
FIFO resetC9h00hW
Line number interruptCAh00hR/W
Pixel alignment register low byteCBh4EhR/W
Pixel alignment register high byteCCh00hR/W
R = Read only
W = Write only
R/W = Read and write
2−15
Table 2−9. Registers Summary (Continued)
INPUT(S) SELECTED
REGISTER FUNCTIONADDRESSDEFAULTR/W
FIFO output controlCDh01hR/W
ReservedCEh
Full field enableCFh00hR/W
Line mode registers
Full field mode registerFCh7FhR/W
ReservedFDh−FFh
D0h
D1h−FBh
00h
FFh
R/W
R = Read only
W = Write only
R/W = Read and write
2.20 Register Definitions
2.20.1 Video Input Source Selection #1 Register
Address00h
Default00h
76543210
ReservedBlack outputReserved
Channel 1 source
selection
S-video selection
Channel 1 source selection:
0 = AIP1A selected (default)
1 = AIP1B selected
Black output:
0 = Normal operation (default)
1 = Force black screen output (outputs synchronized)
a. Forced to 10h in normal mode
b. Forced to 01h in extended mode
Table 2−10. Analog Channel and Video Mode Selection
ADDRESS 00
BIT 1BIT 0
CompositeAIP1A (default)00
AIP1B10
S-VideoAIP1A (luma), AIP1B (chroma)x1
2−16
2.20.2 Analog Channel Controls Register
Address01h
Default15h
76543210
Reserved1Automatic offset controlAutomatic gain control
Automatic offset control:
00 = Disabled
01 = Automatic offset enabled (default)
10 = Reserved
11 = Offset level frozen to the previously set value
Automatic gain control (AGC):
00 = Disabled (fixed gain value)
01 = AGC enabled (default)
10 = Reserved
11 = AGC frozen to the previously set value
2.20.3 Operation Mode Controls Register
Address02h
Default00h
76543210
Reserved
Color burst
reference enable
TV/VCR mode
Color burst reference enable
0 = Color burst reference for AGC disabled (default)
1 = Color burst reference for AGC enabled
TV/VCR mode
00 = Automatic mode determined by the internal detection circuit. (default)
01 = Reserved
10 = VCR (nonstandard video) mode
11 = TV (standard video) mode
With automatic detection enabled, unstable or nonstandard syncs on the input video forces the detector into the VCR
mode. This turns off the comb filters and turns on the chroma trap filter.
White peak disable
0 = White peak protection enabled (default)
1 = White peak protection disabled
Color subcarrier PLL frozen:
0 = Color subcarrier PLL increments by the internally generated phase increment. (default)
0 = Normal operation (default)
1 = Power down mode. A/Ds are turned off and internal clocks are reduced to minimum.
White peak
disable
Color subcarrier
PLL frozen
Luma peak
disable
Power down mode
2−17
2.20.4 Miscellaneous Control Register
Address03h
Default01h
76543210
HSYNC, VSYNC/PALI,
AVID, FID/GLCO
output enable
Vertical blanking
on/off
Clock output
enable
VBKOGPCL pin
GPCL output
enable
Lock status
(HVLK)
YCbCr output
enable (TVPOE)
VBKO (pin 27) function select:
0 = GPCL (default)
1 = VBLK
GPCL (data is output based on state of bit 5):
0 = GPCL outputs 0 (default)
1 = GPCL outputs 1
GPCL output enable:
0 = GPCL is inactive (default)
1 = GPCL is output
NOTE: GPCL must not be programmed to be 0 when register 0Fh bit 1 is 1 (GPCL/VBLK).
Lock status (HVLK) (configured along with register 0Fh, please see Figure 2−8 for the relationship between the
configuration shared pins):
0 = Terminal VSYNC/P ALI outputs the PAL indicator (PALI) signal and terminal FID/GLCO outputs the field
ID (FID) signal (default) (if terminals are configured to output PALI and FID in register 0Fh)
1 = Terminal VSYNC/PALI outputs the horizontal lock indicator (HLK) and terminal FID outputs the vertical
lock indicator (VLK) (if terminals are configured to output PALI and FID in register 0Fh)
These are additional functionalities that are provided for ease of use.
YCbCr output enable:
0 = YOUT[7:0] high impedance (default)
1 = YOUT[7:0] active
HSYNC, VSYNC/PALI, active video indicator (AVID), and FID/GLCO output enables:
0 = HSYNC, VSYNC/PALI, AVID, and FID/GLCO are high-impedance (default).
1 = HSYNC, VSYNC/PALI, AVID, and FID/GLCO are active.
Vertical blanking on/off:
0 = Vertical blanking (VBLK) off (default)
1 = Vertical blanking (VBLK) on
Clock output enable:
0 = SCLK output is high impedance.
1 = SCLK output is enabled (default).
NOTE: When enabling the outputs, ensure the clock output is not accidently disabled.
Table 2−11. Digital Output Control
Register 03h, Bit 3
(TVPOE)
2−18
Register C2h, Bit 2
(VDPOE)
0XHigh impedance After both YCbCr output enable bits are programmed.
X0High impedance After both YCbCr output enable bits are programmed.
11ActiveAfter both YCbCr output enable bits are programmed.
YCbCr OutputNotes
NOTE: VDPOE default is 1 and TVPOE default is 0.
4
0F(Bit 2)
3
0F(Bit 4)
9
LOCK24B
VSYNC/PALI
HLK0
HVLK1
1HVLK
0VLK
0F(Bit 6)
LOCK23
M
HLK/HVLK
U
X
M
VLK/HVLK1
U
X
PALI0
FID
03(Bit 4)
HVLK
VSYNC0
M
PALI/HLK/HVLK
U
1
X
M
FID/VLK/HVLK0
U
0
X
GLCO
M
U
1
X
M
U
1
X
0F(Bit 3)
FID/GLCO
VSYNC/PALI/HLK/HVLK
FID/GLCO/VLK/HVLK
Pin 2
Pin 2
VBLK1
GPCL
M
VBLK/GPCL1
0
03(Bit 7)
VBKO
U
X
INTREQ
INTREQ/GPCL/VBLK
0
0F(Bit 1)
M
INTREQ/GPCL//VBLK
U
X
Pin 27
SCLK0
PCLK
Figure 2−8. Configuration Shared Pins
NOTE: Also refer to the configuration shared pins register at subaddress 0Fh.
M
U
1
X
0F(Bit 0)
SCLK/PCLK
PCLK/SCLK
Pin
2−19
2.20.5 Autoswitch Mask Register
Address04h
DeviceTVP5150ATVP5150AM1
DefaultFChDCh
76543210
ReservedSEC_OFFN443_OFFPALN_OFFPALM_OFFReserved
N443_OFF:
0 = NTSC443 is unmasked from the autoswitch process. Autoswitch does switch to NTSC443.
1 = NTSC443 is masked from the autoswitch process. Autoswitch does not switch to NTSC443. (default)
PALN_OFF:
0 = PAL-N is unmasked from the autoswitch process. Autoswitch does switch to PAL-N.
1 = PAL-N is masked from the autoswitch process. Autoswitch does not switch to PAL-N. (default)
PALM_OFF:
0 = PAL-M is unmasked from the autoswitch process. Autoswitch does switch to PAL-M.
1 = PAL-M is masked from the autoswitch process. Autoswitch does not switch to PAL-M. (default)
SEC_OFF:
0 = SECAM is unmasked from the autoswitch process. Autoswitch does switch to SECAM. (default for
TVP5150AM1)
1 = SECAM is masked from the autoswitch process. Autoswitch does not switch to SECAM. (default for
TVP5150A)
2.20.6 Color Killer Threshold Control Register
Address06h
Default10h
76543210
ReservedAutomatic color killerColor killer threshold
Automatic color killer:
00 = Automatic mode (default)
01 = Reserved
10 = Color killer enabled, the CbCr terminals are forced to a zero color state.
11 = Color killer disabled
Color killer threshold:
11111 = −30 dB (minimum)
10000 = −24 dB (default)
00000 = −18 dB (maximum)
2−20
2.20.7 Luminance Processing Control #1 Register
Address07h
Default60h
76543210
2x luma output
enable
Pedestal not present
2x luma output enable:
0 = Output depends on bit 4, luminance bypass enabled during vertical blanking (default).
1 = Outputs 2x luma samples during the entire frame. This bit takes precedence over bit 4.
Pedestal not present:
0 = 7.5 IRE pedestal is present on the analog video input signal.
1 = Pedestal is not present on the analog video input signal (default).
Disable raw header:
0 = Insert 656 ancillary headers for raw data
1 = Disable 656 ancillary headers and instead force dummy ones (0x40) (default)
Luminance bypass enabled during vertical blanking:
0 = Disabled. If bit 7, 2x luma output enable, is 0, then normal luminance processing occurs and YCbCr
samples are output during the entire frame (default).
1 = Enabled. If bit 7, 2x luma output enable, is 0, then normal luminance processing occurs and YCbCr
samples are output during V ACTIVE and 2x luma samples are output during VBLK. Luminance bypass
occurs for the duration of the vertical blanking as defined by registers 18h and 19h.
Disable raw
header
Luma bypass enabled
during vertical blanking
Luminance signal delay with respect to
chrominance signal
Luminance bypass occurs for the duration of the vertical blanking as defined by registers 18h and 19h.
Luma signal delay with respect to chroma signal in pixel clock increments (range −8 to +7 pixel clocks):
0 = ITU-R BT.601 coding range (Y ranges from 16 to 235. U and V range from 16 to 240)
1 = Extended coding range (Y, U, and V range from 1 to 254) (default)
11 = Notch 3
Luminance filter select [1:0] selects one of the four chroma trap (notch) filters to produce luminance signal by
removing the chrominance signal from the composite video signal. The stopband of the chroma trap filter is centered
at the chroma subcarrier frequency with stopband bandwidth controlled by the two control bits. Please refer to the
following table for the stopband bandwidths. The WCF bit is controlled in the chrominance control #2 register, see
Section 2.20.25.
Please see Figure 2−8 for the relationship between the configuration shared pins.
2.20.16 Active Video Cropping Start Pixel MSB Register
Address11h
Default00h
76543210
AVID start pixel MSB [7:0]
Active video cropping start pixel MSB [9:2], set this register first before setting register 12h. The TVP5150A decoder
updates the AVID start values only when register 12h is written to. This start pixel value is relative to the default values
of the AVID start pixel.
2−25
2.20.17 Active Video Cropping Start Pixel LSB Register
Address12h
Default00h
76543210
ReservedAVID activeAVID start pixel LSB [1:0]
AVID active:
0 = AVID out active in VBLK (default)
1 = AVID out inactive in VBLK
Active video cropping start pixel LSB [1:0]: The TVP5150A decoder updates the AVID start values only when this
register is written to.
AVID start [9:0] (combined registers 11h and 12h):
01 1111 1111 = 511
00 0000 0001 = 1
00 0000 0000 = 0 (default)
11 1111 1111 = −1
10 0000 0000 = −512
2.20.18 Active Video Cropping Stop Pixel MSB Register
Address13h
Default00h
76543210
AVID stop pixel MSB
Active video cropping stop pixel MSB [9:2], set this register first before setting the register 14h. The TVP5150A
decoder updates the AVID stop values only when register 14h is written to. This stop pixel value is relative to the
default values of the AVID stop pixel.
2.20.19 Active Video Cropping Stop Pixel LSB Register
Address14h
Default00h
76543210
ReservedAVID stop pixel LSB
Active video cropping stop pixel LSB [1:0]: The number of pixels of active video must be an even number. The
TVP5150A decoder updates the AVID stop values only when this register is written to.
AVID stop [9:0] (combined registers 13h and 14h):
01 1111 1111 = 511
00 0000 0001 = 1
00 0000 0000 = 0 (default) (see Figure 2−3 and Figure 2−4)
11 1111 1111 = −1
10 0000 0000 = −512
2−26
2.20.20 Genlock and RTC Register
0
0
0
1
1
0
Address15h
Default01h
76543210
ReservedF/V bit controlReservedGLCO/RTC
F/V bit control
BIT 5BIT 4NUMBER OF LINESF BITV BIT
StandardITU-R BT.656ITU-R BT.656
00
11Illegal
GLCO/RTC. The following table helps in understanding the different modes.
Nonstandard evenForce to 1Switch at field boundary
Nonstandard oddTogglesSwitch at field boundary
StandardITU-R BT.656ITU-R BT.656
NonstandardTogglesSwitch at field boundary
StandardITU-R BT.656ITU-R BT.656
NonstandardPulse modeSwitch at field boundary
All other values are reserved.
Figure 2−6 shows the timing of GLCO and Figure 2−7 shows the timing of RTC.
2−27
2.20.21 Horizontal Sync (HSYNC) Start Register
BT.656 EAV Code
H
hb
BT.656 SAV Code
Address16h
Default80h
76543210
HSYNC start
HSYNC start:
1111 1111 = −127 x 4 pixel clocks
1111 1110 = −126 x 4 pixel clocks
1000 0001 = −1 x 4 pixel clocks
1000 0000 = 0 pixel clocks (default)
0111 1111 = 1 x 4 pixel clocks
0111 1110 = 2 x 4 pixel clocks
0000 0000 = 128 x 4 pixel clocks
U
YOUT
[7:0]
SYNC
Y V Y FF0000XY801
0
8010FF0000XYU Y
AVID
128 SCLK
Start of
Digital Line
N
hbhs
N
Start of Digital
Active Line
Figure 2−9. Horizontal Sync
Table 2−12. Clock Delays (SCLKs)
STANDARDN
NTSC16272
PAL20284
SECAM40280
hbhs
N
hb
Detailed timing information is also available in Section 2.12, Synchronization Signals.
2−28
2.20.22 Vertical Blanking Start Register
Address18h
Default00h
76543210
Vertical blanking start
Vertical blanking (VBLK) start:
0111 1111 = 127 lines after start of vertical blanking interval
0000 0001 = 1 line after start of vertical blanking interval
0000 0000 = Same time as start of vertical blanking interval (default) (see Figure 2−2)
1111 1111 = 1 line before start of vertical blanking interval
1000 0000 = 128 lines before start of vertical blanking interval
Vertical blanking is adjustable with respect to the standard vertical blanking intervals. The setting in this register
determines the timing of the GPCL/VBLK signal when it is configured to output vertical blank (see register 03h). The
setting in this register also determines the duration of the luma bypass function (see register 07h).
2.20.23 Vertical Blanking Stop Register
Address19h
Default00h
76543210
Vertical blanking stop
Vertical blanking (VBLK) stop:
0111 1111 = 127 lines after stop of vertical blanking interval
0000 0001 = 1 line after stop of vertical blanking interval
0000 0000 = Same time as stop of vertical blanking interval (default) (see Figure 2−2)
1111 1111 = 1 line before stop of vertical blanking interval
1000 0000 = 128 lines before stop of vertical blanking interval
Vertical blanking is adjustable with respect to the standard vertical blanking intervals. The setting in this register
determines the timing of the GPCL/VBLK signal when it is configured to output vertical blank (see register 03h). The
setting in this register also determines the duration of the luma bypass function (see register 07h).
2−29
2.20.24 Chrominance Control #1 Register
Address1Ah
Default0Ch
76543210
ReservedColor PLL reset
Chrominance adaptive
comb filter enable (ACE)
Color PLL reset:
0 = Color PLL not reset (default)
1 = Color PLL reset
Color PLL phase is reset to zero and the color PLL reset bit then immediately returns to zero. When this bit is set,
the subcarrier PLL phase reset bit is transmitted on terminal 23 (GLCO) on the next line (NTSC or PAL).
Chrominance adaptive comb filter enable (ACE):
Interrupt reset register B is used by the external processor to reset the interrupt status bits in interrupt status
register B. Bits loaded with a 1 allow the corresponding interrupt status bit to reset to 0. Bits loaded with a 0 have no
effect on the interrupt status bits.
Software initialization reset:
0 = No effect (default)
1 = Reset software initialization bit
Macrovision detect changed reset:
0 = No effect (default)
1 = Reset Macrovision detect changed bit
Field rate changed reset:
0 = No effect (default)
1 = Reset field rate changed bit
Macrovision
detect changed
reset
Reserved
Field rate
changed reset
Line alternation
changed reset
Color lock
changed reset
H/V lock
changed reset
TV/VCR
changed reset
Line alternation changed reset:
0 = No effect (default)
1 = Reset line alternation changed bit
Color lock changed reset:
0 = No effect (default)
1 = Reset color lock changed bit
H/V lock changed reset:
0 = No effect (default)
1 = Reset H/V lock changed bit
TV/VCR changed reset [TV/VCR mode is determined by counting the total number of lines/frame. The mode switches
to VCR for nonstandard number of lines]:
0 = No effect (default)
1 = Reset TV/VCR changed bit
2−32
2.20.27 Interrupt Enable Register B
Address1Dh
Default00h
76543210
Software initialization
occurred enable
Interrupt enable register B is used by the external processor to mask unnecessary interrupt sources for interrupt B.
Bits loaded with a 1 allow the corresponding interrupt condition to generate an interrupt on the external pin.
Conversely, bits loaded with 0s mask the corresponding interrupt condition from generating an interrupt on the
external pin. This register only affects the external pin, it does not affect the bits in the interrupt status register. A given
condition can set the appropriate bit in the status register and not cause an interrupt on the external pin. To determine
if this device is driving the interrupt pin either AND interrupt status register B with interrupt enable register B or check
the state of interrupt B in the interrupt B active register.
Software initialization occurred enable:
0 = Disabled (default)
1 = Enabled
Macrovision detect changed:
0 = Disabled (default)
1 = Enabled
Field rate changed:
Macrovision
detect changed
Reserved
Field rate
changed
Line alternation
changed
Color lock
changed
H/V lock
changed
TV/VCR
changed
0 = Disabled (default)
1 = Enabled
Line alternation changed:
0 = Disabled (default)
1 = Enabled
Color lock changed:
0 = Disabled (default)
1 = Enabled
H/V lock changed:
0 = Disabled (default)
1 = Enabled
TV/VCR changed:
0 = Disabled (default)
1 = Enabled
2−33
2.20.28 Interrupt Configuration Register B
Address1Eh
Default00h
76543210
ReservedInterrupt polarity B
Interrupt polarity B:
0 = Interrupt B is active low (default).
1 = Interrupt B is active high.
Interrupt polarity B must be same as interrupt polarity A bit at bit 0 of the interrupt configuration register A at address
C2h.
Interrupt configuration register B is used to configure the polarity of interrupt B on the external interrupt pin. When
the interrupt B is configured for active low, the pin is driven low when active and high-impedance when inactive
(open-drain). Conversely , when the interrupt B is configured for active high, it is driven high for active and driven low
for inactive.
2.20.29 Video Standard Register
Address28h
Default00h
76543210
ReservedVideo standard
Video standard:
0000 = Autoswitch mode (default)
0001 = Reserved
0010 = (M) NTSC ITU-R BT.601
0011 = Reserved
0100 = (B, G, H, I, N) PAL ITU-R BT.601
0101 = Reserved
0110 = (M) PAL ITU-R BT.601
0111 = Reserved
1000 = (Combination-N) PAL ITU-R BT.601
1001 = Reserved
1010 = NTSC 4.43 ITU-R BT.601
1011 = Reserved
1100 = SECAM ITU-R BT.601
With the autoswitch code running, the user can force the device to operate in a particular video standard mode and
sample rate by writing the appropriate value into this register.
2.20.30 Cb Gain Factor Register
Address2Ch
76543210
Cb gain factor
This is a read-only register that provides the gain applied to the Cb in the YCbCr data stream.
2−34
2.20.31 Cr Gain Factor Register
Address2Dh
76543210
Cr gain factor
This is a read-only register that provides the gain applied to the Cr in the YCbCr data stream.
2.20.32 Macrovision On Counter Register
Address2Eh
Default0Fh
76543210
Macrovision on counter
This register allows the user to determine how many consecutive frames in which the Macrovision AGC pulses have
to be detected before the decoder decides that the Macrovision AGC pulses are present.
2.20.33 Macrovision Off Counter Register
Address2Fh
Default01h
76543210
Macrovision off counter
This register allows the user to determine how many consecutive frames in which the Macrovision AGC pulses are
not detected before the decoder decides that the Macrovision AGC pulses are not present.
2.20.34 656 Revision Select Register
NOTE: This register exists only for the TVP5150AM1.
Address30h
Default00h
76543210
Reserved
656 revision
select
656 revision select:
0 = Adheres to ITU-R BT.656.4 timing (default for TVP5150AM1, this is the only option for TVP5150A).
1 = Adheres to ITU-R BT.656.3 timing.
2.20.35 MSB of Device ID Register
Address80h
Default51h
76543210
MSB of device ID
This register identifies the MSB of the device ID. Value = 0x51.
2−35
2.20.36 LSB of Device ID Register
Address81h
Default50h
76543210
LSB of device ID
This register identifies the LSB of the device ID. Value = 0x50.
2.20.37 ROM Major Version Register
Address82h
DeviceTVP5150ATVP5150AM1
Default03h04h
76543210
†
†
This register can contain a number from 0x01 to 0xFF.
ROM major version
Value = 0x03 for TVP5150A
Value = 0x04 for TVP5150AM1
2.20.38 ROM Minor Version Register
Address83h
DeviceTVP5150ATVP5150AM1
Default21h00h
76543210
†
†
This register can contain a number from 0x01 to 0xFF.
ROM minor version
Value = 0x21 for TVP5150A
Value = 0x00 for TVP5150AM1
2.20.39 Vertical Line Count MSB Register
Address84h
76543210
ReservedVertical line count MSB
Vertical line count bits [9:8]
2.20.40 Vertical Line Count LSB Register
Address85h
76543210
Vertical line count LSB
Vertical line count bits [7:0]
Registers 84h and 85h can be read and combined to extract the detected number of lines per frame. This can be used
with nonstandard video signals such as a VCR in fast-forward or rewind modes to synchronize the downstream video
circuitry.
2−36
2.20.41 Interrupt Status Register B
Address86h
76543210
Software
initialization
Software initialization:
Macrovision detect changed:
Command ready:
Field rate changed:
Line alternation changed:
Macrovision detect
changed
Command
ready
Field rate
changed
Line alternation
changed
0 = Software initialization is not ready (default).
1 = Software initialization is ready.
0 = Macrovision detect status has not changed (default).
1 = Macrovision detect status has changed.
0 = TVP5150A is not ready to accept a new command (default).
1 = TVP5150A is ready to accept a new command.
0 = Field rate has not changed (default).
1 = Field rate has changed.
0 = Line alteration has not changed (default).
1 = Line alternation has changed.
Color lock
changed
H/V lock
changed
TV/VCR
changed
Color lock changed:
0 = Color lock status has not changed (default).
1 = Color lock status has changed.
H/V lock changed:
0 = H/V lock status has not changed (default).
1 = H/V lock status has changed.
TV/VCR changed:
0 = TV/VCR status has not changed (default).
1 = TV/VCR status has changed.
Interrupt status register B is polled by the external processor to determine the interrupt source for interrupt B. After
an interrupt condition is set, it can be reset by writing to the interrupt reset register B at subaddress 1Ch with a 1 in
the appropriate bit.
2.20.42 Interrupt Active Register B
Address87h
76543210
ReservedInterrupt B
Interrupt B:
0 = Interrupt B is not active on the external terminal (default).
1 = Interrupt B is active on the external terminal.
The interrupt active register B is polled by the external processor to determine if interrupt B is active.
2−37
2.20.43 Status Register #1
Address88h
76543210
Peak white
detect status
Peak white detect status:
Line-alternating status:
Field rate status:
Lost lock detect:
Color subcarrier lock status:
Line-alternating
status
Field rate
status
Lost lock
detect
Color subcarrier
lock status
0 = Peak white is not detected.
1 = Peak white is detected.
0 = Nonline alternating
1 = Line alternating
0 = 60 Hz
1 = 50 Hz
0 = No lost lock since status register #1 was last read.
1 = Lost lock since status register #1 was last read.
Vertical sync
lock status
Horizontal sync
lock status
TV/VCR status
0 = Color subcarrier is not locked.
1 = Color subcarrier is locked.
Vertical sync lock status:
0 = Vertical sync is not locked.
1 = Vertical sync is locked.
Horizontal sync lock status:
0 = Horizontal sync is not locked.
1 = Horizontal sync is locked.
TV/VCR status. TV mode is determined by detecting standard line-to-line variations and specific chroma SCH phases
based on the standard input video format. VCR mode is determined by detecting variations in the chroma SCH phases
compared to the chroma SCH phases of the standard input video format.
0 = TV
1 = VCR
2−38
2.20.44 Status Register #2
Address89h
76543210
Reserved
Weak signal
detection
Weak signal detection:
0 = No weak signal
1 = Weak signal mode
PAL switch polarity of first line of odd field:
0 = PAL switch is 0
1 = PAL switch is 1
Field sequence status:
0 = Even field
1 = Odd field
AGC and offset frozen status:
0 = AGC and offset are not frozen.
1 = AGC and offset are frozen.
Macrovision detection:
PAL switch
polarity
Field sequence
status
AGC and offset frozen
status
Macrovision detection
000 = No copy protection
001 = AGC process present (Macrovision Type 1 present)
010 = Colorstripe process Type 2 present
011 = AGC process and colorstripe process Type 2 present
100 = Reserved
101 = Reserved
110 = Colorstripe process Type 3 present
111 = AGC process and color stripe process Type 3 present
2.20.45 Status Register #3
Address8Ah
76543210
Front-end AGC gain value (analog and digital)
†
Represents 8 bits (MSB) of a 10-bit value
This register provides the front-end AGC gain value of both analog and digital gains.
†
2−39
2.20.46 Status Register #4
VIDEO STANDARD
Address8Bh
76543210
Subcarrier to horizontal (SCH) phase
SCH (color PLL subcarrier phase at 50% of the falling edge of horizontal sync of line one of odd field; step size
360_/256):
This register contains information about the detected video standard and the sampling rate at which the device is
currently operating. When autoswitch code is running, this register must be tested to determine which video standard
has been detected.
These registers contain the closed caption data arranged in bytes per field.
2.20.49 WSS Data Registers
Address94h−99h
NTSC
ADDRESS76543210BYTE
94hb5b4b3b2b1b0WSS field 1 byte 1
95hb13b12b11b10b9b8b7b6WSS field 1 byte 2
96hb19b18b17b16b15b14WSS field 1 byte 3
97hb5b4b3b2b1b0WSS field 2 byte 1
98hb13b12b11b10b9b8b7b6WSS field 2 byte 2
99hb19b18b17b16b15b14WSS field 2 byte 3
These registers contain the wide screen signaling (WSS) data for NTSC.
Bits 0−1 represent word 0, aspect ratio
Bits 2−5 represent word 1, header code for word 2
Bits 6−13 represent word 2, copy control
Bits 14−19 represent word 3, CRC
PAL/SECAM
ADDRESS76543210BYTE
94hb7b6b5b4b3b2b1b0WSS field 1 byte 1
95hb13b12b11b10b9b8WSS field 1 byte 2
96hReserved
97hb7b6b5b4b3b2b1b0WSS field 2 byte 1
98hb13b12b11b10b9b8WSS field 2 byte 2
99hReserved
PAL/SECAM:
Bits 0−3 represent group 1, aspect ratio
Bits 4−7 represent group 2, enhanced services
Bits 8−10 represent group 3, subtitles
Bits 11−13 represent group 4, others
This address is provided to access VBI data in the FIFO through the host port. All forms of teletext data come directly
from the FIFO, while all other forms of VBI data can be programmed to come from the registers or from the FIFO.
Current status of the FIFO can be found at address C6h and the number of bytes in the FIFO is located at address
C7h. If the host port is to be used to read data from the FIFO, then the output formatter must be disabled at address
CDh bit 0. The format used for the VBI FIFO is shown in Section 2.9.
Filter logic: allows different logic to be applied when combining the decision of filter 1 and filter 2 as follows:
00 = NOR (Default)
01 = NAND
10 = OR
11 = AND
Mode:
0 = Teletext WST PAL mode B (2 header bytes) (default)
1 = Teletext NABTS NTSC mode C (5 header bytes)
TTX filter 2 enable:
0 = Disabled (default)
1 = Enabled
TTX filter 1 enable:
0 = Disabled (default)
1 = Enabled
If the filter matches or if the filter mask is all 0s, then a true result is returned.
2−44
2.20.55 Interrupt Status Register A
AddressC0h
Default00h
76543210
Lock state interruptLock interruptReservedFIFO threshold interruptLine interruptData interrupt
The interrupt status register A can be polled by the host processor to determine the source of an interrupt. After an
interrupt condition is set it can be reset by writing to this register with a 1 in the appropriate bit(s).
Lock state interrupt:
0 = TVP5150A is not locked to the video signal (default).
1 = TVP5150A is locked to the video signal.
Lock interrupt:
0 = A transition has not occurred on the lock signal (default).
1 = A transition has occurred on the lock signal.
FIFO threshold interrupt:
0 = The amount of data in the FIFO has not yet crossed the threshold programmed at address C8h (default).
1 = The amount of data in the FIFO has crossed the threshold programmed at address C8h.
Line interrupt:
0 = The video line number has not yet been reached (default).
1 = The video line number programmed in address CAh has occurred.
Data interrupt:
0 = No data is available (default).
1 = VBI data is available either in the FIFO or in the VBI data registers.
2−45
2.20.56 Interrupt Enable Register A
AddressC1h
Default00h
76543210
Reserved
Lock interrupt
enable
The interrupt enable register A is used by the host processor to mask unnecessary interrupt sources. Bits loaded with
a 1 allow the corresponding interrupt condition to generate an interrupt on the external pin. Conversely, bits loaded
with a 0 mask the corresponding interrupt condition from generating an interrupt on the external pin. This register only
affects the interrupt on the external terminal, it does not affect the bits in interrupt status register A. A given condition
can set the appropriate bit in the status register and not cause an interrupt on the external terminal. To determine if
this device is driving the interrupt terminal either perform a logical AND of interrupt status register A with interrupt
enable register A, or check the state of the interrupt A bit in the interrupt configuration register at address C2h.
Lock interrupt enable:
0 = Disabled (default)
1 = Enabled
Cycle complete interrupt enable:
0 = Disabled (default)
1 = Enabled
Bus error interrupt enable:
Cycle complete
interrupt enable
Bus error
interrupt enable
Reserved
FIFO threshold
interrupt enable
Line interrupt
enable
Data interrupt
enable
0 = Disabled (default)
1 = Enabled
FIFO threshold interrupt enable:
0 = Disabled (default)
1 = Enabled
Line interrupt enable:
0 = Disabled (default)
1 = Enabled
Data interrupt enable:
0 = Disabled (default)
1 = Enabled
2−46
2.20.57 Interrupt Configuration Register A
AddressC2h
Default04h
76543210
Reserved
YCbCr enable (VDPOE):
0 = YCbCr pins are high impedance.
1 = YCbCr pins are active if other conditions are met (default).
Interrupt A (read-only):
0 = Interrupt A is not active on the external pin (default).
1 = Interrupt A is active on the external pin.
Interrupt polarity A:
0 = Interrupt A is active low (default).
1 = Interrupt A is active high.
Interrupt configuration register A is used to configure the polarity of the external interrupt terminal. When interrupt
A is configured as active low, the terminal is driven low when active and high-impedance when inactive (open
collector). Conversely, when the terminal is configured as active high, it is driven high when active and driven low
when inactive.
YCbCr enable
(VDPOE)
Interrupt AInterrupt polarity A
2.20.58 VDP Configuration RAM Register
AddressC3hC4hC5h
DefaultDCh0Fh00h
Address76543210
C3hConfiguration data
C4hRAM address (7:0)
C5hReserved
The configuration RAM data is provided to initialize the VDP with initial constants. The configuration RAM is 512 bytes
organized as 32 dif ferent configurations of 16 bytes each. The first 12 configurations are defined for the current VBI
standards. An additional 2 configurations can be used as a custom programmed mode for unique standards like
Gemstar.
Address C3h is used to read or write to the RAM. The RAM internal address counter is automatically incremented
with each transaction. Addresses C5h and C4h make up a 9-bit address to load the internal address counter with a
specific start address. This can be used to write a subset of the RAM for only those standards of interest. Registers
D0h−FBh must all be programmed with FFh, before writing or reading the configuration RAM. Full field mode (CFh)
must be disabled as well.
The suggested RAM contents are shown below. All values are hexadecimal.
RAM
address 8
2−47
Table 2−13. VBI Configuration RAM For Signals With Pedestal
FIFO full error FIFO empty TTX available CC field 1 available CC field 2 available WSS available VPS available VITC available
The VDP status register indicates whether data is available in either the FIFO or data registers, and status information
about the FIFO. Reading data from the corresponding register does not clear the status flags automatically. These
flags are only reset by writing a 1 to the respective bit. However, bit 6 is updated automatically.
FIFO full error:
0 = No FIFO full error
1 = FIFO was full during a write to FIFO.
The FIFO full error flag is set when the current line of VBI data can not enter the FIFO. For example, if the FIFO has
only 10 bytes left and teletext is the current VBI line, the FIFO full error flag is set, but no data is written because the
entire teletext line will not fit. However, if the next VBI line is closed caption requiring only 2 bytes of data plus the
header, this goes into the FIFO. Even if the full error flag is set.
FIFO empty:
0 = FIFO is not empty.
1 = FIFO is empty.
TTX available:
0 = Teletext data is not available.
1 = Teletext data is available.
CC field 1 available:
0 = Closed caption data from field 1 is not available.
1 = Closed caption data from field 1 is available.
CC field 2 available:
0 = Closed caption data from field 2 is not available.
1 = Closed caption data from field 2 is available.
WSS available:
0 = WSS data is not available.
1 = WSS data is available.
VPS available:
0 = VPS data is not available.
1 = VPS data is available.
VITC available:
0 = VITC data is not available.
1 = VITC data is available.
2.20.60 FIFO Word Count Register
AddressC7h
76543210
Number of words
This register provides the number of words in the FIFO. 1 word equals 2 bytes.
2−49
2.20.61 FIFO Interrupt Threshold Register
AddressC8h
Default80h
76543210
Number of words
This register is programmed to trigger an interrupt when the number of words in the FIFO exceeds this value (default
80h). This interrupt must be enabled at address C1h. 1 word equals 2 bytes.
2.20.62 FIFO Reset Register
AddressC9h
Default00h
76543210
Any data
Writing any data to this register resets the FIFO and clears any data present.
2.20.63 Line Number Interrupt Register
AddressCAh
Default00h
76543210
Field 1 enableField 2 enableLine number
This register is programmed to trigger an interrupt when the video line number matches this value in bits 5:0. This
interrupt must be enabled at address C1h. The value of 0 or 1 does not generate an interrupt.
These registers form a 10-bit horizontal pixel position from the falling edge of sync, where the VDP controller initiates
the program from one line standard to the next line standard; for example, the previous line of teletext to the next line
of closed caption. This value must be set so that the switch occurs after the previous transaction has cleared the delay
in the VDP, but early enough to allow the new values to be programmed before the current settings are required.
2−50
2.20.65 FIFO Output Control Register
AddressCDh
Default01h
76543210
ReservedHost access enable
This register is programmed to allow I2C access to the FIFO or allowing all VDP data to go out the video port.
Host access enable:
0 = Output FIFO data to the video output Y[9:2]
2
1 = Allow I
C access to the FIFO data (default)
2.20.66 Full Field Enable Register
AddressCFh
Default00h
76543210
ReservedFull field enable
This register enables the full field mode. In this mode, all lines outside the vertical blank area and all lines in the line
mode registers programmed with FFh are sliced with the definition of register FCh. V alues other than FFh in the line
mode registers allow a different slice mode for that particular line.
Full field enable:
0 = Disable full field mode (default)
1 = Enable full field mode
2−51
2.20.67 Line Mode Registers
AddressD0hD1h−FBh
Default00hFFh
ADDRESS76543210
D0hLine 6 Field 1
D1hLine 6 Field 2
D2hLine 7 Field 1
D3hLine 7 Field 2
D4hLine 8 Field 1
D5hLine 8 Field 2
D6hLine 9 Field 1
D7hLine 9 Field 2
D8hLine 10 Field 1
D9hLine 10 Field 2
DAhLine 11 Field 1
DBhLine 11 Field 2
DChLine 12 Field 1
DDhLine 12 Field 2
DEhLine 13 Field 1
DFhLine 13 Field 2
E0hLine 14 Field 1
E1hLine 14 Field 2
E2hLine 15 Field 1
E3hLine 15 Field 2
E4hLine 16 Field 1
E5hLine 16 Field 2
E6hLine 17 Field 1
E7hLine 17 Field 2
E8hLine 18 Field 1
E9hLine 18 Field 2
EAhLine 19 Field 1
EBhLine 19 Field 2
EChLine 20 Field 1
EDhLine 20 Field 2
EEhLine 21 Field 1
EFhLine 21 Field 2
F0hLine 22 Field 1
F1hLine 22 Field 2
F2hLine 23 Field 1
F3hLine 23 Field 2
F4hLine 24 Field 1
F5hLine 24 Field 2
F6hLine 25 Field 1
F7hLine 25 Field 2
F8hLine 26 Field 1
F9hLine 26 Field 2
FAhLine 27 Field 1
FBhLine 27 Field 2
2−52
These registers program the specific VBI standard at a specific line in the video field.
Bit 7:
0 = Disable filtering of null bytes in closed caption modes
1 = Enable filtering of null bytes in closed caption modes (default)
In teletext modes, bit 7 enables the data filter function for that particular line. If it is set to 0, then the data filter passes
all data on that line.
Bit 6:
0 = Send VBI data to registers only.
1 = Send VBI data to FIFO and the registers. Teletext data only goes to FIFO. (default)
Bit 5:
0 = Allow VBI data with errors in the FIFO
1 = Do not allow VBI data with errors in the FIFO (default)
Bit 4:
0 = Do not enable error detection and correction
1 = Enable error detection and correction (when bits [3:0] = 1 2, 3, and 4 only) (default)
Bits [3:0]:
0000 = WST SECAM
0001 = WST PAL B
0010 = WST PAL C
0011 = WST NTSC
0100 = NABTS NTSC
0101 = TTX NTSC
0110 = CC PAL
0111 = CC NTSC
1000 = WSS PAL
1001 = WSS NTSC
1010 = VITC PAL
1011 = VITC NTSC
1100 = VPS PAL
1101 = Custom 1
1110 = Custom 2
1111 = Active video (VDP off) (default)
A value of FFh in the line mode registers is required for any line to be sliced as part of the full field mode.
2.20.68 Full Field Mode Register
AddressFCh
Default7Fh
76543210
Full field mode
This register programs the specific VBI standard for full field mode. It can be any VBI standard. Individual line settings
take priority over the full field register. This allows each VBI line to be programmed independently but have the
remaining lines in full field mode. The full field mode register has the same definitions as the line mode registers
(default 7Fh).
2−53
2−54
3 Electrical Specifications
3.1Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless
otherwise noted)
Supply voltage range:IO_DVDD to DGND −0.5 V to 4.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog input voltage range A
Digital output voltage range, V
Operating free-air temperature, T
Storage temperature, T
†
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Analog input voltage (ac-coupling necessary)00.75V
Digital input voltage high0.7 IO_DVDDV
Digital input voltage low0.3 IO_DVDDV
XTAL input voltage high0.7 PLL_AVDDV
XTAL input voltage low0.3 PLL_AVDDV
High-level output current2mA
Low-level output current−2mA
SCLK high-level output current4mA
SCLK low-level output current−4mA
Operating free-air temperature070°C
3.2.1Crystal Specifications
CRYSTAL SPECIFICATIONSMINNOMMAXUNIT
Frequency14.31818MHz
Frequency tolerance±50ppm
3−1
3.3Electrical Characteristics
DVDD = 1.8 V, PLL_AVDD = 1.8 V, CH_AVDD = 1.8 V, IO_DVDD = 3.3 V
For minimum/maximum values: T
= 0°C to 70°C, and for typical values: TA = 25°C unless otherwise noted
A
3.3.1DC Electrical Characteristics
PARAMETER
I
DD(IO_D)
I
DD(D)
I
DD(PLL_A)
I
DD(CH_A)
P
TOT
P
DOWN
C
i
V
OH
V
OL
V
OH_SCLK
V
OL_SCLK
I
IH
I
IL
NOTES: 1. Measured with a load of 15 pF.
3.3-V I/O digital supply currentColor bar input4.8mA
1.8-V digital supply currentColor bar input25.3mA
1.8-V analog PLL supply currentColor bar input5.4mA
1.8-V analog core supply currentColor bar input24.4mA
Total power dissipation, normal modeColor bar input115150mW
Total power dissipation, power-down mode
(see Note 2)
Input capacitanceBy design8pF
Output voltage highIOH = 2 mA0.8 IO_DVDDV
Output voltage lowIOL = −2 mA0.22 IO_DVDDV
SCLK output voltage highIOH = 4 mA0.8 IO_DVDDV
SCLK output voltage lowIOL = −2 mA0.22 IO_DVDDV
High-level input currentVI = V
Low-level input currentVI = V
2. Assured by device characterization.
3.3.2Analog Processing and A/D Converters
TEST CONDITIONS
(see NOTE 1)
Color bar input1mW
IH
IL
MINTYPMAXUNIT
±20µA
±20µA
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
ZiInput impedance, analog video inputsBy design500kΩ
C
i
Vi(pp)Input voltage range
∆GGain control range012dB
DNLDC differential nonlinearityA/D only±0.5LSB
INLDC integral nonlinearityA/D only±1LSB
FrFrequency response6 MHz−0.9−3dB
SNRSignal-to-noise ratio6 MHz, 1.0 V
NSNoise spectrum50% flat field50dB
DPDifferential phase1.5°
DGDifferential gain0.5%
†
The 0.75-V maximum applies to the sync-chroma amplitude, not sync-white. The recommended termination resistors are 37.4 Ω as seen in
Chapter 5.
Input capacitance, analog video inputsBy design10pF
†
C
coupling
= 0.1 µF00.75V
P-P
50dB
3−2
3.3.3Timing
3.3.3.1 Clocks, Video Data, Sync Timing
PARAMETER
Duty cycle PCLK50%
t
1
t
2
t
3
t
4
t
5
t
6
NOTE 3: Measured with a load of 15 pF.
VS, HS, FID
PCLK high time18.5ns
PCLK low time18.5ns
PCLK fall time10% to 90%4ns
PCLK rise time90% to 10%4ns
Output hold time2ns
Output delay time38ns
PCLK
Y, C, AVID,
TEST CONDITIONS
(see NOTE 2)
t
1
t
3
t
5
t
2
t
4
Valid DataValid Data
MINTYPMAXUNIT
V
OH
V
OL
t
6
Figure 3−1. Clocks, Video Data, and Sync Timing
3−3
3.3.3.2 I2C Host Port Timing
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
t
t
t
t
t
t
t
t
C
f
1
2
3
4
5
6
7
8
b
I2C
Bus free time between STOP and START1.3µs
Setup time for a (repeated) START condition0.6µs
Hold time (repeated) START condition0.6µs
Setup time for a STOP condition0.6ns
Data setup time100ns
Data hold time00.9µs
Rise time VC1(SDA) and VC0(SCL) signal250ns
Fall time VC1(SDA) and VC0(SCL) signal250ns
Capacitive load for each bus line400pF
I2C clock frequency400kHz
Stop StartStop
VC1 (SDA)
VC0 (SCL)
Data
t
1
t3
t
7
t6
t
8
t5
t3
t2
t4
Figure 3−2. I2C Host Port Timing
3−4
4 Example Register Settings
The following example register settings are provided only as a reference. These settings, given the assumed input
connector, video format, and output format, set up the TVP5150A decoder and provide video output. Example register
settings for other features and the VBI data processor are not provided here.
4.1Example 1
4.1.1Assumptions
Device:TVP5150AM1
Input connector: Composite (AIP1A)
Video format: NTSC-M, PAL (B, G, H, I), or SECAM
NOTE: NTSC-443, PAL-N, and PAL-M are masked from the autoswitch process by default.
See the autoswitch mask register at address 04h.
Output format: 8-bit ITU-R BT.656 with embedded syncs
4.1.2Recommended Settings
Recommended I2C writes: For this setup, only one write is required. All other registers are set up by default.
2
I
C register address 03h = Miscellaneous controls register address
2
I
C data 09h = Enables YCbCr output and the clock output
NOTE: HSYNC, VSYNC/PALI, AVID, and FID/GLCO are high impedance by default. See the
miscellaneous control register at address 03h.
Video format: NTSC-M, 443, PAL (B, G, H, I, M, N) or SECAM (B, D,G, K, KI, L)
Output format: 8-bit 4:2:2 YCbCr with discrete sync outputs
4.2.2Recommended Settings
Recommended I2C writes: This setup requires additional writes to output the discrete sync 4:2:2 data outputs, the
HSYNC, and the VSYNC, and to autoswitch between all video formats mentioned above.
2
I
C register address 00h = Video input source selection #1 register
2
I
C data 01h = Selects the S-Video input, AIP1A (luma), and AIP1B (chroma)
2
C register address 03h = Miscellaneous controls register address
I
2
I
C data 0Dh = Enables the YCbCr output data, HSYNC, VSYNC/PALI, AVID, and FID/GLCO
2
I
C register address 04h = Autoswitch mask register
2
I
C data C0h = Unmask NTSC-443, PAL-N, and PAL-M from the autoswitch process
2
C register address 0Dh = Outputs and data rates select register
I
2
I
C data 40h = Enables 8-bit 4:2:2 YCbCr with discrete sync output
4−1
4−2
5 Application Information
5.1Application Example
CH1_IN
CH2_IN
OSC_IN
R1
37.4 Ω
37.4 Ω
R5
37.4 Ω
37.4 Ω
OSC
R2
R6
S1
12
14.31818MHz
0.1uF
0.1uF
C5
0.1uF
CL1
30
REFM
CH_AGND
TVP5150A
IO_DVDD
YOUT7
11
1031
C1
1uF
PDN
AVID
REFP
INTERQ/GPCL/VBLK
YOUT6
YOUT5
YOUT4
YOUT3
1213141516
25526627728829
HSYNC
VSYNC/PALI
FID/GLCO
YOUT0
YOUT1
YOUT2
PDN
INTERQ/GPCL
AVID
HSYNC
IO_DVDD
R3
1.2K
24
23
22
SDA
21
SCL
20
DVDD
19
DGND
18
17
PCLK/SCLK
IO_DVDD
R7
Implies I2C address is BAh. If B8h is to be used,
10K
connect pulldown resistor to digital ground.
R4
1.2K
VSYNC/PALI
FID/GLCO
SDA
SCL
PDN
INTERQ/GPCL
AVID
HSYNC
VSYNC/PALI
FID/GLCO
DVDD
C7
0.1uF
PCLK/SCLK
RESETB
YOUT[7:0]
C2
1uF
AVDD
C4
AVDD
C6
Y1
C8
CL2
0.1uF
C11
1
AIP1A
2
AIP1B
3
PLL_AGND
4
PLL_AVDD
XTAL1/OSC
XTAL2
AGND
RESETB
IO_DVDD
C9
C3
1uF
32
CH_AVDD
PCLK/SCLK
9
C10
0.1uF
NOTE: The use of INTERQ/GPCL/AVID/HSYNC and VSYNC is optional. These are outputs and can be left floating.
When OSC is connected through S1, remove the capacitors for the crystal.
PDN needs to be high, if device has to be always operational.
RESETB is operational only when PDN is high. This allows an active low reset to the device.
Figure 5−1. Application Example
5−1
5−2
6 Mechanical Data
PBS (S-PQFP-G32) PLASTIC QUAD FLATPACK
25
32
1,05
0,95
0,50
24
0,23
0,17
17
16
9
1
3,50 TYP
5,05
SQ
4,95
7,10
SQ
6,90
8
0,08
M
0,10 MIN
0,13 NOM
Gage Plane
0,25
0°−ā 7°
0,70
0,40
1,20 MAX
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
Seating Plane
0,08
4087735/A 11/95
6−1
ZQC (S−PBGA−N48)PLASTIC BALL GRID ARRAY
4,10
0,77
0,71
3,90
SQ
G
F
E
D
C
B
A
A1 Corner
1,00 MAX
Seating Plane
3,00 TYP
0,50
1
234567
Bottom View
0,50
3,00 TYP
0,35
0,25
0,05
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. MicroStar Junior BGA package configuration.
D. Falls within JEDEC MO-225
E. This package is lead free.
0,25
0,15
0,08
4204695/A 09/02
6−2
MicroStar Junior is a trademark of Texas Instruments.
PACKAGE OPTION ADDENDUM
www.ti.com
22-Feb-2005
PACKAGING INFORMATION
Orderable DeviceStatus
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
TVP5150AM1PBSACTIVETQFPPBS32250 Green (RoHS &
no Sb/Br)
TVP5150AM1PBSRACTIVETQFPPBS321000 Green (RoHS &
no Sb/Br)
TVP5150AM1ZQCACTIVEBGA MI
ZQC48360Pb-Free
CROSTA
R JUNI
OR
TVP5150AM1ZQCRACTIVEBGA MI
ZQC482500Pb-Free
CROSTA
R JUNI
OR
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional
product content details.
None: Not yet available Lead (Pb-Free).
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens,
including bromine (Br) or antimony (Sb) above 0.1% of total product weight.
(RoHS)
(RoHS)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAULevel-3-260C-168 HR
CU NIPDAULevel-3-260C-168 HR
SNAGCULevel-3-260C-168 HR
SNAGCULevel-3-260C-168 HR
(3)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPQF027 – NOVEMBER 1995
PBS (S-PQFP-G32) PLASTIC QUAD FLATPACK
25
32
1,05
0,95
0,50
24
0,23
0,17
17
16
9
1
3,50 TYP
5,05
SQ
4,95
7,10
SQ
6,90
8
0,08
M
0,10 MIN
0,13 NOM
Gage Plane
0,25
0°–7°
0,70
0,40
1,20 MAX
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
Seating Plane
0,08
4087735/A 11/95
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
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