TEXAS INSTRUMENTS TUSB2136 Technical data

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Data M anua

August 2007 MSDS Bus Solutions

SLLS442E

TUSB2136

Data Manual

Universal Serial Bus Compound Hub

with General-Purpose 8052 MCU

Literature Number: SLLS442E

August 2007

Printed on Recycled Pape

Contents

Section Title Page

1 Introduction 1−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Features 1−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Functional Block Diagram 1−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Terminal Assignments 1−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Ordering Information 1−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Terminal Functions 1−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.6 Revision History 1−5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Functional Description 2−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 MCU Memory Map 2−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Miscellaneous Registers 2−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1 TUSB2136 Boot Operation 2−1. . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.2 MCNFG: MCU Configuration Register 2−2. . . . . . . . . . . . . . . . .

2.2.3 PUR_n: GPIO Pullup Register for Port n (n = 0 to 3) 2−2. . . . .

2.2.4 INTCFG: Interrupt Configuration 2−3. . . . . . . . . . . . . . . . . . . . . .

2.2.5 WDCSR: Watchdog Timer, Control, and Status Register 2−3.

2.2.6 PCON: Power Control Register (at SFR 87h) 2−4. . . . . . . . . . .

2.3 Buffers + I/O RAM Map 2−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.4 Endpoint Descriptor Block (EDB-1 to EDB-3) 2−5. . . . . . . . . . . . . . . . . . . .

2.4.1 OEPCNF_n: Output Endpoint Configuration 2−7. . . . . . . . . . . .

2.4.2 OEPBBAX_n: Output Endpoint X-Buffer Base-Address 2−7. .

2.4.3 OEPBCTX_n: Output Endpoint X Byte Count 2−8. . . . . . . . . . .

2.4.4 OEPBBAY_n: Output Endpoint Y-Buffer Base-Address 2−8. .

2.4.5 OEPBCTY_n: Output Endpoint Y Byte Count 2−8. . . . . . . . . . .

2.4.6 OEPSIZXY_n: Output Endpoint X/Y Byte Count 2−9. . . . . . . .

2.4.7 IEPCNF_n: Input Endpoint Configuration 2−9. . . . . . . . . . . . . .

2.4.8 IEPBBAX_n: Input Endpoint X-Buffer Base-Address 2−9. . . .

2.4.9 IEPBCTX_n: Input Endpoint X-Byte Base-Address 2−10. . . . . .

2.4.10 IEPBBAY_n: Input Endpoint Y-Buffer Base-Address 2−10. . . . .

2.4.11 IEPBCTY_n: Input Endpoint Y Byte Count 2−10. . . . . . . . . . . . .

2.4.12 IEPSIZXY_n: Input Endpoint X/Y-Buffer Size 2−11. . . . . . . . . . .

2.5 Endpoint-0 Descriptor Registers 2−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.5.1 IEPCNFG_0: Input Endpoint-0 Configuration Register 2−11. . .

2.5.2 IEPBCNT_0: Input Endpoint-0 Byte Count Register 2−12. . . . .

2.5.3 OEPCNFG_0: Output Endpoint-0 Configuration

2.5.4 OEPBCNT_0: Output Endpoint-0 Byte Count Register 2−13. . .

2.6 USB Registers 2−13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iii

2.6.1 FUNADR: Function Address Register 2−13. . . . . . . . . . . . . . . . .

2.6.2 USBSTA: USB Status Register 2−14. . . . . . . . . . . . . . . . . . . . . . .

2.6.3 USBMSK: USB Interrupt Mask Register 2−15. . . . . . . . . . . . . . .

2.6.4 USBCTL: USB Control Register 2−16. . . . . . . . . . . . . . . . . . . . . .

2.6.5 HUBCNFG: HUB-Configuration Register 2−17. . . . . . . . . . . . . . .

2.6.6 HUBPOTG: HUB Power-On to Power-Good

Descriptor Register 2−17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.6.7 HUBCURT: HUB Current Descriptor Register 2−17. . . . . . . . . . .

2.6.8 HUBPIDL: HUB-PID Register (Low-Byte) 2−18. . . . . . . . . . . . . .

2.6.9 HUBPIDH: HUB-PID Register (High-Byte) 2−18. . . . . . . . . . . . .

2.6.10 HUBVIDL: HUB-VID Register (Low-Byte) 2−18. . . . . . . . . . . . . .

2.6.11 HUBVIDH: HUB-VID Register (High-Byte) 2−18. . . . . . . . . . . . .

2.6.12 VIDSTA: VID/PID Status Register 2−18. . . . . . . . . . . . . . . . . . . . .

2.7 Function Reset and Power-Up Reset Interconnect 2−19. . . . . . . . . . . . . . .

2.8 Pullup Resistor Connect/Disconnect 2−19. . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9 8052 Interrupt and Status Registers 2−20. . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.9.1 8052 Standard Interrupt Enable Register 2−21. . . . . . . . . . . . . . .

2.9.2 Additional Interrupt Sources 2−21. . . . . . . . . . . . . . . . . . . . . . . . . .

2.9.3 VECINT: Vector Interrupt Register 2−22. . . . . . . . . . . . . . . . . . . . .

) 2−23. . . . . . . . . . .

2.10 I

2.9.4 Logical Interrupt Connection Diagram (INT0

2.9.5 P2[7:0] Interrupt (INT1

C Registers 2−24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.10.1 I2CSTA: I

2.10.2 I2CADR: I

2.10.3 I2CDAI: I

2.10.4 I2CDAO: I

C Status and Control Register 2−24. . . . . . . . . . . . . .

C Address Register 2−25. . . . . . . . . . . . . . . . . . . . . . .

C Data-Input Register 2−25. . . . . . . . . . . . . . . . . . . . . .

C Data-Output Register 2−25. . . . . . . . . . . . . . . . . . .

) 2−23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11 Read/Write Operations 2−25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.1 Read Operation (Serial EEPROM) 2−25. . . . . . . . . . . . . . . . . . . .

2.11.2 Current Address Read Operation 2−26. . . . . . . . . . . . . . . . . . . . .

2.11.3 Sequential Read Operation 2−26. . . . . . . . . . . . . . . . . . . . . . . . . .

2.11.4 Write Operation (Serial EEPROM) 2−27. . . . . . . . . . . . . . . . . . . .

2.11.5 Page Write Operation 2−28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Electrical Specifications 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Absolute Maximum Ratings Over Operating Free-Air

Temperature Range 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Commercial Operating Condition 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Electrical Characteristics, T

= 25°C, VCC = 3.3 V ± 0.3 V,

GND = 0 V 3−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Application 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 Keyboard Section 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Reset Timing 4−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Mechanical Data 5−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Illustrations

Figure Title Page

1−1 TUSB2136 Block Diagram 1−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−1 MCU Memory Map (TUSB2136B) 2−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−2 Reset Diagram 2−19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−3 Pullup Resistor Connect/Disconnect Circuit 2−20. . . . . . . . . . . . . . . . . . . . . . . . . .

2−4 Internal Vector Interrupt (INT0

2−5 P2[7:0] Input Port Interrupt Generation 2−23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−1 Keyboard LED Connection 4−1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−2 Keyboard Matrix Scan Connection 4−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−3 Partial Connection Bus Power Mode 4−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−4 Upstream Connection (a) Non-Switching Power Mode (b) Switching

Power Mode 4−2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−5 Downstream Connection − Only One Port Shown 4−3. . . . . . . . . . . . . . . . . . . . .

4−6 Reset Timing 4−3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

) 2−23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Tables

Table Title Page

2−1 XDATA Space 2−4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−2 Memory Mapped Registers Summary (XDATA Range = FF80 → FFFF) 2−5. .

2−3 EDB and Buffer Allocations in XDATA 2−6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−4 EDB Entries in RAM (n = 1 to 3) 2−7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−5 Input/Output EDB-0 Registers 2−11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−6 External Pins Mapping to S[3:0] in VIDSTA Register 2−19. . . . . . . . . . . . . . . . . . .

2−7 8052 Interrupt Location Map 2−20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2−8 Vector Interrupt Values 2−22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4−1 GPIO Assignment for Matrix Scan and LED Drive 4−1. . . . . . . . . . . . . . . . . . . . .

1 Introduction

The TUSB2136 is an integrated universal serial bus (USB) hub with a general-purpose 8052 microcontroller that can be used for various USB controller applications. The TUSB2136 has 8K × 8 RAM space for application development. Using a 12-MHz crystal, the onboard oscillator generates the internal system clocks. No additional programming is required for any part of the hub functions. The device is programmed via an inter-IC (I on from an EEPROM, or optionally, the application firmware can be downloaded from a host PC via USB. The 8052-based microprocessor allows several third-party standard tools to be used for application development. In addition, the application code available in the general market can also be used (this may or may not require some code modification due to hardware variations).

1.1 Features

• Multiproduct support with one code and one chip (up to 16 products with one chip)

• Fully compliant with the USB specification as a compound full-speed device: TID #30270119

• Supports 1.5- and 12-Mbits/s USB data rates

• Supports USB suspend/resume and remote wake-up operation

• Integrated two-port hub with individual power management per port

• Integrated 8052 microcontroller with:

− 256 × 8 RAM for internal data

− 8K × 8 RAM code space available for downloadable firmware from host or I

− 512 × 8 shared RAM used for data buffers and endpoint descriptor blocks (EDB) [1]

− Four 8052 GPIO ports (ports 0,1, 2 and 3)

− Master I

− Watchdog timer

C controller for external slave device access

C) serial interface at power

C port.

• Operates from a 12-MHz crystal

• On-chip PLL generates 48 MHz

• Supports a total of three input and three output (interrupt, bulk) endpoints

• Power-down mode

• 64-pin TQFP package

[1] This is the buffer space for USB packet transactions.

1−1

1.2 Functional Block Diagram

12 MHz

USB0 USB1 USB2

Clock,

PLL and

Dividers

USB HUB

USB

SIE

6K y 8

ROM

8K y 8 SRAM

CPU − I/F Susp/Res

UBM

USB Buffer

Manager

TDM

Control

Logic

8052 Core

Reset and

Interrupt

Logic

2 y 16-Bit

Timers

Port-1

Port-2

Port-3

Port-4

I2C

Controller

8 P0[7:0]

8 P1[7:0]

8 P2[7:0]

8 P3[7:0]

RSTI INT1

I2C Bus

Figure 1−1. TUSB2136 Block Diagram

1−2

1.3 Terminal Assignments

P0.5

P0.4

P0.3

P0.2

P0.1

PM PACKAGE

(TOP VIEW)

P0.0

GND

P1.7

P1.6

VDD18

VREN

P1.5

P1.4

P1.3

P1.2

P0.6 P0.7 P3.7 P3.6 P3.5 P3.4 P3.3 P3.2

P3.1/S1/TXD

P3.0/S0/RXD

GND

X2 X1

DM2

DP2

1.4 Ordering Information

47 46 45 44 4348 42

49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64

12 3

PWR01

OVCR2

PWR02

5678

GND

OVCR1

DM1

40 39 3841

910111213

DP1

37 36

SDA

SCL

35 34 33

14 15 16

RST

TEST0

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

SUSP

TEST1

P1.1 P1.0 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 GND P2.1 P2.0 SELF/BUS GND DM0 DP0 PUR

PACKAGE

0°C to 70°C TUSB2136PM

PLASTIC QUAD FLATPACK

(PM)

1−3

1.5 Terminal Functions

I/O

DESCRIPTION

P3.0/S0/RXD

I/O

P3.1/S1/TXD

TERMINAL

NAME NO.

DM0 19 I/O Differential data-minus USB port 0: upstream DM1 6 I/O Differential data-minus port 1: downstream DM2 63 I/O Differential data-minus port 2: downstream DP0 18 I/O Differential data-plus USB port 0: upstream DP1 7 I/O Differential data-plus port 1: downstream DP2 64 I/O Differential data-plus port 2: downstream GND 5, 20, 24,

42, 59 OVCR1 4 I Port 1: Overcorrect indicator; Schmitt-trigger input, 100-µA active pullup OVCR2 1 I Port 2: Overcorrect indicator; Schmitt-trigger input, 100-µA active pullup P0.[0:7] 43, 44, 45,

46, 47, 48,

49, 50 P1.[0:7] 31, 32, 33,

34, 35, 36,

40, 41 P2.[0:7] 22, 23, 25,

26, 27, 28,

29, 30 P3.0/S0/RXD 58 I/O

P3.1/S1/TXD 57

P3.2 56 I/O General-purpose I/O port 3 bit 2, Schmitt-trigger input, 100-µA active pullup, open-drain output†; INT0

P3.3 55 I/O General-purpose I/O port 3 bit 3, Schmitt-trigger input, 100-µA active pullup, open-drain output

P3.[4:7] 54, 53, 52,51I/O General-purpose I/O port 3 bit 4, Schmitt-trigger input, 100-µA active pullup, open-drain output

— Power supply ground

I/O General-purpose I/O port 0 bits 0−7, Schmitt-trigger input, 100-µA active pullup, open-drain output

I/O General-purpose I/O port 1 bits 0−7, Schmitt-trigger input, 100-µA active pullup, open-drain output

I/O General-purpose I/O port 2 bits 0−7, Schmitt-trigger input, 100-µA active pullup, open-drain output

P3.0: General-purpose I/O port 3 bit 0, Schmitt-trigger input, 100-µA active pullup, open-drain output S0: See Section 2.6.12

RXD: Can be used as a UART interface I/O P3.1: General-purpose I/O port 3 bit 1, Schmitt-trigger input, 100-µA active pullup, open-drain output I/O S1: See Section 2.6.12 I/O TXD: Can be used as a UART interface

only used internally (see Section 2.9.4)

†;

may support INT1

input, depending on configuration (see Figure 2−5)

†

1−4

PUR 17 O Pullup resistor connection pin (3-state); push-pull CMOS output (±8 mA) PWRO1 3 O Port 1: power on/off control signal; push-pull CMOS output (±8 mA) PWRO2 2 O Port 2: power on/off control signal; push-pull CMOS output (±8 mA) RST 13 I Controller master reset signal, Schmitt-trigger input, 100-µA active pullup S2 8 I General-purpose input; can be used for VID/PID selection under firmware control. This input has no

S3 9 I General-purpose input. This input has no internal pullup, so it must be driven/pulled either low or high

SCL 12 O Serial clock I2C; push-pull output SDA 11 I/O Serial data I2C; open-drain output SELF/BUS 21 I USB power MODE select: self powered (HIGH), bus powered (LOW) SUSP 16 O Suspend status signal: suspended (HIGH); unsuspended (LOW)

‡

TEST0

‡

TEST1

†

All open-drain output pins can sink up to 8 mA.

‡

The functions controlled by TEST0 and TEST1 are shown in the following table. Because these two pins have internal pullups, they can be left unconnected for the default mode.

14 I Test input 0, Schmitt-trigger input, 100-µA active pullup 15 I Test input 1, Schmitt-trigger input, 100-µA active pullup

internal pullup, so it must be driven/pulled either low or high and connot be left unconnected.

and connot be left unconnected.

†

1.5 Terminal Functions (Continued)

I/O

DESCRIPTION

TERMINAL

NAME NO.

VDD18 VREN 38 I Voltage regulator enable: enable active LOW; disable active HIGH X2 60 O 12-MHz crystal output X1 61 I 12-MHz crystal input

†

During normal o p e r a t i o n , t h e i n t e r n a l 3 . 3 - t o 1 . 8 - V v o ltage regulator of the TUSB2136 is enabled and provides power to the core. To save power during the suspend mode, the internal regulator is disabled. In this case, the pin becomes an input, and a simple external power source is required to provide power to the core. This source needs to supply a very limited amount of power (10 µA maximum) within the voltage range of 1 V to

1.95 V.

NOTE 1: The MCU treats the outputs as open-drain types in that the output can be driven low continuously, but a high output is driven for two

10,39,62 — Power supply input, 3.3 V typical

†

37 1.8 V. When VREN is low, 1.8 V must be applied to provide current for the core during suspend.

clock cycles and then the output is placed in a high-impedance state.

TEST0

0 0 Selects 48-MHz clock input (from an oscillator or other onboard clock source) 0 1 Reserved for testing purposes 1 0 Reserved for testing purposes 1 1 Selects 12-MHz crystal as clock source (default)

TEST1 FUNCTION

1.6 Revision History

Version Date Changes

Dec−2000 Initial Release

A Feb−2001 1. Clarified pin descriptions for P3.2 (56), P3.3 (55), and VDDOUT (37).

B Jun−2002 1. Changed name of pin 37 from VDDOUT to VDD18 and enhanced pin description.

C Apr−2003 1. Simplified Terminal Function Table for GPIO Ports

2. Add red/write capability for each of the register bits.

3. Corrected Quiescent and Suspend current figures in Table 3.3.

4. Added Section 4.2 Reset Timing

5. Added NOTE to cover page.

2. Removed NOTE from cover page.

2. Clarified GPIO Port 3 pin descriptions in Terminal Function Table

3. Clarified functional description for Pins S2 and S3 (8 & 9)

4. Clarified TEST0 & TEST1 (14 & 15) pin functions in Terminal Functions Table

5. Added note on open-drain output pins for Terminal Functions Table

6. Added additional note for operation of VDD18 (pin 37) to Terminal Functions Table.

7. Removed most references to ROM version including Fig 2.2.

8. Added USB Logo to Cover page

1−5

1−6

2 Functional Description

2.1 MCU Memory Map

Figure 2−1 illustrates the MCU memory map under boot and normal operation. It must be noted that the internal 256 bytes of IDATA are not shown since it is assumed to be in the standard 8052 location (0000 to 00FF). The shaded areas represent the internal ROM/RAM. For more information regarding the integrated 8052, see the TUSBxxxx Microcontroller Reference Guide (SLLU044).

When the SDW bit = 0 (boot mode): The 6K ROM is mapped to address (0000−17FF) and is duplicated in location (8000−97FF) in code space. The internal 8K RAM is mapped to address range (0000−1FFF) in data space. Buffers, memory-mapped registers (MMRs), and I/O are mapped to address range (FD80−FFFF) in data space.

When the SDW bit = 1 (normal mode): The 6K ROM is mapped to (8000−97FF) in code space. The internal 8K RAM is mapped to address range (0000−1FFF) code space. Buffers, MMR, and I/O are mapped to address range (FD80−FFFF) in data space.

0000

17FF

1FFF

8000

97FF

FD80

Boot Mode (SDW = 0)

CODE

6K Boot ROM

XDATA

RAM

Read/Write

512 Bytes

RAM

Normal Mode (SDW = 1)

CODE

Code RAM

Read Only

6K Boot ROM

XDATA

512 Bytes

RAM

FF80 FFFF

MMR

Figure 2−1. MCU Memory Map (TUSB2136B)

2.2 Miscellaneous Registers

2.2.1 TUSB2136 Boot Operation

Because the code space is in RAM (with the exception of the boot ROM), the TUSB2136 firmware must be loaded from an external source. Two options for booting are available: an external serial EEPROM source connected to the

2−1

I2C bus, or the host can be used via the USB. On device reset, the SDW bit (in the ROM register) and the CONT bit

SDW

OVCE

XINT

in the USB control register (USBCTL) are cleared. This configures the memory space to boot mode (see memory map, Table 2−2) and keeps the device disconnected from the host.

The first instruction is fetched from location 0000 (which is in the 6K ROM). The 8K RAM is mapped to XDATA space (location 0000h). The MCU executes a read from an external EEPROM and tests to see if it contains the code (test for boot signature). If it contains the code, the MCU reads from EEPROM and writes to the 8K RAM in XDATA space. If not, the MCU proceeds to boot from USB.

Once the code is loaded, the MCU sets SDW to 1. This switches the memory map to normal mode, i.e. the 8K RAM is mapped to code space, and the MCU starts executing from location 0000h. Once the switch is done, the MCU sets CONT to 1 (in the USBCTL register) This connects the device to the USB, resulting in the normal USB device enumeration.

2.2.2 MCNFG: MCU Configuration Register

This register is used to control the MCU clock rate.

76 5 43210 RSV XINT OVCE R3 R2 R1 R0 SDW R/W R/W R/W R/O R/O R/O R/O R/W

BIT NAME RESET FUNCTION

0 SDW 0

4−1 R[3:0] No effect These bits reflect the device revision number.

5 OVCE 0

6 XINT 0

7 RSV 0 Reserved

This bit enables/disables boot ROM. SDW = 0 When clear, the MCU executes from the 6K boot ROM space. The boot ROM appears in two

locations: 0000 and 8000h. The 8K RAM is mapped to XDATA space; therefore, read/write operation is possible. This bit is set by the MCU after the RAM load is completed. The MCU cannot clear this bit. It is cleared on power-up reset or function reset.

SDW = 1 When set by MCU, the 6K boot ROM maps to location 8000h, and the 8K RAM is mapped to

code space, starting at location 0000h. At this point, the MCU executes from RAM, and write operation is disabled (no write operation is possible in code space).

Hub overcorrect detection enable/disable bit. OVCE = 0 Hub overcorrect detection is disabled. OVCE = 1 Hub overcorrect detection is enabled. INT1 source control bit XINT = 0 INT1 is connected to the P3.3 pin and operates as a standard INT1 interrupt. XINT = 1 INT1 is connected to the OR of port-2 inputs.

2.2.3 PUR_n: GPIO Pullup Register for Port n (n = 0 to 3)

PUR_0: GPIO pullup register for port 0 PUR_1: GPIO pullup register for port 1 PUR_2: GPIO pullup register for port 2 PUR_3: GPIO pullup register for port 3

76543210

PORT_n.7 PORT_n.6 PORT_n.5 PORT_n.4 PORT_n.3 PORT_n.2 PORT_n.1 PORT_n.0

R/W R/W R/W R/W R/W R/W R/W R/W

BIT NAME RESET FUNCTION

0−7 PORT_n.N

(N = 0 to 7)

2−2

0 The MCU can write to this register. If the MCU sets this bit to 1, the pullup resistor is disconnected from

the pin. If the MCU clears this bit to 0, the pullup resistor is connected to the pin. The pullup resistor is connected to the VCC power supply.

2.2.4 INTCFG: Interrupt Configuration

WDE

76 5 43210

RSV RSV RSV RSV I3 I2 I1 I0

R/O R/O R/O R/O R/W R/W R/W R/W

BIT NAME RESET FUNCTION

0−3 I[3:0] 0010 The MCU can write to this register to set the interrupt delay time for port 2 on the MCU. The value of the

4−7 RSV 0 Reserved

lower nibble represents the delay in ms. Default after reset is 2 ms.

2.2.5 WDCSR: Watchdog Timer, Control, and Status Register

A watchdog timer (WDT) with 1-ms clock is provided. The watchdog timer only works when a USB start-of-frame has been detected by the TUSB3210. If this register is not accessed for a period of 32 ms, the WDT counter resets the MCU (see Figure 2−2, Reset Diagram). When the IDL bit in PCON is set, the WDT is suspended until an interrupt is detected. At this point, the IDL bit is cleared and the WDT resumes operation. The WDE bit of this register is cleared only on power-up or USB reset (if enabled). When the MCU writes a 1 to the WDE bit of this register the WDT starts running.

76 5 43210

WDE WDR RSV RSV RSV RSV RSV WDT

R/W R/W R/O R/O R/O R/O R/O W/O

BIT NAME RESET FUNCTION

0 WDT 0 The MCU must write a 1 to this bit to prevent the WDT from resetting the MCU. If MCU does not write a 1 in a

5−1 RSV 0 Reserved

6 WDR 0

7 WDE 0

period of 31 ms, the WDT resets the device. Writing a 0 has no effect on the WDT. (The WDT is a 5-bit counter using a 1-ms CLK). This bit is read as 0.

Watchdog reset indication bit. This bit indicates if the reset occurred due to power-on reset or watchdog timer reset.

WDR = 0 A power-up or USB reset occurred. WDR = 1 A watchdog time-out reset occurred. To clear this bit, the MCU must write a 1. Writing a 0 has

no effect. Watchdog timer enable WDE = 0 Disabled WDE = 1 Enabled

2−3

2.2.6 PCON: Power Control Register (at SFR 87h)

IDL

Internal

memory mapped registers

↑

memory mapped registers

(EDB)

Setup packet buffer

Input endpoint-0 buffer

RAM

Output endpoint-0 buffer

Data buffers

↑

(368 bytes)

76 5 43210

SMOD RSV RSV RSV GF1 GF0 RSV IDL

R/W R/O R/O R/O R/W R/W R/O R/W

BIT NAME RESET FUNCTION

0 IDL 0

1 RSV 0 Reserved 3−2 GF[1:0] 00 General-purpose bits. The MCU can write and read them. 6−4 RSV 0 Reserved

7 SMOD 0 Double baud-rate control bit. For more information see the UART serial interface in the M8052 core

MCU idle mode bit. This bit can be set by the MCU and is cleared only by the INT1 interrupt. IDL = 0 The MCU is not in idle mode. This bit is cleared by the INT1 interrupt logic when INT1 is

IDL = 1 The MCU is in idle mode and RAM is in low-power mode. The oscillator/APLL is off and the

specification.

asserted for at least 400 µs.

WDT is suspended. When in suspend mode, only INT1 and generate an interrupt. INT1 recognized.

must be asserted for at least 400 µs for the interrupt to be

can be used to exit from the idle state

2.3 Buffers + I/O RAM Map

The address range from FD80 to FFFF is reserved for data buffers, setup packet, endpoint descriptor blocks (EDB), and all I/O. RAM space of 512 bytes [FD80−FF7F] is used for EDB and buffers. The FF80−FFFF range is used for memory-mapped registers (MMR). Table 2−1 represents the internal XDATA space allocation.

Table 2−1. XDATA Space

DESCRIPTION ADDRESS RANGE

(MMR)

Endpoint descriptor blocks

Setup packet buffer

Input endpoint-0 buffer

Output endpoint-0 buffer

FFFF

FF80 FF7F

↑

FF08 FF07

↑

FF00 FEFF

↑

FEF8 FEF7

↑

FEF0 FEEF

512 -Byte

2−4

FD80

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