Texas Instruments TUSB2046BVFR, TUSB2046BVF Datasheet

TUSB2046B

4-PORT HUB FOR THE UNIVERSAL SERIAL BUS

WITH OPTIONAL SERIAL EEPROM INTERFACE

SLLS413 – FEBRUARY 2000

Universal Serial Bus (USB) Version 1.1 Compliant

32-Pin LQFP† Package With a 0.8 mm Pin Pitch

3.3-V Low Power ASIC Logic

Integrated USB Transceivers

State Machine Implementation Requires No Firmware Programming

One Upstream Port and Four Downstream Ports

All Downstream Ports Support Full-Speed and Low-Speed Operations

Two Power Source Modes

– Self-Powered Mode – Bus-Powered Mode

Power Switching and Over-current Reporting is Provided Ganged or Per Port

Supports Suspend and Resume Operations

Supports Programmable Vendor ID and Product ID With External Serial EEPROM

3-State EEPROM Interface Allows EEPROM Sharing

Push-Pull Outputs for PWRON Eliminate the Need for External Pullup Resistors

Noise Filtering on OVRCUR Provides Immunity to Voltage Spikes

Package Pinout Allows 2-Layer PCB

Low EMI Emission Achieved by a 6-MHz Crystal Input

Migrated From Proven TUSB2040 Hub

Lower Cost Than the TUSB2040 Hub

Enhanced System ESD Performance

Supports 6 MHz Operation Through a Crystal Input or a 48 MHz Input Clock

description

DP0

DM0

RESET EECLK

EEDATA/GANGED

GND

BUSPWR

VF PACKAGE

(TOP VIEW)

SUSPND

TSTMODE

XTAL1

XTAL2

32 26

31 30 29 28 27

1 2 3 4 5 6 7 8

11 12 13 14 15

910

DP1

DM1

PWRON1

OVRCUR1

GND

PWRON2

TSTPLL/48MCLK

EXTMEM

24 23 22 21 20 19 18 17

DP2

DM2

OVRCUR2

DP4 DM4 OVRCUR4 PWRON4 DP3 DM3 OVRCUR3 PWRON3

The TUSB2046B is a 3.3-V CMOS hub device that provides one upstream port and four downstream ports in compliance with the 1.1 Universal Serial Bus (USB) specification. Because this device is implemented with a digital state machine instead of a microcontroller, no firmware programming is required. Fully compliant USB transceivers are integrated into the ASIC for all upstream and downstream ports. The downstream ports support both full-speed and low-speed devices by automatically setting the slew rate according to the speed of the device attached to the ports. The configuration of the BUSPWR pin selects either the bus-powered or the self-powered mode.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

†

JEDEC descriptor S-PQFP-G for low profile quad flat pack (LQFP).

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

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TUSB2046B 4-PORT HUB FOR THE UNIVERSAL SERIAL BUS WITH OPTIONAL SERIAL EEPROM INTERFACE

SLLS413 – FEBRUARY 2000

description (continued)

Configuring the GANGED input determines the power switching and over-current detection modes for the downstream ports. External power management devices such as the TPS2044 are required to control the 5-V source to the downstream ports according to the corresponding values of the PWRON pin. Upon detecting any over-current conditions, the power management device sets the corresponding OVRCUR TUSB2046B to a logic low. If GANGED is high, all PWRON outputs switch together and if any OVRCUR is activated, all ports transition to power off state. If GANGED is low, the PWRON outputs and OVRCUR inputs operate on a per port basis.

The TUSB2046B provides the flexibility of using a 6-MHz or a 48-MHz clock. The logic level of the TSTMODE terminal controls the selection of the clock source. When TSTMODE is low, the output of the internal APLL circuitry is selected to drive the internal core of the chip. When TSTMODE is high, the TSTPLL/48MCLK input is selected as the input clock source and the APLL circuitry is powered down and bypassed. The internal oscillator cell is also powered down while TSTMODE is high.

Low EMI emission is achieved because the TUSB2046B is able to utilize a 6 MHz crystal input. Connect the crystal as shown in Figure 6. An internal PLL then generates the 48 MHz clock used to sample data from the upstream port and to synchronize the 12 MHz used for the USB clock. If low power suspend and resume are desired, a passive crystal or resonator must be used. However, a 6-MHz oscillator may be used by connecting the output to the XTAL1 terminal and leaving the XTAL2 terminal open. The oscillator TTL output must not exceed 3.6 V.

pin of the

For 48-MHz operation, the clock can not be generated with a crystal, using the XT AL2 output, since the internal oscillator cell only supports fundamental frequency.

Refer to Figure 7 and Figure 8 in the input clock configuration.

The EXTMEM pin enables or disables the optional EEPROM interface. When the EXTMEM pin is high, the product ID (PID) displayed during enumeration is the general-purpose USB hub. For this default, pin 5 is disabled and pin 6 functions as the GANGED input pin. If custom PID and Vendor ID (VID) descriptors are desired, the EXTMEM EEPROM interface with pin 5 and pin 6 functioning as the EECLK and EEDATA, respectively. See Table 1 for a description of the EEPROM memory map.

Other useful features of the TUSB2046B include a package with a 0.8 mm pin pitch for easy PCB routing and assembly , push-pull outputs for the PWRON pins eliminate the need for pullup resistors required by traditional open collector I/Os, and OVRCUR pins have noise filtering for increased immunity to voltage spikes.

pin must be low (EXTMEM = 0). For this configuration, pin 5 and pin 6 function as the

input clock configuration

section for more detailed information regarding

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functional block diagram

Hub Repeater

DP0 DM0

USB

Transceiver

Suspend/Resume

Logic and

Frame Timer

TUSB2046B

4-PORT HUB FOR THE UNIVERSAL SERIAL BUS

WITH OPTIONAL SERIAL EEPROM INTERFACE

SLLS413 – FEBRUARY 2000

SUSPND

TSTPLL/48MCLK

XTAL1

XTAL2

RESET

EXTMEM

EEDATA/GANGED

EECLK

SIE Interface

Logic

OSC/PLL

SIE

Serial

EEPROM

Interface

Port 4

Logic

USB

Transceiver

24 23

DP4 DM4

Port 3

Logic

USB

Transceiver

20 19

Port 2

Logic

USB

Transceiver

16 15

DP2 DM2DP3 DM3

Port 1

Logic

Transceiver

12 11

USB

DP1 DM1

Hub/Device

Command

Decoder

Hub

Power

Logic

10, 14, 18, 22

9, 13, 17, 21

BUSPWR

OVRCUR1 – OVRCUR4

PWRON1 – PWRON4

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TUSB2046B

I/O

DESCRIPTION

4-PORT HUB FOR THE UNIVERSAL SERIAL BUS WITH OPTIONAL SERIAL EEPROM INTERFACE

SLLS413 – FEBRUARY 2000

Terminal Functions

TERMINAL

NAME NO.

BUSPWR 8 I Power source indicator. BUSPWR is an active high input that indicates whether the downstream ports

DM0 2 I/O Root port USB differential data minus. DM0 paired with DP0 constitutes the upstream USB port. DM1 – DM4 11, 15,

DP0 1 I/O Root port USB differential data plus. DP0 paired with DM0 constitutes the upstream USB port. DP1 – DP4 12, 16,

EECLK 5 O EEPROM serial clock. When EXTMEM is high, the EEPROM interace is disabled. The EECLK pin is

EEDATA/ GANGED

EXTMEM 26 I EEPROM read enable. When EXTMEM is high, the serial EEPROM interface of the device is disabled.

GND 7, 28 Ground. GND terminals must be tied to ground for proper operation. OVRCUR1 –

OVRCUR4

PWRON1 – PWRON4

RESET 4 I Reset. RESET is an active low TTL input with hysteresis and must be asserted at power up. When RESET

SUSPND 32 O Suspend status. SUSPND is an active high output available for external logic power down operations.

TSTMODE 31 I T est/Mode pin. TSTMODE is used as a test pin during production testing. This pin must be tied to ground

TSTPLL/48MCLK 27 I/O Test/48MHz clock input. TSTPLL/48MCLK is used as a test pin during production testing. This pin must

XTAL1 30 I Crystal 1. XT AL1 is a 6-MHz crystal input with 50% duty cycle. An internal PLL generates the 48-MHz and

XTAL2 29 O Crystal 2. XTAL2 is a 6-MHz crystal output. This terminal should be left open when using an oscillator.

19, 23

20, 24

6 I/O EEPROM serial data/power management mode indicator. When EXTMEM is high, EEDATA/GANGED

10, 14,

18, 22

9, 13,

17, 21

3, 25 3.3-V supply voltage

source their power from the USB cable or a local power supply. For the bus-power mode, this pin should be pulled to 3.3 V, and for the self-powered mode, this pin should be pulled low. Input must not change dynamically during operation.

I/O USB differential data minus. DM1 – DM4 paired with DP1 – DP4 support up to four downstream USB ports.

I/O USB differential data plus. DP1 – DP4 paired with DM1 – DM4 support up to four downstream USB ports.

disabled and should be left floating (unconnected). When EXTMEM clock output to the EEPROM with a 100 µA internal pulldown.

selects between gang or per-port power over-current detection for the downstream ports. When EXTMEM is low, EEDAT A/GANGED acts as a serial data I/O for the EEPROM and is internally pulled down with a 100 µA pulldown. This standard TTL input must not change dynamically during operation.

When EXTMEM interface, respectively .

I Over-current input. OVRCUR1 – OVRCUR4 are active low. For per-port over current detection, one

over-current input is available for each of the four downstream ports. In the ganged mode, any OVRCUR input may be used and all OVRCUR pins should be tied together. OVRCUR pins are active low inputs with noise filtering logic.

O Power-on/-off control signals. PWRON1 – PWRON4 are active low, push-pull outputs. Push-pull outputs

eliminate the pullup resistors which open-drain outputs require. However, the external power switches that connect to these pins must be able to operate with 3.3-V inputs because these outputs cannot drive 5-V signals.

is asserted, all logic is initialized. Generally, a reset with a pulse width between 100 µs and 1 ms is recommended after 3.3 V VCC reaching its 90%. Clock signal has to be active during the last 60 µs of the reset window.

During the suspend mode, SUSPND is high. SUSPND is low for normal operation.

or 3.3 V VCC for normal 6 MHz or 48 MHz operation, respectively.

be tied to ground for normal 6 MHz operation. If 48 MHz input clock is desired, a 48 MHz clock source (no crystal) can be connected to this input pin.

12-MHz clocks used internally by the ASIC logic.

is low, terminals 5 and 6 are configured as the clock and data pins of the serial EEPROM

is low, EECLK acts as a 3-state serial

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TUSB2046B

4-PORT HUB FOR THE UNIVERSAL SERIAL BUS

WITH OPTIONAL SERIAL EEPROM INTERFACE

SLLS413 – FEBRUARY 2000

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VCC (see Note 1) –0.5 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

–0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK, (VI < 0 V or VI > VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK, (VO < 0 V or V Storage temperature range, T

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

> VCC) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, TA 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage levels are with respect to GND.

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V Input voltage, TTL/LVCMOS, V Output voltage, TTL/LVCMOS, V High-level input voltage, signal-ended receiver, V Low-level input voltage, signal-ended receiver, V High-level input voltage, TTL/LVCMOS, V Low-level input voltage, TTL/LVCMOS, V Operating free-air temperature, T

External series, differential driver resistor, R Operating (dc differential driver) high speed mode, f Operating (dc differential driver) low speed mode, f Common mode, input range, differential receiver , V Input transition times, tt, TTL/LVCMOS 0 25 ns Junction temperature range, T

IH(REC)

IL(REC)

IH(TTL)

IL(TTL)

(DRV)

(OPRH)

(OPRL)

(ICR)

3 3.3 3.6 V 0 V 0 V 2 V

2 V 0 0.8 V 0 70 °C

22 (–5%) 22 (5%) Ω

0.8 2.5 V

0 115 °C

CC CC CC

0.8 V CC

12 Mb/s

1.5 Mb/s

V V V

†

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TUSB2046B

USB data lines

Positi

VT–)

IOZHigh-impedance output current

ICCInput supply current

4-PORT HUB FOR THE UNIVERSAL SERIAL BUS WITH OPTIONAL SERIAL EEPROM INTERFACE

SLLS413 – FEBRUARY 2000

electrical characteristics over recommended ranges of operating free-air temperature and supply voltage (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

IT+

IT–

hys

o(DRV)

†

Applies for input buffers with hysteresis

‡

Applies for open drain buffers

High-level output voltage

Low-level output voltage

ve input threshold voltage

egative-input threshold voltage

nput hysteresis†

Low-level input current TTL/LVCMOS VI = GND –1 µA High-level input current TTL/L VCMOS VI = V

Driver output impedance USB data lines Static VOH or V Differential input voltage USB data lines 0.8 V ≤ V

T+

–

TTL/LVCMOS IOH = –4 mA VCC –

= 15 kΩ, to GND 2.8

(DRV)

IOH = –12 mA (without R

TTL/LVCMOS IOL = 4 mA 0.5

= 1.5 kΩ to 3.6 V 0.3

(DRV)

IOL = 12 mA (without R TTL/LVCMOS 1.8 V Single-ended TTL/LVCMOS 0.8 V Single-ended TTL/LVCMOS 0.3 0.7 V Single-ended 0.8 V ≤ V TTL/LVCMOS V = VCC or GND USB data lines 0 V ≤ VO ≤ V

0.8 V ≤ V

Normal operation 40 mA

Suspend mode 1 µA

≤ 2.5 V 1.8 V

ICR

≤ 2.5 V 1 V

ICR

≤ 2.5 V 300 500 mV

ICR

‡

≤ 2.5 V 0.2 V

ICR

) VCC –

(DRV)

) 0.5

(DRV)

0.5 V

0.5

±10 µA ±10 µA

1 µA

7.1 19.9 Ω

differential driver switching characteristics over recommended ranges of operating free-air temperature and supply voltage, C

full speed mode

PARAMETER TEST CONDITIONS MIN MAX UNIT

(RFM

O(CRS)

Characterized only. Limits are approved by design and are not production tested.

low speed mode

(RFM)

O(CRS)

Characterized only. Limits are approved by design and are not production tested.

Transition rise time for DPor DM See Figure 1 and Figure 2 4 20 ns Transition fall time for DPor DM See Figure 1 and Figure 2 4 20 ns Rise/fall time matching Signal crossover output voltage

PARAMETER TEST CONDITIONS MIN MAX UNIT

Transition rise time for DPor DM Transition fall time for DPor DM Rise/fall time matching Signal crossover output voltage

= 50 pF (unless otherwise noted)

(tr/tf) × 100 90% 110%

CL = 200 pF to 600 pF, See Figure 1 and Figure 2 75 300 ns

CL = 200 pF to 600 pF, See Figure 1 and Figure 2 75 300 ns (tr/tf) × 100 80% 120% CL = 200 pF to 600 pF 1.3 2.0 V

1.3 2.0 V

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