Texas instruments TUSB1310A Data Manual
PRODUCTPREVIEW
TUSB1310A
USB 3.0 Transceiver
Data Manual
PRODUCT PREVIEW information concerns products in the formative
or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right
to change or discontinue these products withoutnotice.
Literature Number: SLLSE32
November 2010
PRODUCTPREVIEW
TUSB1310A
SLLSE32–NOVEMBER 2010
1 PRODUCT OVERVIEW ......................................................................................................... 7
1.1 Features ...................................................................................................................... 7
1.2 Target Applications ......................................................................................................... 7
1.3 Introduction .................................................................................................................. 8
1.4 Functional Block Diagram .................................................................................................. 8
2 PIN DESCRIPTIONS ........................................................................................................... 10
2.1 Configuration Pins ......................................................................................................... 10
2.2 PIPE ......................................................................................................................... 10
2.3 ULPI ......................................................................................................................... 13
2.3.1 ULPI Modes ..................................................................................................... 13
2.4 Clocking ..................................................................................................................... 14
2.5 JTAG Interface ............................................................................................................. 14
2.6 Reset and Output Control Interface ..................................................................................... 14
2.7 Strap Options .............................................................................................................. 14
2.8 USB Interfaces ............................................................................................................. 15
2.9 Special Connect ........................................................................................................... 15
2.10 Power and Ground ........................................................................................................ 16
3 FUNCTIONAL DESCRIPTION ............................................................................................... 18
3.1 Power On and Reset ...................................................................................................... 18
3.1.1 RESETN and PHY_RESETN – Hardware Reset .......................................................... 18
3.1.2 ULPI Reset – Software Reset ................................................................................. 18
3.1.3 OUT_ENABLE - Output Enable .............................................................................. 18
3.1.4 Power Up Sequence ........................................................................................... 18
3.2 Clocks ....................................................................................................................... 19
3.2.1 Clock Distribution ............................................................................................... 19
3.2.2 Output Clock .................................................................................................... 19
3.3 Power Management ....................................................................................................... 19
3.3.1 USB Power Management ...................................................................................... 20
3.4 Receiver Status ............................................................................................................ 21
3.4.1 Clock Tolerance Compensation .............................................................................. 21
3.4.2 Receiver Detection ............................................................................................. 21
3.4.3 8b/10b Decode Errors .......................................................................................... 22
3.4.4 Elastic Buffer Errors ............................................................................................ 22
3.4.5 Disparity Errors ................................................................................................. 22
3.5 Loopback ................................................................................................................... 22
3.6 Adaptive Equalizer ........................................................................................................ 23
4 REGISTERS ...................................................................................................................... 24
4.1 Register Definitions ........................................................................................................ 24
4.2 Register Map ............................................................................................................... 24
4.2.1 Vendor ID and Product ID (00h-03h) ........................................................................ 24
4.2.2 Function Control (04h-06h) .................................................................................... 25
4.2.3 Interface Control (07h-09h) .................................................................................... 25
4.2.4 Debug (15h) ..................................................................................................... 26
4.2.5 Scratch Register (16-18h) ..................................................................................... 26
5 DESIGN GUIDELINES ......................................................................................................... 27
5.1 Chip Connection on PCB ................................................................................................. 27
2 Contents Copyright © 2010, Texas Instruments Incorporated
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Contents
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TUSB1310A
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5.1.1 USB Connector Pins Connection ............................................................................. 27
5.1.2 Clock Connections .............................................................................................. 28
5.2 Clock Source Requirements ............................................................................................. 29
5.2.1 Clock Source Selection Guide ................................................................................ 29
5.2.2 Oscillator ......................................................................................................... 29
5.2.3 Crystal ............................................................................................................ 30
SLLSE32–NOVEMBER 2010
6 ELECTRICAL SPECIFICATIONS .......................................................................................... 31
6.1 ABSOLUTE MAXIMUM RATINGS ...................................................................................... 31
6.2 RECOMMENDED OPERATING CONDITIONS ....................................................................... 31
6.3 DC CHARACTERISTICS for 1.8-V DIGITAL IO ....................................................................... 31
6.4 DEVICE POWER CONSUMPTION ..................................................................................... 32
6.5 AC Characteristics ......................................................................................................... 32
6.5.1 Power Up and Reset Timing .................................................................................. 32
6.5.2 PIPE Transmit ................................................................................................... 33
6.5.3 PIPE Receive ................................................................................................... 34
6.5.4 ULPI Parameters ............................................................................................... 34
6.5.5 ULPI Clock ....................................................................................................... 34
6.5.6 ULPI Transmit ................................................................................................... 35
6.5.7 ULPI Receive Timing ........................................................................................... 35
6.5.8 Power State Transition Time .................................................................................. 36
Copyright © 2010, Texas Instruments Incorporated Contents 3
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SLLSE32–NOVEMBER 2010
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List of Figures
1-1 Typical Application................................................................................................................. 8
1-2 Functional Block Diagram ........................................................................................................ 9
3-1 Power-Up Sequence............................................................................................................. 19
5-1 Analog Pin Connections......................................................................................................... 27
5-2 USB Standard-A Connector Pin Connection ................................................................................. 28
5-3 USB Standard-B Connector Pin Connection ................................................................................. 28
5-4 Typical Crystal Connections .................................................................................................... 29
6-1 Power Up and Reset Timing.................................................................................................... 33
6-2 PIPE Transmit Timing ........................................................................................................... 33
6-3 PIPE Receive Timing ............................................................................................................ 34
6-4 ULPI Transmit Timing............................................................................................................ 35
6-5 ULPI Receive Timing ............................................................................................................ 35
4 List of Figures Copyright © 2010, Texas Instruments Incorporated
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2-1 Configuration Pins................................................................................................................ 10
2-2 PIPE Signal Description ......................................................................................................... 10
2-3 ULPI Signal Description ......................................................................................................... 13
2-4 ULPI Synchronous and Low Power Mode Functions........................................................................ 13
2-5 Clock Signal Name Description ................................................................................................ 14
2-6 JTAG Signal Name Description ................................................................................................ 14
2-7 Reset and Output Control Signal Description ................................................................................ 14
2-8 Strapping Options ................................................................................................................ 14
2-9 USB Interface Signal Name Descriptions ..................................................................................... 15
2-10 Special Connect Signal Descriptions .......................................................................................... 15
2-11 Power/Ground Signal Descriptions ............................................................................................ 16
3-1 Pin States in Chip Reset ........................................................................................................ 18
3-2 Power States...................................................................................................................... 20
3-3 PIPE Control Pin Matrix ......................................................................................................... 20
3-4 RX_STATUS - SKP .............................................................................................................. 21
3-5 RX_STATUS - Receiver Detection............................................................................................. 21
3-6 8b/10b Decode Errors ........................................................................................................... 22
3-7 Elastic Buffer Errors.............................................................................................................. 22
3-8 Disparity Errors ................................................................................................................... 22
4-1 Register Definitions .............................................................................................................. 24
4-2 Register Map...................................................................................................................... 24
4-3 Vendor ID and Product ID....................................................................................................... 24
4-4 Function Control.................................................................................................................. 25
4-5 Interface Control.................................................................................................................. 25
4-6 Debug.............................................................................................................................. 26
4-7 Scratch Register.................................................................................................................. 26
5-1 Oscillator Specification .......................................................................................................... 29
5-2 Crystal Specification ............................................................................................................. 30
6-1 Power Up and Reset Timing.................................................................................................... 33
6-2 PIPE Transmit Timing ........................................................................................................... 33
6-3 PIPE Receive Timing ............................................................................................................ 34
6-4 ULPI Parameters ................................................................................................................. 34
6-5 ULPI Clock Parameters ......................................................................................................... 34
6-6 ULPI Transmit Timing............................................................................................................ 35
6-7 ULPI Receive Timing ............................................................................................................ 35
SLLSE32–NOVEMBER 2010
List of Tables
Copyright © 2010, Texas Instruments Incorporated List of Tables 5
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SLLSE32–NOVEMBER 2010
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6 List of Tables Copyright © 2010, Texas Instruments Incorporated
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TUSB1310A
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1 PRODUCT OVERVIEW
1.1 Features
1
• Universal Serial Bus (USB)
– Single Port 5.0-Gbps USB 3.0 Physical Layer Transceiver
• One 5.0-Gbps SuperSpeed Conneciton
• One 480-Mbps HS/FS/LS Connection
– Fully Compliant with USB 3.0 Specification, Revision 1.0
– Supports 3+ Meters USB 3.0 Cable Length
– Fully Adaptive Equalizer to Optimize Receiver Sensitivity
– PIPE to Link Layer Controller
• Supports 16-Bit SDR Mode at 250 MHz
• Compliant With PHY Interface for the USB Architectures (PIPE), Version 3.0
– ULPI to Link Layer Controller
• Supports 8-Bit SDR Mode at 60 MHz
• Supports Synchronous Mode and Low Power Mode
• Compliant with UTMI+ Low Pin Interface (ULPI) Specification, Revision 1.1
• General Features
– IEEE 1149.1 JTAG Support
– IEEE 1149.6 JTAG support for the SuperSpeed Port
– Operates on a Single Reference Clock of 40 MHz
– 3.3-, 1.8-, and 1.1-V Supply Voltages
– 1.8-V PIPE and ULPI I/O
– Available in Lead-Free 175-Ball 12- x 12-nF BGA Package (175ZAY)
1.2 Target Applications
• Surveillance Cameras
• Multimedia Handset
• Smartphone
• Digital Still Camera
• Portable Media Player
• Personal Navigation Device
• Audio Dock
• Video IP Phone
• Wireless IP Phone
• Software Defined Radio
SLLSE32–NOVEMBER 2010
USB 3.0 Transceiver
Check for Samples: TUSB1310A
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCT PREVIEW information concerns products in the formative
or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right
to change or discontinue these products without notice.
Copyright © 2010, Texas Instruments Incorporated
PRODUCTPREVIEW
PIPE
ULPI
MCU/CPU
Link Controller
(16 bit 250 MHz)
(8 bit 60 MHz)
Crystal
TUSB1310A
5.0 Gbps
SSTX P/N
SSRX P/N
DP/DM
CLKOUT
TUSB1310A
SLLSE32–NOVEMBER 2010
1.3 Introduction
The TUSB1310A is a single port, 5.0-Gbps USB 3.0 physical layer transceiver operating off of a single
reference clock provided by either a crystal or an external reference clock. The reference clock
frequencies are selectable from 20, 25, 30, and 40 MHz. The TUSB1310A provides the clock to the USB
controller. The use of a single reference clock allows the TUSB1310A to provide a cost effective USB 3.0
solution with few external components and a low implementation cost.
The USB controller interfaces to the TUSB1310A via a PIPE (SuperSpeed) and a ULPI (USB2.0)
interface. The 16-bit PIPE operates off of a 250-MHz interface clock. The ULPI supports 8-bit operations
with a 60-MHz interface clock.
USB 3.0 reduces active and idle power consumption with improved power management features. The
TUSB1310A low power states are controlled by the USB controller via the PIPE interface.
SuperSpeed USB uses existing USB software infrastructure by keeping the existing software interfaces
and software drivers intact. In addition, SuperSpeed USB retains backward compatibility with USB 2.0
based products by using the same form-factor Type-A connector and cables. Existing USB 2.0 devices will
work with new USB 3.0 hosts and new USB 3.0 devices with work with legacy USB 2.0 hosts.
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1.4 Functional Block Diagram
The USB physical layer handles the low level USB protocol and signaling. This includes data serialization
and deserialization, 8b/10b encoding, analog buffers, elastic buffers and receiver detection. It shifts the
clock domain of the data from the USB rate to one that is compatible with the link layer controller.
The SuperSpeed USB contains SSTXP/SSTXN and SSRXP/SSRXP differential pairs and uses the PIPE
to communicate with the link layer controller. The Non-SuperSpeed USB has a DP/DM differential pair and
communicates with the link layer controller via the ULPI. The TUSB1310A reference clock is connected to
an internal crystal oscillator, spread spectrum clock and PLL which provides clocks to all functional blocks
and to the CLKOUT pin for the link layer controller.
A JTAG interface is used for IEEE1149.1 and IEEE1149.6 boundary scan.
Figure 1-1. Typical Application
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Figure 1-2. Functional Block Diagram
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2 PIN DESCRIPTIONS
TYPE DESCRIPTION
I Input
O Output
I/O Input/output
PD, PU Internal pull-down / pull-up
S Strapping pin
P Power Supply
G Ground
2.1 Configuration Pins
The configuration pins are not latched by RESETN.
Table 2-1. Configuration Pins
SIGNAL NAME TYPE PIN NO. MODE NAME DESCRIPTION
PHY_MODE1 I, PD H12 USB Must be set to 0. Operates as USB 3.0 transceiver.
PHY_MODE0 I, PU J12 USB Must be set to 1. Operates as USB 3.0 transceiver.
2.2 PIPE
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The TUSB1310A supports 16-bit SDR mode with a 250-MHz clock.
SIGNAL NAME TYPE BALL NO. DESCRIPTION
TX_CLK I K1
TX_DATA15 G2
TX_DATA14 H2
TX_DATA13 H1
TX_DATA12 J2
TX_DATA11 L3
TX_DATA10 L2
TX_DATA9 M2
TX_DATA8 M1
TX_DATA7 N1
TX_DATA6 P1
TX_DATA5 N2
TX_DATA4 P2
TX_DATA3 N3
TX_DATA2 P3
TX_DATA1 N4
TX_DATA0 P5
TX_DATAK1 G1
TX_DATAK0 J1
PCLK O A6 to this clock. This clock operates at 250 MHz. The rising edge of the clock is the reference
I The 16 bits represent 2 symbols of transmit data where TX_DATA7-0 is the first symbol to
I
Table 2-2. PIPE Signal Description
TX_DATA and TX_DATAK clock for source synchronous PIPE. This clock frequency is
the same as PCLK frequency. The rising edge of the clock is the reference for all signals.
Parallel USB SuperSpeed data input bus.
be transmitted, and TX_DATA15-8 is the second symbol.
Data/Control for the symbols of transmit data. TX_DATAK0 corresponds to the low-byte of
TX_DATA, TX_DATAK1 to the upper byte.
Parallel interface data clock. All data movement across the parallel PIPE is synchronous
for all signals.
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SIGNAL NAME TYPE BALL NO. DESCRIPTION
RX_DATA15 B9
RX_DATA14 A9
RX_DATA13 A8
RX_DATA12 B8
RX_DATA11 B5
RX_DATA10 B4
RX_DATA9 A4
RX_DATA8 B3
RX_DATA7 A3
RX_DATA6 A2
RX_DATA5 B1
RX_DATA4 C2
RX_DATA3 C1
RX_DATA2 D1
RX_DATA1 D2
RX_DATA0 E2
RX_DATAK1 B7 Data/Control for the symbols of receive data. RX_DATAK0 corresponds to the low-byte of
RX_DATAK0 A7
RX_VALID O F1 Active High. Indicates symbol lock and valid data on RX_DATA and RX_DATAK.
CONTROL AND STATUS SIGNALS
PHY_RESETN I, PU J3 Active Low. Resets the transmitter and receiver. This signal is asynchronous.
TX_DETRX_LPBK I, PD M6
TX_ELECIDLE I K3 Active High. Forces TX output to electrical idle depending on the power state.
RX_ELECIDLE F3
RX_STATUS2 C7
RX_STATUS1 C6 BIT 2 BIT 1 BIT 0 DESCRIPTION
RX_STATUS0 C5 0 0 0 Received data OK
O The 16 bits represent 2 symbols of receive data where RX_DATA7-0 is the first symbol
O RX_DATA, RX_DATAK1 to the upper byte. A value of zero indicates a data byte; a value
S, I/O, Active High. While de-asserted with the PHY in P0, P1, P2, or P3, indicates detection of
PD LFPS.
O
POWER_DOWN1 G3 Power up and down the transceiver power states.
POWER_DOWN0 H3 BIT 1 BIT 0 DESCRIPTION
I
SLLSE32–NOVEMBER 2010
Table 2-2. PIPE Signal Description (continued)
Parallel USB SuperSpeed data output bus.
received, and RX_DATA15-8 is the second.
of 1 indicates a control byte.
Active High. Used to tell the PHY to begin a receiver detection operation or to begin
loopback.
Encodes receiver status and error codes for the received data stream when receiving
data.
0 0 1 1 SKP ordered set added
0 1 0 1 SKP ordered set removed
0 1 1 Receiver detected
1 0 0 8B/10B decode error
1 0 1 Elastic buffer overflow
Elastic buffer underflow.
1 1 0 This error code is not used if the elasticity buffer is
operating in the nominal buffer empty mode.
1 1 1 Receive disparity error
0 0 P0, normal operation
0 1 P1, low recovery time latency, power saving state
1 0 P2, longer recovery time latency, low power state
1 1 P3, lowest power state
When transitioning from P3 to P0, the signaling is asynchronous.
Copyright © 2010, Texas Instruments Incorporated PIN DESCRIPTIONS 11
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SIGNAL NAME TYPE BALL NO. DESCRIPTION
PHY_STATUS E3
PWRPRESENT O H11 Indicates the presence of VBUS
CONFIGURATION PINS
TX_ONESZEROS I, PD M4 the transmitter to transmit an alternating sequence of 50 - 250 ones and 50 - 250 zeros –
TX_DEEMPH1 K11
TX_DEEMPH0 L11 BIT 1 BIT 0 DESCRIPTION
TX_MARGIN2 M11 Selects transmitter voltage levels
TX_MARGIN1 M10 BIT 2 BIT 1 BIT 0 TX_SWING DESCRIPTION
TX_MARGIN0 M9 0 0 0 0
S, I/O, management state transitions, rate change, and receiver detection. When this signal
PD transitions during entry and exit from P3 and PCLK is not running, then the signaling is
I, PD, PU
I, PD
TX_SWING I, PD M5 0 Full swing
RX_POLARITY I, PD C8
RX_TERMINATION I, PD D3 0 Terminations removed
RATE I, PU L6
ELAS_BUF_MODE I, PD C9 0 Nominal half full buffer mode
Table 2-2. PIPE Signal Description (continued)
Active High. Used to communicate completion of several PHY func-tions including power
asynchronous.
Active High. Used only when transmitting USB compliance pat-terns CP7 or CP8. Causes
regardless of the state of the TX_DATA interface.
Selects transmitter de-emphasis. When the MAC changes, the TUSB1310A starts to
transmit with the new setting within 128 ns.
0 0 -6 dB de-emphasis
0 1 -3.5 dB de-emphasis
1 0 No de-emphasis
1 1 Reserved
Normal operating range
800 mV - 1200 mV
0 0 0 1
0 0 1
0 1 0
0 1 1
1 0 200 mV - 400 mV
1 1 100 mV - 200 mV
Controls transmitter voltage swing level
1 Half swing
Active High. Tells PHY to do a polarity inversion on the received data. Inverted data show
up on RX_DATA15-0 within 20 PCLK clocks after RX_POLARITY is asserted.
0 PHY does no polarity inversion.
1 PHY does polarity inversion.
Controls presence of receiver terminations
1 Terminations present
Controls the link signaling rate
The RATE is always 1.
Selects elasticity buffer operating mode
1 Nominal empty buffer mode
Don't care
0 800 mV - 1200 mV
1 400 mV - 700 mV
0 700 mV - 900 mV
1 300 mV - 500 mV
0 400 mV - 600 mV
1 200 mV - 400 mV
Normal operating range
400 mV - 700 mV
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