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TRF7964A Multiprotocol Fully Integrated 13.56-MHz RFID Reader and Writer IC

1 Device Overview

1.1 Features

• Completely Integrated Protocol Handling for ISO/IEC 15693, ISO/IEC 18000-3, ISO/IEC 14443 A and B, and FeliCa™

• Integrated State Machine for ISO/IEC 14443 A Anticollision (Broken Bytes) Operation

• Input Voltage Range: 2.7 VDC to 5.5 VDC

• Programmable Output Power: +20 dBm (100 mW), +23 dBm (200 mW)

• Programmable I/O Voltage Levels From 1.8 VDC to 5.5 VDC

• Programmable System Clock Frequency Output (RF, RF/2, RF/4) from 13.56-MHz or 27.12-MHz Crystal or Oscillator

1.2 Applications

• Public Transport or Event Ticketing

• Passport or Payment (POS) Reader Systems

• Product Identification or Authentication

TRF7964A

SLOS787J –MAY 2012–REVISED MARCH 2020

• Integrated Voltage Regulator Output for Other System Components (MCU, Peripherals, Indicators), 20 mA (Max)

• Programmable Modulation Depth

• Dual Receiver Architecture With RSSI for Elimination of "Read Holes" and Adjacent Reader System or Ambient In-Band Noise Detection

• Programmable Power Modes for Ultra Low-Power System Design (Power Down <1 µA)

• Parallel or SPI Interface (With 127-Byte FIFO)

• Temperature Range: –40°C to 110°C

• 32-Pin QFN Package (5 mm × 5 mm)

• Medical Equipment or Consumables

• Access Control, Digital Door Locks

1.3 Description

The TRF7964A device is an integrated analog front end (AFE) and multiprotocol data-framing device for a

13.56-MHz NFC/RFID reader and writer system supporting ISO/IEC 14443 A and B, Sony FeliCa, and ISO/IEC 15693. Pin-to-pin and firmware compatible with the superset device TRF7970A. Built-in programming options make the device suitable for a wide range of applications for proximity and vicinity identification systems.

The device is configured by selecting the desired protocol in the control registers. Direct access to all control registers allows fine tuning of various reader parameters as needed.

The TRF7964A device supports data rates up to 848 kbps with all framing and synchronization tasks for the ISO protocols onboard. Other standards and even custom protocols can be implemented by using one of the direct modes the device offers. These direct modes let the user fully control the AFE and also gain access to the raw subcarrier data or the unframed, but already ISO-formatted, data and the associated (extracted) clock signal.

The receiver system has a dual-input receiver architecture to maximize communication robustness. The receivers also include various automatic and manual gain control options. The received signal strength from transponders, ambient sources, or internal levels is available in the RSSI register.

A SPI or parallel interface can be used for the communication between the MCU and the TRF7964A device. When the built-in hardware encoders and decoders are used, transmit and receive functions use a 127-byte FIFO register. For direct transmit or receive functions, the encoders or decoders can be bypassed so the MCU can process the data in real time.

The TRF7964A device supports a wide supply voltage range of 2.7 V to 5.5 V and data communication levels from 1.8 V to 5.5 V for the MCU I/O interface.

The transmitter has selectable output power levels of 100 mW (+20 dBm) or 200 mW (+23 dBm) equivalent into a 50-Ω load when using a 5-V supply and supports OOK and ASK modulation with selectable modulation depth.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

MUX

RX_IN1

RX_IN2

Phase and

Amplitude

Detector

Gain

RSSI

(AUX)

Logic

Level Shifter

State

Control

Logic

(Control

Registers and

Command

Logic)

127-Byte

FIFO

MCU

Interface

VDD_I/O

I/O_0

I/O_1

I/O_2

I/O_3

I/O_4

I/O_5

I/O_6

I/O_7

IRQ

SYS_CLK

DATA_CLK

ISO Protocol Handling

Decoder

RSSI

(External)

Gain

RSSI

(Main)

Filter

and AGC

Digitizer

Bit

Framing

Serial

Conversion

CRC and Parity

Transmitter

Analog Front End

TX_OUT

VDD_PA

VSS_PA

Digital Control State Machine

Crystal or Oscillator

Timing System

EN2

ASK/OOK

MOD

OSC_IN

OSC_OUT

Voltage Supply Regulator Systems

(Supply Regulators and Reference Voltages)

VSS_A

VSS_RF

VDD_RF

VDD_X

VSS_D

VSS

VIN

VDD_A

BAND_GAP

RF Level

Detector

Phase and

Amplitude

Detector

TRF7964A

SLOS787J –MAY 2012–REVISED MARCH 2020

The built-in programmable auxiliary voltage regulator delivers up to 20 mA to supply an MCU and additional external circuits within the reader system.

Start evaluating the TRF7964A multiprotocol transceiver IC with the DLP-7970ABP of the superset device.

PART NUMBER PACKAGE BODY SIZE

TRF7964ARHB VQFN (32) 5 mm × 5 mm

1.4 Functional Block Diagram

Figure 1-1 shows the block diagram.

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Device Information

Figure 1-1. Block Diagram

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1 Device Overview ......................................... 1

1.1 Features .............................................. 1

1.2 Applications........................................... 1

1.3 Description............................................ 1

1.4 Functional Block Diagram ............................ 2

2 Revision History ......................................... 4

3 Device Characteristics.................................. 5

3.1 Related Products ..................................... 5

4 Terminal Configuration and Functions.............. 6

4.1 Pin Diagram .......................................... 6

4.2 Signal Descriptions ................................... 6

5 Specifications ............................................ 8

5.1 Absolute Maximum Ratings .......................... 8

5.2 ESD Ratings.......................................... 8

5.3 Recommended Operating Conditions ................ 8

5.4 Electrical Characteristics ............................. 9

5.5 Thermal Resistance Characteristics ................ 10

5.6 Switching Characteristics ........................... 10

6 Detailed Description ................................... 11

6.1 Overview ............................................ 11

6.2 System Block Diagram.............................. 12

6.3 Power Supplies...................................... 12

6.4 Receiver – Analog Section.......................... 18

6.5 Receiver – Digital Section........................... 19

6.6 Oscillator Section ................................... 24

6.7 Transmitter – Analog Section ....................... 25

6.8 Transmitter – Digital Section ........................ 26

6.9 Transmitter – External Power Amplifier and

Subcarrier Detector ................................. 27

6.10 TRF7964A IC Communication Interface ............ 27

6.11 TRF7964A Initialization ............................. 45

6.12 Special Direct Mode for Improved MIFARE™

Compatibility......................................... 45

6.13 Direct Commands from MCU to Reader ............ 46

6.14 Register Description................................. 49

7 Applications, Implementation, and Layout........ 67

7.1 TRF7964A Reader System Using SPI With SS

Mode ................................................ 67

7.2 Layout Considerations .............................. 68

7.3 Impedance Matching TX_Out (Pin 5) to 50 Ω ...... 68

7.4 Reader Antenna Design Guidelines ................ 69

8 Device and Documentation Support ............... 70

8.1 Getting Started and Next Steps..................... 70

8.2 Device Nomenclature ............................... 70

8.3 Tools and Software ................................. 71

8.4 Documentation Support ............................. 71

8.5 Support Resources.................................. 72

8.6 Trademarks.......................................... 72

8.7 Electrostatic Discharge Caution..................... 72

8.8 Glossary............................................. 72

9 Mechanical, Packaging, and Orderable

Information .............................................. 73

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2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from March 28, 2017 to March 11, 2020 Page

• Removed links to obsolete EVMs in Section 1.3 Description................................................................... 2

• Removed "(Optional)" from the step that begins "Write the Regulator and I/O Control register (0x0B)..." in

Section 6.11 TRF7964A Initialization............................................................................................. 45

• Updated linked documents in Section 7.4 Reader Antenna Design Guidelines ............................................ 69

• Removed obsolete EVMs in Section 8.3 Tools and Software................................................................. 71

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3 Device Characteristics

Table 3-1 lists the supported modes of operation for the TRF7964A device.

Table 3-1. Supported Protocols

SUPPORTED PROTOCOLS

ISO/IEC 14443 A and B ISO/IEC 15693,

106 kbps 212 kbps 424 kbps 848 kbps 212 kbps, 424 kbps

✓ ✓ ✓ ✓ ✓ ✓

3.1 Related Products

For information about other devices in this family of products or related products, see the following links.

Products for TI Wireless Connectivity Connect more with the industry’s broadest wireless connectivity

portfolio.

Products for NFC / RFID TI provides one of the industry’s most differentiated NFC and RFID product

portfolios and is your solution to meet a broad range of NFC connectivity and RFID identification needs.

Companion Products for TRF7964A Review products that are frequently purchased or used with this

product.

Reference Designs for TRF7964A The TI Designs Reference Design Library is a robust reference

design library that spans analog, embedded processor, and connectivity. Created by TI experts to help you jump start your system design, all TI Designs include schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download designs at ti.com/tidesigns.

ISO/IEC 18000-3

(Mode 1)

TRF7964A

FeliCa

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VDD_A

VIN

VDD_RF

VDD_PA

TX_OUT

VSS_PA

VSS_RX

RX_IN1

I/O_7

RX_IN2

VSS

ASK/OOK

IRQ

MOD

VSS_A

VDD_I/O

Pad

VDD_X

OSC_IN

OSC_OUT

VSS_D

SYS_CLK

DATA_CLK

EN2

9 10

11 12

15 16

32 31 30

29 28

26 25

I/O_6

I/O_5

I/O_4

I/O_3

I/O_2

I/O_1

I/O_0

TRF7964A

SLOS787J –MAY 2012–REVISED MARCH 2020

4 Terminal Configuration and Functions

4.1 Pin Diagram

Figure 4-1 shows the pinout for the 32-pin RHB package.

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Figure 4-1. 32-Pin RHB Package (Top View)

4.2 Signal Descriptions

Table 4-1 describes the signals.

TERMINAL

NAME NO.

DD_A

DD_RF

DD_PA

TX_OUT 5 OUT RF output (selectable output power, 100 mW or 200 mW, with VDD= 5 V) V

SS_PA

SS_RX

RX_IN1 8 INP Main RX input RX_IN2 9 INP Auxiliary RX input V

BAND_GAP 11 OUT Bandgap voltage (VBG= 1.6 V); internal analog voltage reference

ASK/OOK 12 BID

1 OUT Internal regulated supply (2.7 V to 3.4 V) for analog circuitry 2 SUP External supply input to chip (2.7 V to 5.5 V) 3 OUT Internal regulated supply (2.7 V to 5 V), normally connected to V 4 INP Supply for PA; normally connected externally to V

6 SUP Negative supply for PA; normally connected to circuit ground 7 SUP Negative supply for RX inputs; normally connected to circuit ground

10 SUP Chip substrate ground

TYPE

(1)

(1) SUP = Supply, INP = Input, BID = Bidirectional, OUT = Output 6

Table 4-1. Terminal Functions

DESCRIPTION

DD_PA

Selection between ASK and OOK modulation (0 = ASK, 1 = OOK) for direct mode 0 or 1. Can be configured as an output to provide the received analog signal output.

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DD_RF

(pin 3)

(pin 4)

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Table 4-1. Terminal Functions (continued)

TERMINAL

NAME NO.

IRQ 13 OUT Interrupt request

MOD 14

SS_A

DD_I/O

15 SUP Negative supply for internal analog circuits; connected to GND

16 INP Supply for I/O communications (1.8 V to VIN) level shifter. VINshould be never exceeded. I/O_0 17 BID I/O pin for parallel communication I/O_1 18 BID I/O pin for parallel communication

I/O_2 19 BID

I/O_3 20 BID

I/O_4 21 BID

I/O_5 22 BID

I/O_6 23 BID

I/O_7 24 BID

EN2 25 INP DATA_CLK 26 INP Data clock input for MCU communication (parallel and serial)

(1)

TYPE

DESCRIPTION

INP External data modulation input for direct mode 0 or 1

OUT Subcarrier digital data output (see registers 0x1A and 0x1B)

I/O pin for parallel communication TX enable (in special direct mode) I/O pin for parallel communication TX data (in special direct mode) I/O pin for parallel communication Slave select signal in SPI mode I/O pin for parallel communication Data clock output in direct mode 1 and special direct mode I/O pin for parallel communication MISO for serial communication (SPI) Serial bit data output in direct mode 1 or subcarrier signal in direct mode 0 I/O pin for parallel communication. MOSI for serial communication (SPI) Selection of power down mode. If EN2 is connected to VIN, then V

down mode 2 (for example, to supply the MCU).

is active during power

DD_X

TRF7964A

If EN = 1 (EN2 = don't care) the system clock for MCU is configured. Depending on the crystal that is used, options are as follows (see register 0x09):

SYS_CLK 27 OUT

13.56-MHz crystal: Off, 3.39 MHz, 6.78 MHz, or 13.56 MHz

27.12-MHz crystal: Off, 6.78 MHz, 13.56 MHz, or 27.12 MHz

If EN = 0 and EN2 = 1, then system clock is set to 60 kHz EN 28 INP Chip enable input (If EN = 0, then chip is in sleep or power-down mode). V

SS_D

29 SUP Negative supply for internal digital circuits

OSC_OUT 30 OUT Crystal or oscillator output

OSC_IN 31

DD_X

32 OUT

INP Crystal or oscillator input

OUT Crystal oscillator output

Internally regulated supply (2.7 V to 3.4 V) for digital circuit and external devices (for example,

an MCU) Thermal Pad PAD SUP Chip substrate ground

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5 Specifications

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5.1 Absolute Maximum Ratings

(1) (2)

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

V I

Input voltage range –0.3 6 V

Maximum current V

Maximum operating virtual junction temperature

Storage temperature –55 150 °C

STG

Any condition 140 °C Continuous operation, long-term reliability

(3)

150 mA

125 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to substrate ground terminal VSS. (3) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may

result in reduced reliability or lifetime of the device.

5.2 ESD Ratings

VALUE UNIT

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins

(ESD)

Electrostatic discharge

Charged-device model (CDM), per JEDEC specification JESD22-C101, all

(2)

pins Machine model (MM) ±200 V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±2000

V may actually have higher performance. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V

may actually have higher performance.

(1)

±2000 V

±500 V

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

V T T

Operating input voltage 2.7 5 5.5 V

Operating ambient temperature –40 25 110 °C

Operating virtual junction temperature –40 25 125 °C

Input voltage, logic low

Input voltage threshold, logic high

I/O lines, IRQ, SYS_CLK, DATA_CLK, EN, EN2, ASK/OOK, MOD

MIN TYP MAX UNIT

0.2 ×

DD_I/O

0.8 ×

DD_I/O

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5.4 Electrical Characteristics

TYP operating conditions are TA= 25°C, VIN = 5 V, full-power mode (unless otherwise noted) MIN and MAX operating conditions are over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Low-level output voltage

High-level output voltage

All building blocks disabled, including

PD1

PD2

Supply current in power down mode 1

Supply current in power down mode 2 (sleep mode)

supply-voltage regulators; measured after 500-ms settling time (EN = 0, EN2 = 0)

The SYS_CLK generator and V remain active to support external circuitry;

DD_X

measured after 100-ms settling time (EN = 0, EN2 = 1)

Oscillator running, supply-voltage

STBY

ON1

ON2

ON3

POR

DD_A

DD_X

VDD_Xmax

RFOUT

RFIN

RF_INmax

RF_INmin

SYS_CLK

CRYSTAL

D_CLKmax

OUT

SYS_CLK

Supply current in stand-by mode

regulators in low-consumption mode (EN = 1, EN2 = x)

Supply current without antenna driver current

Supply current, TX (half power)

Supply current, TX (full power) Power-on-reset voltage Input voltage at V

Oscillator, regulators, RX and AGC active, TX is off

Oscillator, regulators, RX and AGC and TX active, P

OUT

= 100 mW

Oscillator, regulators, RX and AGC and TX active, P

OUT

= 200 mW

1.4 2 2.6 V Bandgap voltage (pin 11) Internal analog reference voltage 1.5 1.6 1.7 V Regulated output voltage for analog

circuitry (pin 1)

VIN= 5 V 3.1 3.4 3.8 V

Regulated supply for external circuitry Output voltage pin 32, VIN= 5 V 3.1 3.4 3.8 V Maximum output current of V

DD_X

Antenna driver output resistance

(1)

Output current pin 32, VIN= 5 V 20 mA Half-power mode, VIN= 2.7 V to 5.5 V 8 12

Full-power mode, VIN= 2.7 V to 5.5 V 4 6 RX_IN1 and RX_IN2 input resistance 4 10 20 kΩ Maximum RF input voltage at RX_IN1

and RX_IN2 Minimum RF input voltage at RX_IN1

and RX_IN2 (input sensitivity)

(2)

RF_INmax

SUBCARRIER

should not exceed V

= 424 kHz 1.4 2.5

= 848 kHz 2.1 3 SYS_CLK frequency In power mode 2, EN = 0, EN2 = 1 25 60 120 kHz Carrier frequency Defined by external crystal 13.56 MHz

Crystal run-in time

Maximum DATA_CLK frequency

(4)

Time until oscillator stable bit is set (register 0x0F)

Depends on capacitive load on the I/O lines, TI recommends 2 MHz

(3)

(4)

Output resistance I/O_0 to I/O_7 500 800 Ω Output resistance R

SYS_CLK

(1) Antenna driver output resistance (2) Measured with subcarrier signal at RX_IN1 or RX_IN2 and measured the digital output at MOD pin with register 0x1A bit 6 = 1. (3) Depends on the crystal parameters and components (4) TI recommends a DATA_CLK speed of 2 MHz. Higher data clock depends on the capacitive load. Maximum SPI clock speed should not

exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. MISO driver has a typical output resistance of 400 Ω (12-ns time constant when 30-pF load used).

DD_I/O

0.2 ×

0.8 ×

0.5 5 µA

120 200 µA

1.9 3.5 mA

10.5 14 mA

70 78 mA

130 150 mA

3.5 V

3 ms

2 4 10 MHz

200 400 Ω

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5.5 Thermal Resistance Characteristics

PACKAGE θ

(1)

TA≤ 25°C TA≤ 85°C

POWER RATING

RHB (32 pin) 31°C/W 36.4°C/W 2.7 W 1.1 W

(1) This data was taken using the JEDEC standard high-K test PCB. (2) Power rating is determined with a junction temperature of 125°C. This is the temperature at which distortion starts to increase

substantially. Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long-term reliability.

(2)

5.6 Switching Characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

LO/HI

STE,LEAD

STE,LAG

STE,DIS

SU,SI

HD,SI

SU,SO

HD,SO

VALID,SO

DATA_CLK time high or low, one half of DATA_CLK at 50% duty cycle

Slave select lead time, slave select low to clock 200 ns Slave select lag time, last clock to slave select high 200 ns Slave select disable time, slave select rising edge to

next slave select falling edge MOSI input data setup time 15 ns MOSI input data hold time 15 ns MISO input data setup time 15 ns MISO input data hold time 15 ns

MISO output data valid time

Depends on capacitive load on the I/O lines

(1)

DATA_CLK edge to MISO valid, CL≤ 30 pF

250 62.5 50 ns

300 ns

30 50 75 ns

(1) TI recommends a DATA_CLK speed of 2 MHz. Higher data clock depends on the capacitive load. Maximum SPI clock speed should not

exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. MISO driver has a typical output resistance of 400 Ω (12-ns time constant when 30-pF load used).

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MCU

(MSP430 or ARM)

Matching

DD_X

DD_I/O

TX_OUT

RX_IN 1

RX_IN2

VSSV

Parallel

or SPI

Supply: 2.7 V to 5.5 V

Crystal

13.56 MHz

XIN

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6 Detailed Description

6.1 Overview

6.1.1 RFID – Reader and Writer

The is a high-performance 13.56-MHz HF RFID transceiver IC composed of an integrated analog front end (AFE) and a built-in data framing engine for ISO/IEC 15693, ISO/IEC 14443 A and B, and FeliCa. This includes data rates up to 848 kbps for ISO/IEC 14443 with all framing and synchronization tasks on board (in default mode). This architecture lets the customer build a complete cost-effective yet highperformance multiprotocol 13.56-MHz RFID system together with a low-cost microcontroller.

Other standards and even custom protocols can be implemented by using either of the direct modes that the device offers. These direct modes (0 and 1) allow the user to fully control the analog front end (AFE) and also gain access to the raw subcarrier data or the unframed but already ISO formatted data and the associated (extracted) clock signal.

The receiver system has a dual input receiver architecture. The receivers also include various automatic and manual gain control options. The received input bandwidth can be selected to cover a broad range of input subcarrier signal options.

The received signal strength from transponders, ambient sources, or internal levels is available through the RSSI register. The receiver output is selectable among a digitized subcarrier signal and any of the integrated subcarrier decoders. The selected subcarrier decoder delivers the data bit stream and the data clock as outputs.

TRF7964A

SLOS787J –MAY 2012–REVISED MARCH 2020

The TRF7964A also includes a receiver framing engine. This receiver framing engine performs the CRC or parity check, removes the EOF and SOF settings, and organizes the data in bytes for ISO/IEC 14443 A and B, ISO/IEC 15693, and FeliCa protocols. Framed data is then accessible to the microcontroller (MCU) through a 127-byte FIFO register.

Figure 6-1. Application Block Diagram

A parallel or serial interface (SPI) can be used for the communication between the MCU and the TRF7964A reader. When the built-in hardware encoders and decoders are used, transmit and receive functions use a 127-byte FIFO register. For direct transmit or receive functions, the encoders and decoders can be bypassed so that the MCU can process the data in real time. The TRF7964A supports data communication voltage levels from 1.8 V to 5.5 V for the MCU I/O interface. The transmitter has selectable output-power levels of 100 mW (+20 dBm) or 200 mW (+23 dBm) equivalent into a 50-Ω load when using a 5-V supply.

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MUX

RX_IN1

RX_IN2

Phase and

Amplitude

Detector

Gain

RSSI

(AUX)

Logic

Level Shifter

State

Control

Logic

(Control

Registers and

Command

Logic)

127-Byte

FIFO

MCU

Interface

VDD_I/O

I/O_0

I/O_1

I/O_2

I/O_3

I/O_4

I/O_5

I/O_6

I/O_7

IRQ

SYS_CLK

DATA_CLK

ISO Protocol Handling

Decoder

RSSI

(External)

Gain

RSSI

(Main)

Filter

and AGC

Digitizer

Bit

Framing

Serial

Conversion

CRC and Parity

Transmitter

Analog Front End

TX_OUT

VDD_PA

VSS_PA

Digital Control State Machine

Crystal or Oscillator

Timing System

EN2

ASK/OOK

MOD

OSC_IN

OSC_OUT

Voltage Supply Regulator Systems

(Supply Regulators and Reference Voltages)

VSS_A

VSS_RF

VDD_RF

VDD_X

VSS_D

VSS

VIN

VDD_A

BAND_GAP

RF Level

Detector

Phase and

Amplitude

Detector

TRF7964A

SLOS787J –MAY 2012–REVISED MARCH 2020

The transmitter supports OOK and ASK modulation with selectable modulation depth. The TRF7964A also includes a data transmission engine that comprises low-level encoding for ISO/IEC 15693, ISO/IEC 14443 A and B, and FeliCa. Included with the transmit data coding is the automatic generation of Start Of Frame (SOF), End Of Frame (EOF), Cyclic Redundancy Check (CRC), and parity bits.

Several integrated voltage regulators ensure a proper power-supply noise rejection for the complete reader system. The built-in programmable auxiliary voltage regulator V 20 mA to supply a microcontroller and additional external circuits within the reader system.

6.2 System Block Diagram

Figure 6-2 shows a block diagram of the TRF7964A.

(pin 32), is able to deliver up to

DD_X

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6.3 Power Supplies

The TRF7964A positive supply input VIN(pin 2) sources three internal regulators with output voltages V

DD_RF

, V

DD_A

and V be connected as indicated in reference schematics. These regulators provide a high power supply reject ratio (PSRR) as required for RFID reader systems. All regulators are supplied by VIN(pin 2).

The regulators are not independent and have common control bits in register 0x0B for output voltage setting. The regulators can be configured to operate in either automatic or manual mode (register 0x0B, bit 7). The automatic regulator setting mode ensures an optimal compromise between PSRR and the highest possible supply voltage for RF output (to ensure maximum RF power output). The manual mode allows the user to manually configure the regulator settings. For applications in which the TRF7964A may be subjected to external noise, manually reducing the regulator settings can improve RF performance.

Figure 6-2. System Block Diagram

. All regulators use external bypass capacitors for supply noise filtering and must

DD_X

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6.3.1 Supply Arrangements

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Regulator Supply Input: V

The positive supply at VIN(pin 2) has an input voltage range of 2.7 V to 5.5 V. VINprovides the supply input sources for three internal regulators with the output voltages V

DD_RF

, V

DD_A

, and V

DD_X

. External

bypass capacitors for supply noise filtering must be used (per reference schematics).

NOTE

VINmust be the highest voltage supplied to the TRF7964A.

RF Power Amplifier Regulator: V

The V

(pin 3) regulator is supplying the RF power amplifier. The voltage regulator can be set for

DD_RF

either 5-V or 3-V operation. External bypass capacitors for supply noise filtering must be used (per reference schematics). When configured for 5-V manual-operation, the V

output voltage can be set

DD_RF

from 4.3 V to 5 V in 100-mV steps. In 3-V manual-operation, the output can be programmed from 2.7 V to

3.4 V in 100-mV steps. The maximum output current capability for 5-V operation is 150 mA and for 3-V operation is 100 mA.

Analog Supply Regulator: V

Regulator V

(pin 1) supplies the analog circuits of the device. The output voltage setting depends on

DD_A

the input voltage and can be set for 5-V and 3-V operation. When configured for 5-V manual-operation, the output voltage is fixed at 3.4 V. External bypass capacitors for supply noise filtering must be used (per reference schematics). When configured for 3-V manual-operation, the V

output can be set from 2.7 V

DD_A

to 3.4 V in 100-mV steps (see Table 6-2).

NOTE

The configuration of V V

output current should not exceed 20 mA.

DD_X

Digital Supply Regulator: V

The digital supply regulator V

DD_X

and V

DD_A

(pin 32) provides the power for the internal digital building blocks and

DD_X

regulators are not independent from each other. The

DD_X

can also be used to supply external electronics within the reader system. When configured for 3-V operation, the output voltage can be set from 2.7 to 3.4 V in 100-mV steps. External bypass capacitors for supply noise filtering must be used (per reference schematics).

NOTE

The configuration of the V The V

output current should not exceed 20 mA.

DD_X

DD_A

and V

regulators are not independent from each other.

DD_X

By default, the regulators are set in automatic regulator setting mode. In this mode, the regulators are automatically set every time the system is activated by setting EN input High or each time the automatic regulator setting bit, B7 in register 0x0B is set to a 1. The action is started on the 0 to 1 transition. This means that, if the user wants to rerun the automatic setting from a state in which the automatic setting bit is already high, the automatic setting bit (B7 in register 0x0B) should be changed: 1-0-1.

By default, the regulator setting algorithm sets the regulator outputs to a "Delta Voltage" of 400 mV below VIN, but not higher than 5 V for V

and 3.4 V for V

DD_RF

DD_A

and V

DD_A

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Power Amplifier Supply: V

The power amplifier of the TRF7964A is supplied through V RF power amplifier is externally connected to the regulator output V

I/O Level Shifter Supply: V

The TRF7964A has a separate supply input V

DD_PA

DD_I/O

(pin 4). The positive supply pin for the

DD_PA

(pin 3).

DD_RF

(pin 16) for the built-in I/O level shifter. The supported

DD_I/O

input voltage ranges from 1.8 V to VIN, not exceeding 5.5 V. Pin 16 is used to supply the I/O interface pins (I/O_0 to I/O_7), IRQ, SYS_CLK, and DATA_CLK pins of the reader. In typical applications, V directly connected to V

DD_X

, while V

also supplies the MCU. This ensures that the I/O signal levels of

DD_X

DD_I/O

the MCU match the logic levels of the TRF7964A.

Negative Supply Connections: VSS, V

The negative supply connections V

SS_X

The substrate connection is VSS(pin 10), the analog negative supply is V supply is V the RF receiver V

(pin 29), the RF output stage negative supply is V

SS_D

(pin 7).

SS_RX

SS_TX

, V

SS_RX

, V

SS_A

, V

SS_PA

of each functional block are all externally connected to GND.

(pin 15), the logic negative

SS_A

(pin 6), and the negative supply for

SS_PA

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6.3.2 Supply Regulator Settings

The input supply voltage mode of the reader needs to be selected. This is done in the Chip Status Control register (0x00). Bit 0 in register 0x00 selects between 5-V or 3-V input supply voltage. The default configuration is 5 V, which reflects an operating supply voltage range of 4.3 V to 5.5 V. If the supply voltage is below 4.3 V, the 3-V configuration should be used.

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As V

is increased, the system can become more susceptible to noise coupling on the RX lines. For

DD_RF

minimum noise coupling, TI recommends using the value of 0x00. For improved range, higher V voltages may be set, but complete system testing is required to determine the value which provides optimal performance.

The various regulators can be configured to operate in automatic or manual mode. This is done in the Regulator and I/O Control register (0x0B), as shown in Table 6-1 and Table 6-2.

Table 6-1. Supply Regulator Setting: 5-V System

(hex)

OPTION BITS SETTING IN REGULATOR CONTROL REGISTER

B7 B6 B5 B4 B3 B2 B1 B0

Automatic Mode (default)

0B 1 x x x x x 0 0 Automatic regulator setting 400-mV difference

Manual Mode

0B 0 x x x x 1 1 1 V 0B 0 x x x x 1 1 0 V 0B 0 x x x x 1 0 1 V 0B 0 x x x x 1 0 0 V 0B 0 x x x x 0 1 1 V 0B 0 x x x x 0 1 0 V 0B 0 x x x x 0 0 1 V 0B 0 x x x x 0 0 0 V

(1) x = Don't care

(1)

COMMENTS

DD_RF DD_RF DD_RF DD_RF DD_RF DD_RF DD_RF DD_RF

= 5 V, V = 4.9 V, V = 4.8 V, V = 4.7 V, V = 4.6 V, V = 4.5 V, V = 4.4 V, V = 4.3 V, V

DD_A

DD_A DD_A DD_A DD_A DD_A DD_A DD_A

= 3.4 V, V

= 3.4 V, V = 3.4 V, V = 3.4 V, V = 3.4 V, V = 3.4 V, V = 3.4 V, V = 3.4 V, V

DD_X

DD_X DD_X DD_X DD_X DD_X DD_X DD_X

DD_RF

= 3.4 V

= 3.4 V = 3.4 V = 3.4 V = 3.4 V = 3.4 V = 3.4 V = 3.4 V

Table 6-2. Supply Regulator Setting: 3-V System

(hex)

OPTION BITS SETTING IN REGULATOR CONTROL REGISTER

B7 B6 B5 B4 B3 B2 B1 B0

Automatic Mode (default)

0B 1 x x x x x 0 0 Automatic regulator setting 400-mV difference

Manual Mode

0B 0 x x x x 1 1 1 V 0B 0 x x x x 1 1 0 V 0B 0 x x x x 1 0 1 V 0B 0 x x x x 1 0 0 V 0B 0 x x x x 0 1 1 V 0B 0 x x x x 0 1 0 V 0B 0 x x x x 0 0 1 V 0B 0 x x x x 0 0 0 V

(1) x = Don't care

(1)

COMMENTS

DD_RF DD_RF DD_RF DD_RF DD_RF DD_RF DD_RF DD_RF

= 3.4 V, V = 3.3 V, V = 3.2 V, V = 3.1 V, V = 3.0 V, V = 2.9 V, V = 2.8 V, V = 2.7 V, V

DD_A DD_A DD_A DD_A DD_A DD_A DD_A DD_A

= 3.4 V, V = 3.3 V, V = 3.2 V, V = 3.1 V, V = 3.0 V, V = 2.9 V, V = 2.8 V, V = 2.7 V, V

The regulator configuration function adjusts the regulator outputs by default to 400 mV below VINlevel, but not higher than 5 V for V

, 3.4 V for V

DD_RF

DD_A

and V

. This ensures the highest possible supply

DD_X

voltage for the RF output stage while maintaining an adequate PSRR (power supply rejection ratio).

DD_X DD_X DD_X DD_X DD_X DD_X DD_X DD_X

= 3.4 V = 3.3 V = 3.2 V = 3.1 V = 3.0 V = 2.9 V = 2.8 V = 2.7 V

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6.3.3 Power Modes

The chip has several power states, which are controlled by two input pins (EN and EN2) and several bits in the chip status control register (0x00) (see Table 6-3 and Table 6-4).

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Table 6-3. 3.3-V Operation Power Modes

CHIP

(0x00)

REGULATOR

CONTROL

(0x0B)

TRANSMITTER RECEIVER

MODE EN2 EN

Power down 0 0 XX XX OFF OFF OFF OFF OFF <0.001 Sleep mode 1 0 XX XX OFF OFF OFF ON ON 0.120 Standby mode at +3.3 VDC X 1 80 00 OFF OFF ON X ON 2 Mode 1 at +3.3 VDC X 1 00 00 OFF OFF ON X ON 3 Mode 2 at +3.3 VDC X 1 02 00 OFF ON ON X ON 9 Mode 3 (half power) at

+3.3 VDC Mode 4 (full power) at

+3.3 VDC

X 1 30 07 ON ON ON X ON 53 14.5

X 1 20 07 ON ON ON X ON 67 17

STATUS CONTROL REGISTER

(1)

SYS_CLK

(13.56 MHz)

SYS_CLK

(60 kHz)

TYPICAL

CURRENT

DD_X

(mA)

TYPICAL

POWER

OUT (dBm)

(1) X = Don't care

Table 6-4. 5-V Operation Power Modes

CHIP

(0x00)

REGULATOR

CONTROL REGISTER

(0x0B)

TRANSMITTER RECEIVER

MODE EN2 EN

Power down 0 0 XX XX OFF OFF OFF OFF OFF <0.001 Sleep mode 1 0 XX XX OFF OFF OFF ON ON 0.120 Standby mode at +5 VDC X 1 81 07 OFF OFF ON X ON 3 Mode 1 at +5 VDC X 1 01 07 OFF OFF ON X ON 5 Mode 2 at +5 VDC X 1 03 07 OFF ON ON X ON 10.5 Mode 3 (half power) at

+5 VDC Mode 4 (full power) at

+5 VDC

X 1 31 07 ON ON ON X ON 70 20

X 1 21 07 ON ON ON X ON 130 23

STATUS CONTROL REGISTER

(1)

SYS_CLK

(13.56 MHz)

SYS_CLK

(60 kHz)

TYPICAL

CURRENT

DD_X

(mA)

TYPICAL

POWER

OUT (dBm)

(1) X = Don't care

Table 6-3 and Table 6-4 show the configuration for the different power modes when using a 3.3-V or 5-V

system supply, respectively. The main reader enable signal is pin EN. When EN is set high, all of the reader regulators are enabled, the 13.56-MHz oscillator is running and the SYS_CLK (output clock for external microcontroller) is also available.

The input pin EN2 has two functions:

• A direct connection from EN2 to VINto ensure the availability of the regulated supply V

DD_X

and an auxiliary clock signal (60 kHz, SYS_CLK) for an external MCU. This mode (EN = 0, EN2 = 1) is intended for systems in which the MCU is also being supplied by the reader supply regulator (V

DD_X

and the MCU clock is supplied by the SYS_CLK output of the reader. This allows the MCU supply and clock to be available during sleep mode.

• EN2 enables the start-up of the reader system from complete power down (EN = 0, EN2 = 0). In this case the EN input is being controlled by the MCU (or other system device) that is without supply voltage during complete power down (thus unable to control the EN input). A rising edge applied to the EN2 input (which has an approximately 1-V threshold level) starts the reader supply system and 13.56MHz oscillator (identical to condition EN = 1).

When user MCU is controlling EN and EN2, a delay of 1 ms between EN and EN2 must be used. If the MCU controls only EN, TI recommends connecting EN2 to either VINor GND, depending on the application MCU requirements for V

and SYS_CLK.

DD_X

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)

VIN

EN2

5 ms

6 ms

VIN

EN2

2 ms

5 ms

6 ms

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Figure 6-3. Nominal Start-up Sequence Using SPI With SS (MCU Controls EN2)

Figure 6-4. Nominal Start-up Sequence Using Parallel (MCU Controls EN2)

This start-up mode lasts until all of the regulators have settled and the 13.56-MHz oscillator has stabilized. If the EN input is set high (EN = 1) by the MCU (or other system device), the reader stays active. If the EN input is not set high (EN = 0) within 100 µs after the SYS_CLK output is switched from auxiliary clock (60 kHz) to high-frequency clock (derived from the crystal oscillator), the reader system returns to complete Power-Down Mode 1. This option can be used to wake-up the reader system from complete Power Down (PD Mode 1) by using a pushbutton switch or by sending a single pulse.

After the reader EN line is high, the other power modes are selected by control bits within the chip status control register (0x00). The power mode options and states are listed in Table 6-3.

When EN is set high (or on rising edge of EN2 and then confirmed by EN = 1) the supply regulators are activated and the 13.56-MHz oscillator is started. When the supplies are settled and the oscillator frequency is stable, the SYS_CLK output is switched from the auxiliary frequency of 60 kHz to the 13.56MHz frequency derived from the crystal oscillator. At this point, the reader is ready to communicate and perform the required tasks. When this occurs, osc_ok (B6) of the RSSI Level and Oscillator Status register is set. The MCU can then program the Chip Status Control register 0x00 and select the operation mode by programming the additional registers.

• Standby Mode (bit 7 = 1 of register 0x00), the reader is capable of recovering to full operation in 100 µs.

• Mode 1 (active mode with RF output disabled, bit 5 = 0 and bit 1 = 0 of register 0x00) is a low power mode which allows the reader to recover to full operation within 25 µs.

• Mode 2 (active mode with only the RF receiver active, bit 1 = 1 of register 0x00) can be used to measure the external RF field (as described in RSSI measurements paragraph) if reader-to-reader anticollision is implemented.

• Modes 3 and 4 (active modes with the entire RF section active, bit 5 = 1 of register 0x00) are the normal modes used for normal transmit and receive operations.

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6.4 Receiver – Analog Section

6.4.1 Main and Auxiliary Receivers

The TRF7964A has two receiver inputs: RX_IN1 (pin 8) and RX_IN2 (pin 9). Each of the input is connected to an external capacitive voltage divider to ensure that the modulated signal from the tag is available on at least one of the two inputs. This architecture eliminates any possible communication holes that may occur from the tag to the reader.

The two RX inputs (RX_IN1 and RX_IN2) are multiplexed into two receivers - the main receiver and the auxiliary receiver. Only the main receiver is used for reception, the auxiliary receiver is used for signal quality monitoring. Receiver input multiplexing is controlled by bit B3 in the Chip Status Control register (address 0x00).

After start-up, RX_IN1 is multiplexed to the main receiver which is composed of an RF envelope detection, first gain and band-pass filtering stage, second gain and filtering stage with AGC. Only the main receiver is connected to the digitizing stage which output is connected to the digital processing block. The main receiver also has an RSSI measuring stage, which measures the strength of the demodulated signal (subcarrier signal).

The primary function of the auxiliary receiver is to monitor the RX signal quality by measuring the RSSI of the demodulated subcarrier signal (internal RSSI). After start-up, RX_IN2 is multiplexed to the auxiliary receiver. The auxiliary receiver has an RF envelope detection stage, first gain and filtering with AGC stage and finally the auxiliary RSSI block.

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The default MUX setting is RX_IN1 connected to the main receiver and RX_IN2 connected to the auxiliary receiver. To determine the signal quality, the response from the tag is detected by the "main" (pin RX_IN1) and "auxiliary" (pin RX_IN2) RSSI. Both values measured and stored in the RSSI Levels and Oscillator Status register (address 0x0F). The MCU can read the RSSI values from the TRF7964A RSSI register and make the decision if swapping the input- signals is preferable or not. Setting B3 in Chip Status Control register (address 0x00) to 1 connects RX_IN1 (pin 8) to the auxiliary received and RX_IN2 (pin 9) to the main receiver.

The main and auxiliary receiver input stages are RF envelope detectors. The RF amplitude at RX_IN1 and RX_IN2 should be approximately 3 VPP for a VINsupply level greater than 3.3 V. If the VINlevel is lower, the RF input peak-to-peak voltage level should not exceed the VINlevel.

6.4.2 Receiver Gain and Filter Stages

The first gain and filtering stage has a nominal gain of 15 dB with an adjustable band-pass filter. The band-pass filter has programmable 3-dB corner frequencies between 110 kHz to 450 kHz for the highpass filter and 570 kHz to 1500 kHz for the low-pass filter. After the band-pass filter, there is another gainand-filtering stage with a nominal gain of 8 dB and with frequency characteristics identical to the first bandpass stage.

The internal filters are configured automatically depending on the selected ISO communication standard in the ISO Control register (address 0x01). If required, additional fine tuning can be done by writing directly to the RX Special Setting registers (address 0x0A).

Table 6-5 shows the various settings for the receiver analog section. Setting B4, B5, B6, and B7 to 0

results in a band-pass characteristic of 240 kHz to 1.4 MHz, which is appropriate for ISO/IEC 14443 B 106 kbps, ISO/IEC 14443 A and B data rates of 212 kbps and 424 kbps, and FeliCa 424 kbps.

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Table 6-5. RX Special Setting Register (0x0A)

Function: Sets the gains and filters directly Default: 0x40 at POR = H or EN = L, and at each write to the ISO Control register (0x01). When bits B7, B6, B5 and B4 are all zero, the

filters are set for ISO/IEC 14443 B (240 kHz to 1.4 MHz).

Bit Name Function Description

B7 C212 Band-pass 110 kHz to 570 kHz Appropriate for 212-kHz subcarrier system (FeliCa) B6 C424 Band-pass 200 kHz to 900 kHz Appropriate for 424-kHz subcarrier used in ISO/IEC 15693

B5 M848 Band-pass 450 kHz to 1.5 MHz

B4 hbt B3 gd1 00 = Gain reduction 0 dB

B2 gd2

B1 Reserved B0 Reserved

Band-pass 100 kHz to 1.5 MHz Gain reduced for 18 dB

01 = Gain reduction for 5 dB 10 = Gain reduction for 10 dB 11 = Gain reduction for 15 dB

Appropriate for Manchester-coded 848-kHz subcarrier used in ISO/IEC 14443 A and B

Appropriate for highest bit rate (848 kbps) used in high-bit-rate ISO/IEC 14443

Sets the RX gain reduction and reduces sensitivity

6.5 Receiver – Digital Section

The output of the TRF7964A analog receiver block is a digitized subcarrier signal and is the input to the digital receiver block, which consists of two sections that partly overlap. The digitized subcarrier signal is a digital representation of the modulation signal on the RF envelope. The two sections of the digital receiver block are the protocol bit decoder section and the framing logic section.

The protocol bit decoder section converts the subcarrier coded signal into a serial bit stream and a data clock. The decoder logic is designed for maximum error tolerance. This tolerance lets the decoder section successfully decode even partly corrupted subcarrier signals that would otherwise be lost due to noise or interference.

The framing logic section formats the serial bit stream data from the protocol bit decoder stage into data bytes. During the formatting process, special signals such as the start of frame (SOF), end of frame (EOF), start of communication, and end of communication are automatically removed. The parity bits and CRC bytes are also checked and removed. The end result is "clean or raw" data that is sent to the 127byte FIFO register where it can be read by the external microcontroller system. Providing the data this way, in conjunction with the timing register settings of the TRF7964A, means that the firmware developer does not need to know the finer details of the ISO protocols to create a very robust application, especially in low-cost platforms in which code space is at a premium and high performance is still required.

The start of the receive operation (successfully received SOF) sets the IRQ flags in the IRQ Status register (0x0C). The end of the receive operation is signaled to the external system MCU by setting pin 13 (IRQ) to high. When data is received in the FIFO, an interrupt is sent to the MCU to signal that there is data to be read from the FIFO. The FIFO Status register (0x1C) should be used to provide the number of bytes that should be clocked out during the actual FIFO read. Additionally, an interrupt is sent to the MCU when the received data occupies 75% of the FIFO capacity to signal that the data should be removed from the FIFO. By default, that interrupt is triggered once the received data packet is longer than 124 bytes. This setting can be modified in the Adjustable FIFO IRQ Levels register (0x14).

Any error in the data format, parity, or CRC is detected and notified to the external system by setting pin 13 (IRQ) to high. The source condition of the interrupt is available in the IRQ Status register (0x0C).

Section 6.14.3.3.1 describes the bit coding description of this register.

The framing section also supports bit-collision detection as specified in ISO/IEC 14443 A and ISO/IEC 15693. When a bit collision is detected, an interrupt request is sent and a flag is set in the IRQ Status register (0x0C). For ISO/IEC 14443 A specifically, the position of the bit collision is written in two registers: partly in the Collision Position register (0x0E) and partly in the Collision Position and Interrupt Mask register (0x0D) (bits B6 and B7).

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This collision position is presented as sequential bit number, where the count starts immediately after the start bit. This means a collision in the first bit of a UID would give the value 00 0001 0000 in these registers when their contents are combined after being read (the count starts with 0 and the first 16 bits are the command code and the number of valid bits [NVB] byte).

The receive section also contains two timers. The RX wait time timer is controlled by the value in the RX Wait Time register (0x08). This timer defines

the time interval after the end of the transmit operation during which the receive decoders are not active (held in reset state). This prevents false detections resulting from transients following the transmit operation. The value of the RX Wait Time register (0x08) defines the time in increments of 9.44 µs. This register is preset at every write to the ISO Control register (0x01) according to the minimum tag response time defined by each standard.

The RX no response timer is controlled by the RX No Response Wait Time register (0x07). This timer measures the time from the start of the slot in the anticollision sequence until the start of tag response. If there is no tag response in the defined time, an interrupt request is sent and a flag is set in the IRQ Status register (0x0C). This enables the external controller to be relieved of the task of detecting empty slots. The wait time is stored in the register in increments of 37.76 µs. This register is also preset automatically for every new protocol selection.

The main register controlling the digital part of the receiver is the ISO Control register (0x01). By writing to this register, the user selects the protocol to be used. With each new write in this register, all related registers are preset to their defaults for the protocol, so no further adjustments in other registers are needed for proper operation. Table 6-6 describes the bit fields of the ISO Control register (0x01).

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NOTE

If changes to other registers are needed to fine-tune the system, those changes must be made after setting the ISO Control register (0x01).

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Table 6-6. Coding of the ISO Control Register

BIT SIGNAL NAME FUNCTION COMMENTS

TRF7964A

B7 rx_crc_n Receiving without CRC

B6 dir_mode Direct mode type

B5 rfid RFID mode

B4 iso_4 RFID B3 iso_3 RFID B2 iso_2 RFID B1 iso_1 RFID B0 iso_0 RFID

1 = No RX CRC 0 = RX CRC

0 = Output is subcarrier data 1 = Output is bit stream and clock from decoder selected by ISO bits

0 = RFID reader mode 1 = Reserved (should be set to 0)

See Table 6-7 for B0:B4 settings based on ISO protocol used by application. See Table 6-7 for B0:B4 settings based on ISO protocol used by application. See Table 6-7 for B0:B4 settings based on ISO protocol used by application. See Table 6-7 for B0:B4 settings based on ISO protocol used by application. See Table 6-7 for B0:B4 settings based on ISO protocol used by application.

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Table 6-7. Coding of the ISO Control Register For RFID Mode (B5 = 0)

Iso_4 Iso_3 Iso_2 Iso_1 Iso_0 PROTOCOL REMARKS

0 0 0 0 0 ISO/IEC 15693 low bit rate, one subcarrier, 1 out of 4 0 0 0 0 1 ISO/IEC 15693 low bit rate, one subcarrier, 1 out of 256 0 0 0 1 0 ISO/IEC 15693 high bit rate, one subcarrier, 1 out of 4 Default for RFID IC 0 0 0 1 1 ISO/IEC 15693 high bit rate, one subcarrier, 1 out of 256 0 0 1 0 0 ISO/IEC 15693 low bit rate, double subcarrier, 1 out of 4 0 0 1 0 1 ISO/IEC 15693 low bit rate, double subcarrier, 1 out of 256 0 0 1 1 0 ISO/IEC 15693 high bit rate, double subcarrier, 1 out of 4 0 0 1 1 1 ISO/IEC 15693 high bit rate, double subcarrier, 1 out of 256 0 1 0 0 0 ISO/IEC 14443 A, bit rate 106 kbps

0 1 0 0 1 ISO/IEC 14443 A high bit rate 212 kbps

0 1 0 1 0 ISO/IEC 14443 A high bit rate 424 kbps 0 1 0 1 1 ISO/IEC 14443 A high bit rate 848 kbps 0 1 1 0 0 ISO/IEC 14443 B, bit rate 106 kbps

0 1 1 0 1 ISO/IEC 14443 B high bit rate 212 kbps

0 1 1 1 0 ISO/IEC 14443 B high bit rate 424 kbps 0 1 1 1 1 ISO/IEC 14443 B high bit rate 848 kbps 1 0 0 1 1 Reserved 1 0 1 0 0 Reserved 1 1 0 1 0 FeliCa 212 kbps 1 1 0 1 1 FeliCa 424 kbps

RX bit rate when TX rate different from RX rate (see register 0x03)

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0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 4.25

Input RF Carrier Level (V )

RSSI Levels and Oscillator Status Register Value (0x0F)

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6.5.1 Received Signal Strength Indicator (RSSI)

The TRF7964A incorporates in total three independent RSSI building blocks: Internal Main RSSI, Internal Auxiliary RSSI, and External RSSI. The internal RSSI blocks measure the amplitude of the subcarrier signal, and the external RSSI block measures the amplitude of the RF carrier signal at the receiver input.

6.5.1.1 Internal RSSI – Main and Auxiliary Receivers

Each receiver path has its own RSSI block to measure the envelope of the demodulated RF signal (subcarrier). Internal Main RSSI and Internal Auxiliary RSSI are identical however connected to different RF input pins. The Internal RSSI is intended for diagnostic purposes to set the correct RX path conditions.

The internal RSSI values can be used to adjust the RX gain settings or determine which RX path (main or auxiliary) provides the greater amplitude and, hence, to determine if the MUX may need to be reprogrammed to swap the RX input signal. The measuring system latches the peak value, so the RSSI level can be read after the end of each receive packet. The RSSI register values are reset with every transmission (TX) by the reader. This ensures an updated RSSI measurement for each new tag response.

The Internal RSSI has 7 steps (3 bit) with a typical increment of approximately 4 dB. The operating range is between 600 mVPPand 4.2 VPPwith a typical step size of approximately 600 mV. Both Internal Main and Internal Auxiliary RSSI values are stored in the RSSI Levels and Oscillator Status register (0x0F). The nominal relationship between the input RF peak level and the RSSI value is shown in Figure 6-5.

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Figure 6-5. Digital Internal RSSI (Main and Auxiliary) Value vs RF Input Level in VPP(V)

This RSSI measurement is done during the communication to the Tag; this means the TX must be on. Bit 1 in the Chip Status Control register (0x00) defines if Internal RSSI or the External RSSI value is stored in the RSSI Levels and Oscillator Status register (0x0F). Direct command 0x18 is used to trigger an Internal RSSI measurement.

6.5.1.2 External RSSI

The external RSSI is mainly used to check for any external 13.56-MHz signals at the receiver RX_IN1 input. The external RSSI measurement should be used before turning on the transmitter to prevent RF field collisions. This is especially important for active mode, when both devices emit their own RF field. The level of the RF signal received at the antenna is measured and stored in the RSSI Levels and Oscillator Status register (0x0F). Figure 6-6 shows the relationship between the voltage at the RX_IN1 input and the 3-bit code.

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0 25 50 75 100 125 150 175 200 225 250 275 300 325

RF Input Voltage Level at RF_IN1 (mV )

RSSI Levels and Oscillator Status Register Value (0x0F)

TRF7964A

SLOS787J –MAY 2012–REVISED MARCH 2020

Figure 6-6. Digital External RSSI Value vs RF Input Level in VPP(mV)

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The relation between the 3-bit code and the external RF field strength (A/m) sensed by the antenna must be determined by calculation or by experiments for each antenna design. The antenna Q-factor and connection to the RF input influence the result. Direct command 0x19 is used to trigger an external RSSI measurement.

For clarity, to check the internal or external RSSI value independent of any other operation, the user must:

1. Set transmitter to desired state (on or off) using Bit 5 of Chip Status Control register (0x00) and enable receiver using Bit 1.

2. Check internal or external RSSI using direct commands 0x18 or 0x19, respectively. This action places the RSSI value in the RSSI register.

3. Delay at least 50 µs.

4. Read the RSSI register using direct command 0x0F; values range from 0x40 to 0x7F.

5. Repeat steps 1 to 4 as needed. The register is reset when it is read.

6.6 Oscillator Section

The 13.56-MHz or 27.12-MHz crystal (or oscillator) is controlled by the Chip Status Control register (0x00) and the EN and EN2 terminals. The oscillator generates the RF frequency for the RF output stage as well as the clock source for the digital section. The buffered clock signal is available at pin 27 (SYS_CLK) for any other external circuits. B4 and B5 inside the Modulation and SYS_CLK register (0x09) can be used to divide the external SYS_CLK signal at pin 27 by 1, 2, or 4.

Typical start-up time from complete power down is in the range of 3.5 ms. During Power Down Mode 2 (EN = 0, EN2 = 1) the frequency of SYS_CLK is switched to 60 kHz (typical). The crystal needs to be connected between pin 30 and pin 31. The external shunt capacitors values for C

and C2must be calculated based on the specified load capacitance of the crystal being used. The external shunt capacitors are calculated as two identical capacitors in series plus the stray capacitance of the TRF7964A and parasitic PCB capacitance in parallel to the crystal.

The parasitic capacitance (CS, stray and parasitic PCB capacitance) can be estimated at 4 to 5 pF (typical).

As an example, using a crystal with a required load capacitance (CL) of 18 pF, the calculation is shown in

Equation 1.

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Crystal

Pin 31Pin 30

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C1= C2= 2 × (CL– CS) = 2 × (18 pF – 4.5 pF) = 27 pF (1)

A 27-pF capacitor must be placed on pins 30 and 31 to ensure proper crystal oscillator operation.

Any crystal used with TRF7964A should meet the minimum characteristics in Table 6-8.

TRF7964A

SLOS787J –MAY 2012–REVISED MARCH 2020

Figure 6-7. Crystal Block Diagram

Table 6-8. Minimum Crystal Recommendations

PARAMETER SPECIFICATION

Frequency 13.56 MHz or 27.12 MHz

Mode of operation Fundamental

Type of resonance Parallel

Frequency tolerance ±20 ppm

Aging < 5 ppm/year

Operation temperature range –40°C to 85°C

As an alternative, an external clock oscillator source can be connected to pin 31 to provide the system clock; pin 30 can be left open.

6.7 Transmitter – Analog Section

The 13.56-MHz oscillator generates the RF signal for the PA stage. The power amplifier consists of a driver with selectable output resistance of nominal 4 Ω or 8 Ω. The transmit power level is set by bit B4 in the Chip Status Control register (0x00). The transmit power levels are selectable between 100 mW (half power) or 200 mW (full power) when configured for 5-V automatic operation. The transmit power levels are selectable between 33 mW (half power) or 70 mW (full power) when configured for 3-V automatic operation.

The ASK modulation depth is controlled by bits B0, B1, and B2 in the Modulator and SYS_CLK Control register (0x09). The ASK modulation depth range can be adjusted between 7% to 30% or 100% (OOK).

External control of the transmit modulation depth is possible by setting the ISO Control register (0x01) to direct mode. While operating the TRF7964A in direct mode, the transmit modulation is made possible by selecting the modulation type ASK or OOK at pin 12. External control of the modulation type is made possible only if enabled by setting B6 in the Modulator and SYS_CLK Control register (0x09) to 1.

In normal operation mode, the length of the modulation pulse is defined by the protocol selected in the ISO Control register (0x01). With a high-Q antenna, the modulation pulse is typically prolonged, and the tag detects a longer pulse than intended. For such cases, the modulation pulse length needs to be corrected by using the TX Pulse Length Control register (0x06).

If the register contains all zeros, then the pulse length is governed by the protocol selection. If the register contains a value other than 0x00, the pulse length is equal to the value of the register multiplied by

73.7 ns; therefore, the pulse length can be adjusted between 73.7 ns and 18.8 µs in 73.7-ns increments.

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Texas Instruments TRF7964A Datasheet

1 Device Overview

1.1 Features

1.2 Applications

1.3 Description

1.4 Functional Block Diagram

Table of Contents

2 Revision History

3 Device Characteristics

3.1 Related Products

4 Terminal Configuration and Functions

4.1 Pin Diagram

4.2 Signal Descriptions

5 Specifications

5.1 Absolute Maximum Ratings

5.2 ESD Ratings

5.3 Recommended Operating Conditions

5.4 Electrical Characteristics

5.5 Thermal Resistance Characteristics

5.6 Switching Characteristics

6 Detailed Description

6.1 Overview

6.1.1 RFID – Reader and Writer

6.2 System Block Diagram

6.3 Power Supplies

6.3.1 Supply Arrangements

6.3.2 Supply Regulator Settings

6.3.3 Power Modes

6.4 Receiver – Analog Section

6.4.1 Main and Auxiliary Receivers

6.4.2 Receiver Gain and Filter Stages

6.5 Receiver – Digital Section

6.5.1 Received Signal Strength Indicator (RSSI)

6.5.1.1 Internal RSSI – Main and Auxiliary Receivers

6.5.1.2 External RSSI

6.6 Oscillator Section

6.7 Transmitter – Analog Section