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TRF7960, TRF7961 Multiple-Standard Fully Integrated 13.56-MHz RFID

Analog Front End and Data-Framing Reader System

1 Device Overview

1.1 Features

• Completely Integrated Protocol Handling

• Separate Internal High-PSRR Power Supplies for Analog, Digital, and PA Sections Provide Noise Isolation for Superior Read Range and Reliability

• Dual Receiver Inputs With AM and PM Demodulation to Minimize Communication Holes

• Receiver AM and PM RSSI

• Reader-to-Reader Anticollision

• High Integration Reduces Total BOM and Board Area

– Single External 13.56-MHz Crystal Oscillator – MCU-Selectable Clock-Frequency Output of RF,

RF/2, or RF/4

– Adjustable 20-mA High-PSRR LDO for

Powering External MCU

• Easy to Use With High Flexibility – Automatically Configured Default Modes for

Each Supported ISO Protocol

– 12 User-Programmable Registers

TRF7960, TRF7961

SLOU186G –AUGUST 2006–REVISED MAY 2017

– Selectable Receiver Gain – Programmable Output Power (100 mW or

200 mW) – Adjustable ASK Modulation Range (8% to 30%) – Built-In Receiver Band-Pass Filter With User-

Selectable Corner Frequencies

• Wide Operating Voltage Range of 2.7 V to 5.5 V

• Ultra-Low-Power Modes – Power Down: <1 µA – Standby: 120 µA – Active (RX Only): 10 mA

• Parallel 8-Bit or Serial 4-Pin Serial Peripheral Interface (SPI) With MCU Using 12-Byte FIFO

• Ultra-Small 32-Pin QFN Package (5 mm × 5 mm)

• Available Tools (Also See Tools and Software) – Reference Design and EVM With Development

Software

– Source Code Available for MSP430™ MCU

1.2 Applications

• Secure Access Control

• Product Authentication

1.3 Description

The TRF7960 and TRF7961 devices are integrated analog front end and data-framing systems for a

13.56-MHz RFID reader system that supports multiple protocols including ISO/IEC 14443 A and B, FeliCa™, and ISO/IEC 15693. Built-in programming options make it suitable for a wide range of applications for proximity and vicinity identification systems.

The reader is configured by selecting the desired protocol in the control registers. Direct access to all control registers allows fine-tuning of various reader parameters as needed.

The device supports data rates up to 848 kbps with all framing and synchronization tasks for the ISO protocols onboard. Other standards and even custom protocols can be implemented by using one of the direct modes that the device offers. These direct modes let the application fully control the AFE and also gain access to the raw subcarrier data or the unframed, but already ISO-formatted, data and the associated (extracted) clock signal.

The receiver system has a dual-input receiver architecture to maximize communication robustness. The receivers also include various automatic and manual gain control options. The received signal strength from transponders, ambient sources, or internal levels is available in the RSSI register.

A SPI or parallel interface can be used for the communication between the MCU and the TRF796x reader. When the built-in hardware encoders and decoders are used, transmit and receive functions use a 12-byte FIFO register. For direct transmit or receive functions, the encoders or decoders can be bypassed so the MCU can process the data in real time.

• Medical Systems

• Public Transport or Event Ticketing

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

3 (SPI) or 8 (Parallel)

Impedance

Matching

Circuit

TX_OUT

RX_IN1

RX_IN2

VDD_X

VDD_I/O

SYS_CLK

DATA_CLK

VCC

TRF796x

MSP430 MCU

Crystal

13.56 MHz

IRQ

OSC_IN

OSC_OUT

TRF7960, TRF7961

SLOU186G –AUGUST 2006–REVISED MAY 2017

The TRF7960 and TRF7961 devices support a wide supply voltage range of 2.7 V to 5.5 V and data communication levels from 1.8 V to 5.5 V for the MCU I/O interface.

The transmitter has selectable output power levels of 100 mW (+20 dBm) or 200 mW (+23 dBm) equivalent into a 50-Ω load when using a 5-V supply and supports OOK and ASK modulation with selectable modulation depth.

Built-in programmable auxiliary voltage regulator delivers up to 20 mA to supply an MCU and additional external circuits within the reader system.

Start evaluating the TRF7960 multiprotocol transceiver IC with the TRF7960AEVM or the TRF7960ATB.

Documentation, Tools, Reference Designs, and Software, Samples

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(1) For more information, see Section 9, Mechanical, Packaging, and

1.4 Typical Application

Figure 1-1 shows a typical application block diagram.

Device Information

PART NUMBER PACKAGE BODY SIZE

TRF7960RHB VQFN (32) 5 mm × 5 mm TRF7961RHB VQFN (32) 5 mm × 5 mm

Orderable Information.

(1)

Figure 1-1. Application Block Diagram

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1 Device Overview ......................................... 1

1.1 Features .............................................. 1

1.2 Applications........................................... 1

1.3 Description............................................ 1

1.4 Typical Application ................................... 2

2 Revision History ......................................... 4

3 Device Comparison ..................................... 5

3.1 Related Products ..................................... 5

4 Terminal Configuration and Functions.............. 6

4.1 Pin Diagram .......................................... 6

4.2 Signal Descriptions ................................... 6

5 Specifications ............................................ 8

5.1 Absolute Maximum Ratings .......................... 8

5.2 ESD Ratings.......................................... 8

5.3 Recommended Operating Conditions ................ 8

5.4 Electrical Characteristics ............................. 8

5.5 Thermal Resistance Characteristics.................. 9

6 Detailed Description ................................... 10

6.1 Overview ............................................ 10

6.2 Power Supplies...................................... 10

6.3 Receiver – Analog Section.......................... 16

6.4 Register Descriptions................................ 22

6.5 Direct Commands From MCU to Reader ........... 31

6.6 Reader Communication Interface................... 33

6.7 Parallel Interface Communication................... 34

6.8 Serial Interface Communication..................... 36

7 Applications, Implementation, and Layout........ 41

7.1 Application Schematics ............................. 41

8 Device and Documentation Support ............... 43

8.1 Getting Started and Next Steps..................... 43

8.2 Device Nomenclature ............................... 43

8.3 Tools and Software ................................. 44

8.4 Documentation Support ............................. 44

8.5 Related Links........................................ 45

8.6 Community Resources .............................. 45

8.7 Trademarks.......................................... 45

8.8 Electrostatic Discharge Caution..................... 45

8.9 Export Control Notice ............................... 45

8.10 Glossary............................................. 45

9 Mechanical, Packaging, and Orderable

Information .............................................. 46

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2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from August 12, 2010 to May 18, 2017 Page

• Removed "and AGC" from "Selectable Receiver Gain" in Section 1.1, Features ........................................... 1

• Updated list of applications.......................................................................................................... 1

• Changed contents of Section 1.3, Description.................................................................................... 1

• Added Device Information table .................................................................................................... 2

• Added Section 1.4, Typical Application............................................................................................ 2

• Added Section 3, Device Comparison, and moved Table 3-1 to it............................................................. 5

• Added Section 3.1, Related Products ............................................................................................. 5

• Changed the title of Section 4 from Physical Characteristics to Terminal Configuration and Functions.................. 6

• Removed former Section 3.2, Packaging and Ordering Information (see Section 9, Mechanical, Packaging, and

Orderable Information) ............................................................................................................... 7

• Updated note (1) on Section 5.1, Absolute Maximum Ratings, to standard wording........................................ 8

• Moved ESD ratings from Absolute Maximum Ratings to Section 5.2, ESD Ratings; changed ratings from positive

voltages only to positive and negative; added notes for HBM and CDM...................................................... 8

• Changed format of MIN, TYP, and MAX columns in Section 5.4, Electrical Characteristics ............................... 8

• Added the f

D_CLKmax

• Changed title of and moved Section 5.5, Thermal Resistance Characteristics .............................................. 9

• Moved contents of Section 6.1, Overview from former Section 2............................................................. 10

• Removed a paragraph that began "The second receiver gain stage and digitizer stage..." in Section 6.3,

Receiver – Analog Section......................................................................................................... 17

• Added the last sentence to the paragraph that begins "The start of the receive operation (successfully received

SOF)..." in Section 6.3.2, Receiver – Digital Section .......................................................................... 18

• Added "and ISO/IEC 15693" to the first sentence of the paragraph that begins "The framing section also

supports bit-collision detection..." in Section 6.3.2, Receiver – Digital Section ............................................. 18

• Changed B2 to Reserved in Table 6-11, Chip Status Control Register (Address = 00h) ................................. 23

• Changed B1 and B0 to Reserved in Table 6-22, RX Special Setting Register (Address = 0Ah) ........................ 28

• Corrected the name of the Reset FIFO command in Table 6-31, Command Codes, and Section 6.5.2, Reset FIFO 31

• Added the last sentence to the paragraph that begins "The serial communications work in the same manner..."

in Section 6.8, Serial Interface Communication................................................................................. 36

• Removed former section External Power Amplifier Application............................................................... 40

• Added Section 7, Applications, Implementation, and Layout, and moved the application schematics to it ............. 41

• Added Section 8, Device and Documentation Support......................................................................... 43

• Added Section 9, Mechanical, Packaging, and Orderable Information ...................................................... 46

parameter in Section 5.4, Electrical Characteristics ..................................................... 9

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3 Device Comparison

Table 3-1 summarizes the device characteristics.

Table 3-1. Device Comparison

PROTOCOLS

DEVICE

106 kbps 212 kbps 424 kbps 848 kbps

TRF7960 ✓ ✓ ✓ ✓ ✓ ✓ TRF7961 ✓ ✓

3.1 Related Products

For information about other devices in this family of products or related products, see the following links.

Products for TI Wireless Connectivity Connect more with the broadest wireless connectivity portfolio in

the industry.

Products for NFC / RFID TI provides one of the most differentiated NFC and RFID product portfolios in

the industry and is your solution to meet a broad range of NFC connectivity and RFID identification needs.

Companion Products for TRF7960 Review products that are frequently purchased or used with this

product.

Reference Designs for TRF7960 The TI Designs Reference Design Library is a robust reference design

library that spans analog, embedded processor, and connectivity. Created by TI experts to help you jump start your system design, all TI Designs include schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download designs at

ti.com/tidesigns.

ISO/IEC 14443 A AND B

ISO/IEC 15693,

ISO/IEC 18000-3

Tag-it™

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Exposed Thermal Pad

VDD_A

RX_IN1

VSS_RX

VSS_RF

TX_OUT

VDD_PA

VDD_RF

VIN

I/O_7

I/O_0

I/O_1

I/O_2

I/O_3

I/O_4

I/O_5

I/O_6

RX_IN2

VDD_I/O

VSS_A

MOD

IRQ

ASK/OOK

VSS

VDD_X

EN2

DATA_CLK

SYS_CLK

VSS_D

OSC_OUT

OSC_IN

32 31 30 29 28 27 26 25

10 11 12 13 14 15 16

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4 Terminal Configuration and Functions

4.1 Pin Diagram

Figure 4-1 shows the pinout of the 32-pin RHB package.

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Figure 4-1. 32-Pin RHB Package (Top View)

4.2 Signal Descriptions

Table 4-1 describes the device signals.

Table 4-1. Signal Descriptions

TERMINAL

NAME NO.

VDD_A 1 OUT Internal regulated supply (2.7 V to 3.4 V) for analog circuitry VIN 2 SUP External supply input to chip (2.7 V to 5.5 V) VDD_RF 3 OUT Internal regulated supply (2.7 V to 5 V), normally connected to VDD_PA (pin 4) VDD_PA 4 INP Supply for PA; normally connected externally to VDD_RF (pin 3) TX_OUT 5 OUT RF output (selectable output power, 100 mW at 8 Ω or 200 mW at 4 Ω, with VDD= 5 V) VSS_RF 6 SUP Negative supply for PA; normally connected to circuit ground VSS_RX 7 SUP Negative supply for RX inputs; normally connected to circuit ground RX_IN1 8 INP RX input, used for AM reception RX_IN2 9 INP RX input, used for PM reception VSS 10 SUP Chip substrate ground BAND_GAP 11 OUT Band-gap voltage (1.6 V); internal analog voltage reference; must be AC-bypassed to ground

ASK/OOK 12 BID

IRQ 13 OUT Interrupt request

(1)

TYPE

DESCRIPTION

Also can be configured to provide the received analog signal output (ANA_OUT) Direct mode, selects either ASK or OOK modulation (0 = ASK, 1 = OOK)

(1) SUP = Supply, INP = Input, BID = Bidirectional, OUT = Output 6

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Table 4-1. Signal Descriptions (continued)

TERMINAL

NAME NO.

MOD 14 INP Direct mode, external modulation input VSS_A 15 SUP Negative supply for internal analog circuits; normally connected to circuit ground

VDD_I/O 16 SUP I/O_0 17 BID I/O pin for parallel communication

I/O_1 18 BID I/O pin for parallel communication I/O_2 19 BID I/O pin for parallel communication I/O_3 20 BID I/O pin for parallel communication I/O_4 21 BID I/O pin for parallel communication

I/O_5 22 BID

I/O_6 23 BID

I/O_7 24 BID

EN2 25 INP

DATA_CLK 26 INP Clock input for MCU communication (parallel and serial)

SYS_CLK 27 OUT

EN 28 INP Chip enable input (If EN = 0, then chip is in power-down mode.) VSS_D 29 SUP Negative supply for internal digital circuits; normally connected to circuit ground OSC_OUT 30 OUT Crystal oscillator output OSC_IN 31 INP Crystal oscillator input VDD_X 32 OUT Internally regulated supply (2.7 V to 3.4 V) for external circuitry (MCU) Thermal Pad Connected to circuit ground

TYPE

(1)

Supply for I/O communications (1.8 V to 5.5 V). Should be connected to VIN for 5-V communication, VDD_X for 3.3-V communication, or any other voltage from 1.8 V to 5.5 V.

I/O pin for parallel communication Strobe out clock for serial communication Data clock output in direct mode I/O pin for parallel communication MISO for serial communication (SPI) Serial bit data output in direct mode 1 or subcarrier signal in direct mode 0 I/O pin for parallel communication. MOSI for serial communication (SPI) Pulse enable and selection of power-down mode. If EN2 is connected to VIN, then VDD_X is

active during power down to support the MCU. Pin can also be used for pulse wake up from power-down mode.

Clock for MCU (3.39 / 6.78 / 13.56 MHz) at EN = 1 and EN2 = don't care If EN = 0 and EN2 = 1, then system clock is set to 60 kHz

DESCRIPTION

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5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

VINSupply voltage 6 V I

Output current 150 mA

Maximum junction temperature

Storage temperature range –55 150 °C

stg

Any condition 140 Continuous operation, long-term reliability

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may

result in reduced reliability or lifetime of the device.

5.2 ESD Ratings

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001

Electrostatic discharge

(ESD)

Machine model (MM) ±200

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as

±2000 V may actually have higher performance.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±500 V

may actually have higher performance.

(1)

MIN MAX UNIT

(2)

125

°C

VALUE UNIT

(1)

(2)

±2000

±500

VCharged-device model (CDM), per JEDEC specification JESD22-C101

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN TYP MAX UNIT

VINSupply voltage 2.7 5 5.5 V T

Operating virtual junction temperature –40 125 °C

Operating ambient temperature –40 25 110 °C

5.4 Electrical Characteristics

TYP values at 25°C, MIN and MAX values over operating ambient temperature range, VS= 5 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

PD2

STBY

ON1

ON2

ON3

Supply current in power-down mode

Supply current in power-down mode 2

Supply current in standby mode Supply current without antenna

driver current Supply current with antenna

driver current BG Band-gap voltage Internal analog reference voltage 1.4 1.6 1.7 V V

POR

DD_A

Power-on-reset (POR) voltage 1.4 2 2.5 V

Regulated supply for analog

circuitry

All systems disabled, including supply voltage regulators

The reference voltage generator and VDD_X remain active to support external circuitry.

Oscillator running, supply voltage regulators in low-consumption mode

Oscillator, regulators, RX, and AGC are active, TX is off

Oscillator, regulators, RX, AGC, and TX are active, P

= 100 mW

out

Oscillator, regulators, RX, AGC, and TX are all active, P

= 200 mW

out

1 10 µA

120 300 µA

1.5 4 mA

10 16 mA

70 mA

120 mA

3.1 3.5 3.8 V

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Electrical Characteristics (continued)

TYP values at 25°C, MIN and MAX values over operating ambient temperature range, VS= 5 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DD_RF

DD_X

PSRR

RFOUT

RFIN

SENS

SET_PD

SET_STBY

REC

SYS_CLK

D_CLKmax

CLK

MAX

OUT

SYS_CLK

Regulated supply for RF circuitry

Regulated supply for external

circuitry

Rejection of external supply noise

on the supply VDD_RF regulator

PA driver output resistance

RX_IN1 and RX_IN2 input

resistance

Maximum input voltage At RX_IN1 and RX_IN2 inputs 3.5 V

Input sensitivity

Setup time after power down 10 20 ms

Setup time after standby mode 30 100 µs

Recovery time after modulation

(ISO/IEC 14443)

SYS_CLK frequency In PD2 mode EN = 0 and EN2 = 1 30 60 120 kHz

Maximum DATA_CLK frequency

Maximum CLK frequency 2 MHz

Input logic low

Input logic high

Output resistance of I/O_0 to

I/O_7

Output resistance of SYS_CLK low_io = H for V

(1) Recommended DATA_CLK speed is 2 MHz; higher data clock depends on the capacitive load. Maximum SPI clock speed should not

exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. The MISO driver has a typical output resistance of 400 Ω (12-ns time constant when 30-pF load is used).

Regulator set for 5-V system with 250-mV difference

4 4.6 5.2 V

3.1 3.4 3.8 V

The difference between the external supply and the regulated voltage is higher than 250 mV,

20 26 dB

measured at 212 kHz Half-power mode 8 12 Full-power mode 4 6

5 10 20 kΩ

SUBCARRIER

= 424 kHz 1.2 2.5 = 848 kHz 1.2 3

Modulation signal: sine, 424 kHz, 10 mVpp 60 µs

Depends on capacitive load on the I/O lines, TI recommends 2 MHz

(1)

2 4 8 MHz

DD_I/O

0.2 × V

DD_I/O

0.2 ×

0.8 ×

DD_I/O

low_io = H for V

< 2.7 V 400 800 Ω

DD_I/O

< 2.7 V 200 400 Ω

DD_I/O

Ω

5.5 Thermal Resistance Characteristics

PACKAGE

Rθ

(°C/W)

Rθ

(°C/W)

(1)

TA≤ 25°C TA= 85°C

POWER RATING

RHB (32) 31 36.4 2.7 W 1.1 W

(1) This data was taken using the JEDEC standard high-K test PCB. (2) Power rating is determined with a junction temperature of 125°C. This is the temperature at which distortion starts to increase

substantially. Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long-term reliability.

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(2)

3 (SPI) or 8 (Parallel)

Impedance

Matching

Circuit

TX_OUT

RX_IN1

RX_IN2

VDD_X

VDD_I/O

SYS_CLK

DATA_CLK

VCC

TRF796x

MSP430 MCU

Crystal

13.56 MHz

IRQ

OSC_IN

OSC_OUT

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6 Detailed Description

6.1 Overview

Figure 6-1 shows a typical application diagram for the TRF796x devices. A parallel or serial interface can

be implemented for communication between the MCU and reader. Transmit and receive functions use internal encoders and decoders with a 12-byte FIFO register. For direct transmit or receive functions, the encoders and decoders can be bypassed so the MCU can process the data in real time. The transmitter has selectable output power levels of 100 mW (20 dBm) or 200 mW (23 dBm) into a 50-Ω load (5-V supply) and supports ASK or OOK modulation. Integrated voltage regulators ensure power-supply noise rejection for the complete reader system.

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Data transmission supports low-level encoding for ISO/IEC 15693, modified Miller for ISO/IEC 14443 A, high-bit-rate systems for ISO/IEC 14443, and Tag-it coding systems. Included with the data encoding is automatic generation of SOF, EOF, CRC, and parity bits.

The receiver system enables AM and PM demodulation using a dual-input architecture. The receiver also includes an automatic gain control option and selectable gain. Also included is a selectable bandwidth to cover a broad range of input subcarrier signal options. The received signal strength for AM and PM modulation is accessible through the RSSI register. The receiver output is a digitized subcarrier signal among a selectable protocol and bit rate as outlined in Table 6-13. A selected decoder delivers bit stream and a data clock as outputs.

The receiver system also includes a framing system. This system performs a CRC or parity check, removes the EOF and SOF settings, and organizes the data in bytes. Framed data is then accessible to the MCU through a 12-byte FIFO register and MCU interface. The framing supports ISO/IEC 14443 and ISO/IEC 15693 protocols.

The TRF796x supports data communication levels from 1.8 V to 5.5 V for the MCU I/O interface, while also providing a data synchronization clock. An auxiliary 20-mA regulator (pin 32) is available for additional system circuits.

6.2 Power Supplies

The positive supply pin, VIN (pin 2), has an input voltage range of 2.7 V to 5.5 V. The positive supply input sources three internal regulators with output voltages V capacitors for supply noise filtering. These regulators provide enhanced PSRR for the RFID reader system. Table 6-1 describes the power supplies.

Figure 6-1. Typical Application Diagram

DD_RF

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, V

DD_A

, and V

that use external bypass

DD_X

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The regulators are not independent and have common control bits for output voltage setting. The regulators can be configured to operate in either automatic or manual mode. The automatic regulator mode setting ensures an optimal compromise between regulator PSRR and highest possible supply voltage for RF output power. The manual mode allows the application to manually configure the regulator settings.

Table 6-1. Power Supplies

SUPPLY DESCRIPTION

DD_RF

DD_PA

DD_A

DD_X

The regulator V operation.

When configured for 5-V operation, the output voltage can be set from 4.3 V to 5 V in 100-mV steps. The current sourcing capability for 5-V operation is 150 mA maximum over the adjusted output voltage range.

When configured for 3-V operation, the output voltage can be set from 2.7 V to 3.4 V, also in 100-mV steps. The current sourcing capability for 3-V operation is 100 mA maximum over the adjusted output voltage range.

Regulator V When configured for 5-V operation, the output voltage is fixed at 3.5 V. When configured for 3-V operation, the output voltage can be set from 2.7 V to 3.4 V in 100-mV steps.

NOTE: The V Regulator V

components. When configured for 5-V operation, the output voltage is fixed at 3.4 V. When configured for 3-V operation, the output voltage can be set from 2.7 to 3.4 V in 100-mV steps.

The total current sourcing capability of the V NOTE: The V

The V V

DD_RF

DD_A

DD_X

pin (pin 4) is the positive supply pin for the RF output stage and is externally connected to the regulator output

DD_PA

(pin 3).

(pin 3) is used to source the RF output stage. The voltage regulator can be set for either 5-V or 3-V

DD_RF

(pin 1) supplies voltage to analog circuits within the reader chip. The voltage setting is divided in two ranges.

and V

DD_A

(pin 32) can be used to source the digital I/O of the reader chip together with other external system

and V

DD_A

regulators are configured together (their settings are not independent).

DD_X

regulator is 20 mA (maximum) over the adjusted output range.

DD_X

regulators are configured together (their settings are not independent).

DD_X

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SLOU186G –AUGUST 2006–REVISED MAY 2017

6.2.1 Negative Supply Connections

The negative supply connections are all externally connected together (to GND). The substrate connection is VSS(pin 10), the analog negative supply is V the RF output stage negative supply is V V

SS_RX

(pin 7).

6.2.2 Digital I/O Interface

To allow compatible I/O signal levels, the TRF796x has a separate supply input V input voltage range of 1.8 V to 5.5 V. This pin supplies the I/O interface (I/O_0 to I/O_7), IRQ, SYS_CLK, and DATA_CLK pins of the reader. In typical applications, V that the I/O signal levels of the MCU are the same as the internal logic levels of the reader.

6.2.3 Supply Regulator Configuration

The supply regulators can be automatically or manually configured by the control bits. Table 6-2 lists the manual regulator settings for a 5-V system. Table 6-3 lists the manual regulator settings for a 3-V system.

Table 6-4 and Table 6-5 list the automatic mode gain settings for 5-V and 3-V systems, respectively.

The automatic mode is the default configuration. In automatic mode, the regulators are automatically set every time the system is activated by asserting the EN input high. The internal regulators are also automatically reconfigured every time the automatic regulator selection bit is set high (on the rising edge).

(pin 15), the logic negative supply is V

SS_A

(pin 6), and the negative supply for the RF receiver input is

SS_TX

DD_I/O

is connected directly to V

DD_I/O

SS_D

(pin 16), with an

DD_X

(pin 29),

to ensure

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The application can reset the automatic mode setting from a state in which the automatic setting bit is already high by changing the automatic setting bit from high to low to high. The regulator-configuration algorithm adjusts the regulator outputs 250 mV below the VINlevel, but not higher than 5 V for V V for V

, and 3.4 V for V

DD_A

output stage while maintaining an adequate PSRR (power supply rejection ratio). As an example, the application can improve the PSRR if there is a noisy supply voltage from V voltage difference across the V

Table 6-5.

Table 6-2. Supply-Regulator Setting – Manual – 5-V System

. This algorithm ensures the highest possible supply voltage for the RF

DD_X

by increasing the target

DD_X

regulator as listed for automatic regulator settings in Table 6-4 and

DD_X

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, 3.5

DD_RF

BYTE

ADDRESS

OPTION BITS SETTING IN CONTROL REGISTER

B7 B6 B5 B4 B3 B2 B1 B0

0x00 1 5-V system 0x0B 0 Manual regulator setting 0x0B 0 1 1 1 V 0x0B 0 1 1 0 V 0x0B 0 1 0 1 V 0x0B 0 1 0 0 V 0x0B 0 0 1 1 V 0x0B 0 0 1 0 V 0x0B 0 0 0 1 V 0x0B 0 0 0 0 V

DD_RF DD_RF DD_RF DD_RF DD_RF DD_RF DD_RF DD_RF

= 5 V, V = 4.9 V, V = 4.8 V, V = 4.7 V, V = 4.6 V, V = 4.5 V, V = 4.4 V, V = 4.3 V, V

Table 6-3. Supply-Regulator Setting – Manual – 3-V System

BYTE

ADDRESS

0x00 0 3-V system 0x0B 0 Manual regulator setting 0x0B 0 1 1 1 V 0x0B 0 1 1 0 V 0x0B 0 1 0 1 V 0x0B 0 1 0 0 V 0x0B 0 0 1 1 V 0x0B 0 0 1 0 V 0x0B 0 0 0 1 V 0x0B 0 0 0 0 V

OPTION BITS SETTING IN CONTROL REGISTER

B7 B6 B5 B4 B3 B2 B1 B0

DD_RF DD_RF DD_RF DD_RF DD_RF DD_RF DD_RF DD_RF

= 3.4 V, V = 3.3 V, V = 3.2 V, V = 3.1 V, V = 3.0 V, V = 2.9 V, V = 2.8 V, V = 2.7 V, V

DD_A

DD_A DD_A DD_A DD_A DD_A DD_A DD_A

DD_A DD_A DD_A DD_A DD_A DD_A DD_A DD_A

ACTION

= 3.5 V, V

= 3.5 V, V = 3.5 V, V = 3.5 V, V = 3.5 V, V = 3.5 V, V = 3.5 V, V = 3.5 V, V

ACTION

, V

DD_X

, V

DD_X

, V

DD_X

, V

DD_X

, V

DD_X

, V

DD_X

, V

DD_X

, V

DD_X

DD_X DD_X DD_X DD_X DD_X DD_X DD_X

= 3.4 V = 3.3 V = 3.2 V = 3.1 V = 3.0 V = 2.9 V = 2.8 V = 2.7 V

= 3.4 V

= 3.4 V = 3.4 V = 3.4 V = 3.4 V = 3.4 V = 3.4 V = 3.4 V

Table 6-4. Supply-Regulator Setting – Automatic – 5-V System

BYTE

ADDRESS

0x00 1 5-V system 0x0B 1 x 1 1 Automatic regulator setting; approximately 250-mV difference 0x0B 1 x 1 0 Automatic regulator setting; approximately 350-mV difference 0x0B 1 x 0 0 Automatic regulator setting; approximately 400-mV difference

(1) x = Don't care

OPTION BITS SETTING IN CONTROL REGISTER

B7 B6 B5 B4 B3 B2

(1)

B1 B0

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Table 6-5. Supply-Regulator Setting – Automatic – 3-V System

BYTE

ADDRESS

0x00 0 3-V system 0x0B 1 x 1 1 Automatic regulator setting; approximately 250-mV difference 0x0B 1 x 1 0 Automatic regulator setting; approximately 350-mV difference 0x0B 1 x 0 0 Automatic regulator setting; approximately 400-mV difference

(1) x = Don't care

OPTION BITS SETTING IN CONTROL REGISTER

B7 B6 B5 B4 B3 B2

(1)

B1 B0

ACTION

6.2.4 Power Modes

The chip has seven power states, which are controlled by two input pins (EN and EN2) and three bits in the Chip Status Control register (00h).

The main reader enable input is EN (which has a threshold level of 1 V [minimum]). Any input signal level from 1.8 V to VINcan be used. When EN is set high, all of the reader regulators are enabled, together with the 13.56-MHz oscillator, and the SYS_CLK output clock for an external MCU.

The auxiliary enable input EN2 has two functions:

• A direct connection from EN2 to VINensures availability of the regulated supply (V auxiliary clock signal (60 kHz) on the SYS_CLK output (same for the case EN = 0). This mode is intended for systems in which the MCU controlling the reader is also being supplied by the reader supply regulator (V the MCU supply and clock be available during power down.

• EN2 enables start-up of the reader system from complete power down (EN = 0, EN2 = 0). In this case, the EN input is controlled by the MCU or other system device that is without supply voltage during complete power down (thus unable to control the EN input). A rising edge applied to the EN2 input (which has a 1-V threshold level) starts the reader supply system and 13.56-MHz oscillator (identical to condition EN = 1). This start-up mode lasts until all of the regulators have settled and the 13.56-MHz oscillator has stabilized. If the EN input is set high by the MCU (or other system device), the reader stays active. If the EN input is not set high within 100 µs after the SYS_CLK output is switched from auxiliary clock (60 kHz) to high-frequency clock (derived from the crystal oscillator), the reader system returns to a complete power-down mode. This option can be used to wake the reader system from complete power down by using a push-button switch or by sending a single pulse.

) and the MCU clock is supplied by the SYS_CLK output of the reader. This lets

DD_X

) and an

After the reader EN line is high, the other power modes are selected by control bits. Table 6-6 lists the power mode options and functions.

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Table 6-6. Power Modes

OPTION BITS SETTING IN CHIP STATUS CONTROL

BYTE

ADDRESS

0x00 0 0 Complete power down <1 µA

0x00 0 1

0x00 1 x x x 1 x

0x00 0 0 x 0 1 x

0x00 0 0 x 1 1 x

0x00 0 1 1 x 1 x

0x00 0 1 0 x 1 x

stby

rfon

rf_pwr

rec_on

EN EN2 FUNCTIONALITY CURRENT

VDD_X available, SYS_CLK auxiliary frequency 60 kHz is ON

All supply regulators active and in low power mode,

13.56-MHz oscillator on, SYS_CLK clock available

All supply regulators active,

13.56-MHz oscillator on, SYS_CLK clock available

All supply regulators active,

13.56-MHz oscillator on, SYS_CLK clock available, Receiver active

All supply regulators active,

13.56-MHz oscillator on, SYS_CLK clock available, Receiver active, Transmitter active in half-power mode

All supply regulators active,

13.56-MHz oscillator running, SYS_CLK clock available, Receiver active, Transmitter active in full-power mode

120 µA

1.5 mA

3.5 mA

10 mA

70 mA

(at 5 V)

120 mA (at 5 V)

During reader inactivity, the TRF796x can be placed in power-down mode (EN = 0). The power down can be complete (EN = 0, EN2 = 0) with no function running, or partial (EN = 0, EN2 = 1) with the regulated supply (V

) and 60-kHz auxiliary clock (SYS_CLK) available to the MCU or other system device.

DD_X

When EN is set high (or on rising edge of EN2 and then confirmed by EN = 1), the supply regulators are activated and the 13.56-MHz oscillator is started. When the supplies are settled and the oscillator frequency is stable, the SYS_CLK output is switched from the auxiliary frequency of 60 kHz to the selected frequency derived from the crystal oscillator. At this time, the reader is ready to communicate and perform the required tasks. The control system (MCU) can then write appropriate bits to the Chip Status Control register (address 0x00) and select the operation mode.

The standby mode (bit 7 = 1 in register 0x00) is the active mode with the lowest current consumption. The reader can recover from this mode to full operation in 100 µs.

The active mode with RF section disabled (bit 5 = 0 and bit 1 = 0 in register 0x00) is the next active mode with low power consumption. The reader is capable of recovering from this mode to full operation in 25 µs.

The active mode with only the RF receiver section active (bit 1 = 1 in register 0x00) can be used to measure the external RF field (see Section 6.3.1) if reader-to-reader anticollision is implemented.

The active mode with the entire RF section active (bit 5 = 1 in register 0x00) is the normal mode used for transmit and receive operations.

6.2.5 Timing Diagrams

Figure 6-2 shows an oscilloscope trace of chip power up. Figure 6-3 shows an oscilloscope trace of chip enable to clock start with EN2 low and EN high.

Figure 6-4 shows an oscilloscope trace of chip enable to clock start with EN2 high and EN low.

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Figure 6-2. Chip Power Up [VIN(Blue) to Crystal Start (Red)]

Figure 6-3. Chip Enable to Clock Start, EN2 Low and EN High (Blue) to Start of System Clock (Red)

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Figure 6-4. Chip Enable to Clock Start, EN2 High and EN Low (Blue) to Start of System Clock (Red)

6.3 Receiver – Analog Section

The TRF796x has two receiver inputs, RX_IN1 (pin 8) and RX_IN2 (pin 9). The two inputs are connected to an external filter to ensure that AM modulation from the tag is available on at least one of the two inputs. The external filter provides a 45° phase shift for the RX_IN2 input to allow further processing of a received PM-modulated signal (if it appears) from the tag. This architecture eliminates any possible communication holes that may occur from the tag to the reader.

The two RX inputs are multiplexed to two receiver channels: the main receiver and the auxiliary receiver. Receiver input multiplexing is controlled by control bit B3 (pm_on) in the Chip Status Control register (address 0x00). The main receiver is composed of an RF-detection stage, gain, filtering with AGC, and a digitizing stage whose output is connected to the digital processing block. The main receiver also has an RSSI measuring stage, which measures the strength of the demodulated signal.

The primary function of the auxiliary receiver is to measure the RSSI of the modulation signal. It also has similar RF-detection, gain, filtering with AGC, and RSSI blocks.

The default setting is RX_IN1 connected to the main receiver and RX_IN2 connected to the auxiliary receiver (bit pm_on = 0). When a response from the tag is detected by the RSSI, values on both inputs are measured and stored in the RSSI Level register (address 0x0F). The control system reads the RSSI values and switches to the stronger receiver input (RX_IN1 or RX_IN2 by setting pm_on = 1).

The receiver input stage is an RF level detector. The RF amplitude level on RX_IN1 and RX_IN2 inputs should be approximately 3 VPPfor a VINsupply level greater than 3.3 V. If the VINlevel is lower, the RF input peak-to-peak voltage level should not exceed the VINlevel. VINis the main supply voltage to the device at pin 2.

The first gain and filtering stage following the RF-envelope detector has a nominal gain of 15 dB with an adjustable band-pass filter. The band-pass filter has adjustable 3-dB frequency steps (100 kHz to 400 kHz for high pass and 600 kHz to 1500 kHz for low pass). Following the band-pass filter is another gain-andfiltering stage with a nominal gain of 8 dB and with frequency characteristics identical to the first stage.

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The internal filters are configured automatically, with internal presets for each new selection of a communication standard in the ISO Control register (address 0x01). If required, additional fine-tuning can be accomplished by writing directly to the RX Special Setting register (address 0x0A). Table 6-22 lists the bits of the RX Special Settings register (address 0x0A) that control the receiver analog section.

6.3.1 Received Signal Strength Indicator (RSSI)

The RSSI measurement block measures the demodulated signal (except in the case of a direct command for RF-amplitude measurement; see Section 6.5). The measuring system latches the peak value, so the RSSI level can be read after the end of the receive packet. The RSSI register values reset with every transmission by the reader. This allows an updated RSSI measurement for each new tag response.

Table 6-7 and Table 6-8 list the correlation between the RF input level and RSSI designation levels on

RX_IN1 and RX_IN2.

Table 6-7 compares the RSSI level and the RSSI bit value. The RSSI has seven levels (3 bits each) with

4-dB increments. The input level is the peak-to-peak modulation level of the RF signal as measured on one side envelope (positive or negative).

Table 6-7. RSSI Level Versus Register Bit Value

RSSI 1 2 3 4 5 6 7

Input level 2 mVpp 3.2 mVpp 5 mVpp 8 mVpp 13 mVpp 20 mVpp 32 mVpp

As an example, from Table 6-8, let B2 = 1, B1 = 1, B0 = 0. This yields an RSSI value of 6. From Table 6-7 a bit value of 6 indicates an RSSI level of 20 mVpp.

Table 6-8. RSSI Bit Value and Oscillator Status Register (0x0F)

BIT SIGNAL FUNCTION COMMENTS

B7 Unused B6 osc_ok Crystal oscillator stable B5 rssi_x2 Most significant bit (MSB) of auxiliary receiver RSSI

4 dB per stepB4 rssi_x1 Auxiliary receiver RSSI B3 rssi_x1 Least significant bit (LSB) of auxiliary receiver RSSI B2 rssi_2 MSB of main receiver RSSI

4 dB per stepB1 rssi_1 Main receiver RSSI B0 rssi_0 LSB of main receiver RSSI

6.3.2 Receiver – Digital Section

The received subcarrier is digitized to form a digital representation of the modulated RF envelope. This digitized signal is applied to digital decoders and framing circuits for further processing.

The digital part of the receiver consists of two sections, which partly overlap. The first section consists of the bit decoders for the various protocols, and the second section consists of the framing logic. The bit decoders convert the subcarrier coded signal to a bit stream and also to the data clock. Thus, the subcarrier-coded signal is transformed to serial data, and the data clock is extracted. The decoder logic is designed for maximum error tolerance. This enables the decoders to successfully decode even partly corrupted (due to noise or interference) subcarrier signals.

In the framing section, the serial bit stream data is formatted in bytes. In this process, special signals like the start of frame (SOF), end of frame (EOF), start of communication, and end of communication are automatically removed. The parity bits and CRC bytes are checked and also removed. The end result is clean or raw data, which is sent to the 12-byte FIFO register where it can be read by the external microcontroller system.

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Texas Instruments TRF7960, TRF7961 Datasheet

1 Device Overview

1.1 Features

1.2 Applications

1.3 Description

1.4 Typical Application

Table of Contents

2 Revision History

3 Device Comparison

3.1 Related Products

4 Terminal Configuration and Functions

4.1 Pin Diagram

4.2 Signal Descriptions

5 Specifications

5.1 Absolute Maximum Ratings

5.2 ESD Ratings

5.3 Recommended Operating Conditions

5.4 Electrical Characteristics

5.5 Thermal Resistance Characteristics

6 Detailed Description

6.1 Overview

6.2 Power Supplies

6.2.1 Negative Supply Connections

6.2.2 Digital I/O Interface

6.2.3 Supply Regulator Configuration

6.2.4 Power Modes

6.2.5 Timing Diagrams

6.3 Receiver – Analog Section

6.3.1 Received Signal Strength Indicator (RSSI)

6.3.2 Receiver – Digital Section