Texas Instruments TRF3040PTR, TRF3040PT, TRF3040PHP Datasheet
TRF3040
MODULATOR/SYNTHESIZER
SLWS057 – AUGUST 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
2-GHz Main Synthesizer, Which
Incorporates a Dual-Mode 32/33 and 64/65
Prescaler for Fractional-N Operation
D
200-MHz Auxiliary Synthesizer, Which
Incorporates an 8/9 Prescaler
D
Separate Supply Terminals for Main and
Auxiliary Charge Pumps
D
Internal Compensation for Fractional Spurs
D
Low Phase Noise
D
Normal and Integral Charge Pump Outputs
D
Fully Programmable Main and Auxiliary
Dividers
D
Serial Data Interface
D
Direct I/Q Modulator
D
Control Logic for Power-Down Modes
D
Single-Sideband Suppressed Carrier
(SSBSC) Converter to Generate TX Carrier
D
200-MHz TXIF Synthesizer and Oscillator
D
Variable Gain Amplifier (VGA) W ith 50 dB of
Dynamic Range
D
900-MHz Power Amplifier (P A) Driver With
9 dBm Typical Output Power
D
Reference and Clock Buffers
D
158 mA Typical Total Operating Current at
3.75 V Supply
D
48-Pin Quad Flatpack (LQFP)
14 15
XTAL–
TXEN
DATA
CLOCK
LOCK
STROBE
V
SSA
V
DD
I
I
Q
Q
36
35
34
33
32
31
30
29
28
27
26
25
16
1
2
3
4
5
6
7
8
9
10
11
12
PHP
V
DDA
RXLO+
RXLO–
V
SSA
V
CCP
TXLO+
TXLO–
V
SSP
PHSOUT
IPEAK
TANK+
17 18 19 20
PHA
RCLK
MCLK
47 46 45 44 4348 42
PHIRFRN
V
GND
40 39 3841
21
22 23 24
37
13
INA
RA
TANK–
V
DDA
DUALTX+
DUALTX–
V
DDA
V
DDA
V
DDA
XTAL+
PT PACKAGE
(TOP VIEW)
SS
V
SSAVSSAVSSAVSSAVSSAVSSA
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1999, Texas Instruments Incorporated
TRF3040
MODULATOR/SYNTHESIZER
SLWS057 – AUGUST 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description
The TRF3040 is an integrated transmit modulator/synthesizer circuit suitable for 900-MHz analog and digital
cellular telephones. It consists of a transmit intermediate frequency (TXIF) synthesizer and oscillator, a
single-sideband suppressed carrier (SSBSC) converter , a direct conversion I/Q modulator , a variable gain
amplifier (VGA) with a power amplifier (PA) driver, a main channel fractional-N synthesizer, an auxiliary
channel synthesizer, a crystal oscillator reference buffer, and clock buffers in a small surface-mount
package. Very few external components are required.
The TXIF synthesizer produces the offset signal, TXIF, needed to translate the external local oscillator
(TXLO) signal to the correct transmission frequency. The TXIF_VCO (voltage controlled oscillator) can
operate from 90 MHz to 200 MHz, depending on the component values chosen for the external tank circuit.
The TXLO signal may be differential or single-ended input.
The direct conversion I/Q modulator places the modulation signal (π/4-DQPSK, FM) directly on top of the
transmit carrier frequency.
The VGA has an output range of –41 dBm to 9 dBm into a 200-Ω differential load. The balanced output signal
simplifies the board layout making it easier to meet isolation requirements.
TRF3040
MODULATOR/SYNTHESIZER
SLWS057 – AUGUST 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
TXIF_
VCO
N
(N = 6, 7, 8, 9)
TXIF
TXIF_LD
+90
+90
+
+
+90
Σ
Control Logic
Main
Prescaler
÷ 32/33
Main Phase
Detector
Reference
Divider
Auxiliary
Phase Detector
Auxiliary
Divider
Lock
Detect
TXLO +
DUALTX+
I
TXEN
DATA
CLOCK
STROBE
PHP
PHI
LOCK
PHA
+
–
RXLO
MCLK
RCLK
INA
TXIF_LD
DUALTX–
TANK+
TANK–
PHSOUT
Σ
+
+
12
13
IPEAK
10
11
3
4
38
39
37
43
26
8
7
25
20
22
28
27
35
34
33
31
1
48
32
41
36
INR
Q
Q
–
XTAL
XTAL
XTAL
OSC
I
+
–
RCLK Buffer
Main Divider
Main
Prescaler
÷ 8/9
Auxiliary Synthesizer
Input Buffer
Reference
Divider Buffer
MCLK Buffer
RXLO Buffer
TXIF
Phase
Detector
and
Charge
Pump
TXIF_VCO
Buffer
TXIF_Buffer
TXLO –
BPF
DUALTX
VGA
I/Q Modulator
Transmit Intermediate
Frequency Synthesizer
SSBSC Converter and TXIF Buffer
TXLO_Buffer
TXRF
PA Driver
TRF3040
MODULATOR/SYNTHESIZER
SLWS057 – AUGUST 1999
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME NO.
I/O
DESCRIPTION
CLOCK
33
I Serial clock input
DATA
34
I Serial data input
DUALTX+
20
†
O Differential RF power amplifier driver
DUALTX–
22
†
O Differential RF power amplifier driver
GND
19
Substrate (GND)
I
28
I Baseband inverting in-phase modulation input
I
27
I Baseband noninverting in-phase modulation input
INA
43
I Auxiliary synthesizer input
IPEAK
11
TX offset loop charge pump current setting resistor
LOCK
32
O Lock detect output
MCLK
38
†
O Buffered master clock output
PHA
41
O Auxiliary charge pump output
PHI
48
†
O Main charge pump integral output
PHP
1
O Main charge pump proportional output
PHSOUT
10
O TX offset charge pump output
Q
25
I Baseband inverting quadrature modulation input
Q
26
I Baseband noninverting quadrature modulation input
RA
42
Auxiliary charge pump current setting resistor
RCLK
39
†
O Buffered reference clock output
RF
47 Fractional compensation charge pump current setting resistor
RN
46 Main charge pump current setting resistor
RXLO+
3 I Differential main synthesizer positive input
RXLO–
4 I Differential main synthesizer negative input
STROBE 31 I Data strobe input
TANK+ 12 I Differential TXIF_VCO tank positive input
TANK– 13 I Differential TXIF_VCO tank negative input
TXEN 35 I Transmit enable
TXLO+ 7 I Differential transmit LO positive input
TXLO– 8 I Differential transmit LO negative input
V
CCP
6
Main charge pump and bandgap supply voltage
V
DD
29 Digital supply voltage
2 Main prescaler and bandgap supply voltage
14 TX offset loop supply voltage
V
DDA
24
†
RF modulator supply voltage
40 Oscillator and buffers supply voltage
44 Auxiliary charge pump supply voltage
17, 18 RF modulator ground
5 Main prescaler and bandgap ground
15 TX offset loop ground
V
SSA
16 TX offset loop and charge pump ground
21, 23 PA driver ground
30 Oscillator, MCLK, and RCLK ground
V
SS
45 Digital ground
V
SSP
9 Main charge pump ground
XTAL+ 37 I Crystal oscillator base input
XTAL– 36 O Crystal oscillator emitter input
†
Pins have limited ESD protection
TRF3040
MODULATOR/SYNTHESIZER
SLWS057 – AUGUST 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Power supply voltage range , V
CCP
, V
DD,
V
DDA
(see Note 1) –0.3 V to 4.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to any other terminal, VIN –0.3 V to VCC/V
DD
+ 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation junction temperature, T
Jmax
150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating temperature, T
A
–40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device, at these or any other conditions beyond those indicated under “recommended operating conditions”, is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .
NOTE 1: Voltage values are in respect to V
SSA
(V
SSA
= V
SSP
= VSS = GND)
recommended operating conditions
PARAMETER
MIN NOM MAX UNIT
Supply voltage, V
CCP
, VDD, V
DDA
3.6 3.75 3.9 V
High-level input voltage, VIH (CLOCK, DATA, STROBE, TXEN) 0.7×V
DD
VDD+0.3 V
Low-level input voltage, VIL (CLOCK, DATA, STROBE, TXEN) –0.3 0.3×V
DD
V
Main synthesizer input frequency, f
IN(RXLO±)
2000 MHz
Main synthesizer input power, P
IN(RXLO±)
, (AC coupled, 50-Ω single ended, 100-Ω differential) –17 dBm
Transmit LO input frequency, f
IN(TXLO±)
1050 MHz
Transmit LO input power , P
IN(TXLO±)
, (AC coupled, 50-Ω single ended, 100-Ω differential) –10 dBm
TXIF_VCO tank differential input frequency, f
IN(TANK±)
200 MHz
Crystal oscillator input frequency, f
IN(XTAL+)
25 MHz
Auxiliary synthesizer input frequency, f
IN(INA)
200 MHz
Auxiliary synthesizer input voltage, V
IN(INA)
, (AC coupled) 0.2 V
PP
In-phase differential input, I/I (quiescent) V
DDA
/2 V
Quadraphase differential input, Q/Q (quiescent) V
DDA
/2 V
Operating free-air temperature, T
A
–40 25 85 °C
dc electrical characteristics V
CCP
= VDD = V
DDA
= 3.75 V, TA = 25°C (unless otherwise noted)
supply current I = I
CCP
+ IDD + I
DDA
PARAMETER TEST CONDITIONS
MIN TYP MAX UNIT
I
SLEEP
Sleep mode supply current 2 3 mA
I
STANDBY
Standby mode supply current 22 mA
I
OPER_ANA
Operating supply current – full power analog mode (MODE=0) 142 mA
I
OPER_DIG
Operating supply current – full power digital mode (MODE=1) 158 mA
dc electrical characteristics V
CCP
= VDD = V
DDA
= 3.75 V, TA = 25°C (unless otherwise noted)
(continued)
digital interface
PARAMETER TEST CONDITIONS
MIN TYP MAX UNIT
p
IO = 1 µA 0.050 V
VOLOutput voltage, lo
w
IO = 2 mA
0.4 V
p
IO = –1 µA VDD – 0.050 V
VOHOutput voltage, high
IO = –2 mA VDD – 0.4 V
TRF3040
MODULATOR/SYNTHESIZER
SLWS057 – AUGUST 1999
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
charge pump PHA
PARAMETER TEST CONDITIONS
MIN TYP MAX UNIT
I
PHA
Output current at PHA 200 250 300 µA
∆I
PHA
I
PHA
Relative output current variation (see Figure 1)
RA = 100 kΩ, V
PHA
= V
DDA
/2
2% 10%
∆I
PHA
Output current matching PHA (see Figure 1) 10%
charge pump PHP, normal mode, VRF = V
DDA
(see Note 2)
PARAMETER TEST CONDITIONS
MIN TYP MAX UNIT
I
PHP
Output current at PHP ±250 ±288 ±320 µA
∆I
PHP
I
PHP
Relative output current variation (see Figure 1)
CN = 128,
RN = 120 kΩ
V
PHP = VDDA/2
,
2% 10%
∆I
PHP
Output current matching PHP (see Figure 1) 10%
NOTE 2: When a serial input word A is programmed, the main charge pump on the PHP and PHI is in the speed-up mode as long as
STROBE is high in standard programming or until the speed-up mode counter reaches its terminal count. When this is not the case,
the main charge pumps are in normal mode.
charge pump PHP, speed-up mode, VRF = V
DDA
(see Note 2)
PARAMETER TEST CONDITIONS
MIN TYP MAX UNIT
I
PHP
Output current at PHP ±1.2 ±1.6 ±1.9 mA
∆I
PHP
I
PHP
Relative output current variation (see Figure 1)
CN = 128,
RN = 120 kΩ
V
PHP
= V
DDA/2
,
2% 10%
∆I
PHP
Output current matching PHP (see Figure 1) 10%
NOTE 2: When a serial input word A is programmed, the main charge pump on the PHP and PHI is in the speed-up mode as long as
STROBE is high in standard programming or until the speed-up mode counter reaches its terminal count. When this is not the case,
the main charge pumps are in normal mode.
charge pump PHI, speed-up mode, VRF = V
DDA
(see Note 2)
PARAMETER TEST CONDITIONS
MIN TYP MAX UNIT
I
PHI
Output current at PHI
±3.3 ±4 ±4.5 mA
∆I
PHI
I
PHI
Relative output current variation (see Figure 1)
CN = 128,
CK = 3,
C
L = 1
RN = 120 kΩ,
V
PHA
= V
DDA
/2,
2% 10%
∆I
PHI
Output current matching PHI (see Figure 1)
CL = 1
10%
NOTE 2: When a serial input word A is programmed, the main charge pump on the PHP and PHI is in the speed-up mode as long as
STROBE is high in standard programming or until the speed-up mode counter reaches its terminal count. When this is not the case,
the main charge pumps are in normal mode.
TRF3040
MODULATOR/SYNTHESIZER
SLWS057 – AUGUST 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
dc electrical characteristics V
CCP
= VDD = V
DDA
= 3.75 V, TA = 25°C (unless otherwise noted)
(continued)
fractional compensation PHP, normal mode, VRN = V
DDA
(see Note 2)
PARAMETER TEST CONDITIONS
MIN TYP MAX UNIT
I
PHP–FR
Output current PHP vs. fractional numerator
FMOD = 1, RF = 120 kΩ,
–340 –270 –170 nA
∆I
PHP–FR
I
PHP–FR
Relative output current (see Figure 1)
,
CN = 128,
CK = 3,
,
V
PHP
= V
DDA/2
,
CL = 1
10%
NOTE 2: When a serial input word A is programmed, the main charge pump on the PHP and PHI is in the speed-up mode as long as STROBE
is high in standard programming or until the speed-up mode counter reaches its terminal count. When this is not the case, the main
charge pumps are in normal mode.
fractional compensation PHP, speed-up mode, VRN = V
DDA
(see Note 2)
PARAMETER TEST CONDITIONS
MIN TYP MAX UNIT
I
PHP–FR
Output current PHP vs. fractional numerator
FMOD = 1,
RF = 120 kΩ
,
–1.7 –1.4 –1.1 µA
∆I
PHP–FR
I
PHP–FR
Relative output current (see Figure 1)
,
CN = 128,
CK = 3,
RF 120 kΩ,
V
PHP
=V
DDA/2
,
CL = 1
15%
NOTE 2: When a serial input word A is programmed, the main charge pump on the PHP and PHI is in the speed-up mode as long as STROBE
is high in standard programming or until the speed-up mode counter reaches its terminal count. When this is not the case, the main
charge pumps are in normal mode.
fractional compensation PHI, speed-up mode, VRN = V
DDA
(see Note 2)
PARAMETER TEST CONDITIONS
MIN TYP MAX UNIT
I
PHI–FR
Output current PHI vs. fractional numerator
FMOD = 1,
RF = 120 kΩ
,
–5.1 –4 –2.9 µA
∆I
PHI–FR
I
PHI–FR
Relative output current (see Figure 1)
,
CN = 128,
CK = 3,
RF 120 kΩ,
V
PHI
= V
DDA/2
,
CL = 1
15%
NOTE 2: When a serial input word A is programmed, the main charge pump on the PHP and PHI is in the speed-up mode as long as STROBE
is high in standard programming or until the speed-up mode counter reaches its terminal count. When this is not the case, the main
charge pumps are in normal mode.
charge pump leakage currents
PARAMETER TEST CONDITIONS
MIN TYP MAX UNIT
I
PHI
Output leakage current PHI
±0.1 ±10 nA
I
PHA
Output leakage current PHA
V
RF
=
V
RN
=
V
DDA
,
V
PHP
= 0 to
V
DDA
±0.1 ±10 nA
TRF3040
MODULATOR/SYNTHESIZER
SLWS057 – AUGUST 1999
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ac electrical characteristics V
CCP
= VDD = V
DDA
= 3.75 V, TA = 25°C (unless otherwise noted)
transmit intermediate frequency synthesizer, SSBSC converter and I/Q modulator
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TXLO± Transmit LO input frequency 900 1100 MHz
TXLO± Transmit LO input power
AC coupled;
50-Ω single-ended,
100-Ω differential
–13 –10 dBm
TANK± TXIF_VCO tank differential input frequency range 155 MHz
PHSOUT TXIF_PD charge pump output level 0.5 V
DDA
–0.5 V
IPEAK TXIF_PD charge pump current setting R
IPEAK
= 13 kΩ 2.3 mA
Kφ TXIF_PD phase gain PLL in phase lock 1.46 mA/rad
XTAL oscillator input frequency 15 25 MHz
XTAL
+
XTAL negative resistance With external capacitors –100 Ω
Frequency range 20 MHz
RCLK,
Output levels
RCLK, MCLK load circuit
0.7 1 1.4 V
PP
MCLK
Harmonic content 10 dBc
Differential input frequency 1.8 MHz
Differential modulation level 0.8 0.9 1.0 V
PEAK
I/I, Q/Q
Differential input impedance 10 kΩ
DC bias point 1.65 1.7 2.0 V
TXRF TX operating frequency range 820 920 MHz
RF output frequency
SE = 1, TXEN = 1,
AMPS/DAMPS
820 853 MHz
Output power (I/Q set to typical conditions)
Open collector, matched to
200 Ω differential impedance
9 dBm
Gain flatness 1 dB
3rd order 33 36 dBc
Linearity in DAMPS mode (I/Q in phase, levels set to
5th order 45 62 dBc
nominal conditions Pout set to 8 dBm)
7th order 53 70 dBc
pp
VGA set to Pout = 8 dBm 26 40
Carrier suppression, I & Q in quadrature
VGA set to Pout = –38 dBm 33
dBc
DUALTX±
Sideband suppression, I & Q in quadrature 25 43 dBc
Adjacent channel noise power Ar 30 kHz offset –95 dBc/Hz
Alternate channel noise power At 60 kHz offset –101 dBc/Hz
TXLO 21 33
Upper sideband 21 60
TXLO conversion products (see Note 3)
TXLO –2×TXIF 15
dBc
TXLO ±3×TXIF 36
Harmonics ≤ 10th 21
Broadband noise (0-dB VGA or 9-dBm output,
whichever is less
869 to 894 MHz –124 dBc/Hz
NOTE 3: Parameters may vary depending on external output matching circuit.
TRF3040
MODULATOR/SYNTHESIZER
SLWS057 – AUGUST 1999
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ac electrical characteristics V
CCP
= VDD = V
DDA
= 3.75 V, TA = 25°C (unless otherwise noted)
(continued)
frequency synthesizers
main divider
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RXLO± Main synthesizer input frequency 2000 MHz
RXLO± Main synthesizer input power
AC coupled, external shunt 50-Ω
single-ended, 100 Ω differential
–17 dBm
RXLO± Main synthesizer input harmonics and subharmonics No multiclocking 30 dBc
reference divider
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Operating frequency 25 MHz
INR
Harmonics No multiclocking 10 dBc
auxiliary divider
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Auxiliary synthesizer input frequency 110 MHz
INA
Auxiliary synthesizer input signal amplitude
No multiclocking
0.2 V
PP
Auxiliary synthesizer input harmonics 10 dBc
p
p
Resistance 5 100 kΩ
Z
INA
Auxiliary synthesizer in ut im edance
Capacitance 3 pF
timing requirements, serial data interface (see Figure 6)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DATA Serial data input rate 10 MHz
CLOCK Serial data clock input 10 MHz
STROBE Serial data strobe input 10
Transmit enable TXEN=1
TXEN
Transmit enable
Transmit disable TXEN=0
Logic
t
su
Setup time: Data to CLOCK, CLOCK to STROBE 30 ns
t
k
Hold time. CLOCK to DATA 30 ns
CLOCK 30
STROBE (B-G words) 100
t
sw
Pulse width
A-word, PR = 01
1/f
VCO
× (NM2 × 65) + t
w
ns
A-word, PR = 10
1/f
VCO
× (NM2 × 65) +
(NM3+1) × 72) + t
w
TRF3040
MODULATOR/SYNTHESIZER
SLWS057 – AUGUST 1999
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
charge-pump current output definitions
I
2
I
1
I
2
I
1
Current
Voltage
∆ I
OUT
REL
∆ I
OUT
MATCH
I
SINK
I
SOURCE
∆ I
OUT
REL
V
1
V
2
Figure 1. Charge-Pump Output Current Definitions
The relative output current variation is defined as the percent difference between charge-pump current output
at two charge-pump output voltages and the mean charge-pump current output (see Figure 1):
D
I
OUT REL
Ť
I
OUT MEAN
Ť
+2
ǒ
I2–I
1
Ǔ
Ť
ǒ
I2)
I
1
Ǔ
Ť
× 100%; with V1+
0.7 V, V2+
V
DDA
–0.8 V.
Output current matching is defined as the difference between charge-pump sinking current output and
charge-pump sourcing current output at a given charge-pump output (see Figure 1).
∆I
OUT MATCH
= I
SINK
– I
SOURCE
; with V1 ≤ Voltage ≤ V2.
TRF3040
MODULATOR/SYNTHESIZER
SLWS057 – AUGUST 1999
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
2
3
4
5
6
7
8
9
10
11
12
1
35
34
33
32
31
30
29
28
27
26
25
36
23
22
21
20
19
18
17
16
15
14
13
24
38
39
40
41
42
43
44
45
46
47
48
37
C1
27pFC2.01µF
C3
15µF
R1
10
VCC
OSC_VCC
R4
9.1k
Ω
C4
.01µF
C5
15pF
C50
15pF
R6
4.7kΩ
RCLK
J1
L1
2200nH
XTAL
R8
9.1kΩ
C6
.01µF
C7
15pF
C71
15pF
R9
4.7kΩ
MCLK
J2
L2
2200nH
C11
DNP
C12
DNP
R11
DNP
TXEN
DATA
CLOCK
LOCK
STROBE
C13
27pF
C14
.01µF
C15
15µF
R12
10
VCC
D_VCC
R13
0
1–
J3
U1
TRF3040
C21
DNP
R15
0
1
J4
C22
DNP
R18
0
Q
J5
C29
DNP
R19
0
Q–
J7
C31
DNP
C23
27pF
C24 C25
.01 µF
R16
0
VCC
RF_VCC
C28
27pF
C27
.01µF
C26
TANK–
PD_VCC
R17
0
VCC
DUALTX
C34
27pF
C98
15 µF
C99
.01µF
R57
0
VCC
PA_VCC
L3
12nH
L4
12nH
DUALTX–
C30
2.2pF
C33
10pF
C35
2.2pF
BALUN1
SLT–090G
1
3
4
6
5
C32
1.8pF
J6
TANK
PHSOUT
R14
18kΩ
PHP
RXLO
TXLO
C97
27pF
C101
.01µF
C104
15µF
R23
10
VCC
AUX_VCC
PHI
R7
120kΩ
R3
33kΩ
R2
100kΩ
PHA
C10
27pF
C9
.01µF
C8
15µF
P_VCC
R10
10
VCC
C19
27pF
C18
.01µF
C17
15µF
CP_VCC
R5
10
VCC
INA
15µF
+
+
+
+
+
+
+
+
Note: DNP = Do Not Place
C16
22pF
C111
3.3pF
15 µF
Figure 2. Evaluation Board Schematic
TRF3040
MODULATOR/SYNTHESIZER
SLWS057 – AUGUST 1999
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
L10
12nH
MVCO
RTL402672
M/CO__VCC
PHP
TXLO
+
PHI
RXLO
+
C102
27pF
L11
12nH
R24
10
C45
100µF
C103
27pF
C46
.01µF
C47
DNP
C107
27pF
(100µF)
VT
VVCO2X1X
2X7
11X
5
8
R20
1.5kΩ
C36
470pF
R21
3.9kΩ
C37
1500pF
C38
1500pF
R22
5.1kΩ
C39
.022µF
TXLO
R43
30
R25
18
R30
18
R42
180
R40
180
L12
5.6nH
C49
4.7pF
R26
18
L13
1.5nH
C51
1pF
R28
49.9
C42
22pF
C48
22pF
J8
STRIPLINE
J9C55
DNP
9dB ATTENUATOR
PAD
R27
62
R29
100
R31
100
R32
49.9
RXLO
9
5dB ATTENUATOR
PAD
+
MAIN VCO
R61
10 MΩ
C56
100 pF
NET00033
R37
1 kΩ
R39
1 kΩ
C65
100 pF
C63
27 pF
C62
.01 µF
C61
1 µF
R38
1 kΩ
V
CC
1
3
2
3
VC1:A
KV1470
VC1:B
KV1470
C60
3 pF
L9
82 nH
TANK+
TANK–
PHSOUT
C57
330 pF
C58
3300 pF
R36
360 Ω
R35
51 kΩ
C59
33 pF
C64
33 pF
+
TANK CKT
Ω
Ω
Ω
ΩΩ
Ω
Ω
Ω
Ω
Ω
Figure 2. Evaluation Board Schematic (continued)
Loading...