Two Operating Modes:
– Philips SA7025 Emulation Mode
Pin-for-Pin and Programming
Compatible
– Extended Performance Mode (EPM)
D
Dual RF – IF Phase-Locked Loops
D
Fractional-N or Integer-N Operation
D
Programmable EPM Fractional
Modulus of 1–16
D
Normal, Speed-Up, and Fractional
CLOCK
DATA
STROBE
V
SS
RFIN
RFIN
V
CCP
REFIN
RA
AUXIN
Compensation Charge Pumps
D
2.9-V to 5.1-V Operation
D
Low-Power Consumption
description
The TRF2050 is a low-voltage, low-power consumption 1.2-GHz fractional-N/integer-N frequency synthesizer
component for wireless applications. Fractional-N division and an integral speed-up charge pump are used to
achieve rapid channel switching. Two operating modes are available: 1) SA7025 emulation mode in which the
part emulates the Philips SA7025 fractional-N synthesizer and 2) extended performance mode (EPM), which
provides additional features including fractional accumulator modulos from 1 to 16 (compared to only 5 or 8 for
the SA7025) and programmable control of the speed-up mode duration (compared to the SA7025 method of
holding the strobe line high).
PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
TRF2050
V
DD
TSETUP
LOCK/TEST
RF
RN
V
DDA
PHP
PHI
V
SSA
PHA
Along with external loop filters, the TRF2050 provides all functions necessary for voltage-controlled oscillator
(VCO) control in a dual phase-locked loop (PLL) frequency synthesizer system. A main channel is provided for
radio frequency (RF) channels and an auxiliary channel for intermediate frequency (IF) channels. The
current-output charge pumps directly drive passive resistance-capacitance (RC) filter networks to generate
VCO control voltages. Rapid main-channel frequency switching is achieved with a charge pump arrangement
that increases the current drive and alters the loop-filter frequency response during the speed-up mode portion
of the switching interval.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Terminals 4, 7, 12, 15, and 20 are for supply voltage. Terminal 19 is for testing. These terminals are not shown.
‡
Conversion and selection block provides emulation of SA7025 64/65/72 triple-modulus prescaler operation using the TRF2050 32/33
dual-modulus prescaler .
IPrescaler positive RF input
IPrescaler negative RF input
IReference frequency input signal
IResistor to V
IResistor to V
IResistor to V
ISerial interface strobe signal
IT est setup for pin 18. For lock detect output, pin 19 connects to VCC through a pullup resistor; for test mode output,
pin 19 terminates to ground.
Prescaler positive supply voltage
Digital supply voltage
Analog supply voltage
Digital ground
Analog ground
sets auxiliary charge pump reference current
SSA
sets proportional and integral charge pump reference current
SSA
sets compensation charge pump reference current
SSA
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Operating ambient temperature range, T
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Voltage values are with respect to V
CCP,
VDD, V
stg
SSA
(see Note 1)–0.6 V to 5.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
High-level input voltage, VIH (CLOCK, DATA STROBE)0.7 × V
Low-level input voltage, VIL (CLOCK, DATA STROBE)–0.30.3 × V
Operating free-air temperature, T
, V
DDA
A
2.9
DD
4.8
VDD +0.3V
–402585°C
5.1
DD
V
V
dc electrical characteristics VDD = V
DDA
= V
=3.6 V, over recommended operating free-air
CCP
temperature range. internal registers: CN = 128, CL = 1, CK = 3, N = 3969, NF = 1, FMOD = 8,
SM = 0, NA = 296, SA = 0, P A = 1. external components: RN = 18 kΩ , RF = 24 kΩ, RA = 100 kΩ (unless
otherwise noted)
supply current: I = IDD + I
PARAMETERTEST CONDITIONS
I
STANDBY
I
MAIN
I
AUX
I
TOTAL
Total standby supply currentsEM = EA = 0 (see Notes 2 and 3)
Operational supply currentsEM = 1, EA = 0 (see Note 3)
Operational supply currentsEM = 0, EA = 1 (see Note 3)
Operational supply currents
NOTES: 2. VRN = VRA = VRF = V
3. For optimum standby and operational current consumption, the following condition should be be maintained:
VDD ≤ V
DDA
digital interface
V
OH
V
OL
I
IH
I
IL
High-level output voltage
Low-level output voltage
High-level input current
Low-level input current
+ I
CCP
DDA
EM = EA = 1 (see Note 3)
DDA
< VDD + 1.
PARAMETERTEST CONDITIONS
IOH = 2 mAVDD –0.5V
IOL = – 2 mA0.5V
MIN
TYP
MAX
7.0
1.5
7.5
200
UNIT
µA
mA
mA
mA
MINTYPMAXUNIT
10µA
10µA
charge pump currents (see Figure 1)
auxiliary charge pump
|I
|Output current PHA
PHA
∆I
PHA
|I
|
ÁÁÁ
PHA
∆I
PHA
proportional charge pump, normal mode, VRF = V
|I
PHP-NM
∆I
|I
PHP-NM
ÁÁÁ
∆I
4
PHP-NM
PHP-NM
|
|
PARAMETER
Relative output current variation PHA (see Figure 1)
Output current matching PHA (see Figure 1)
DDA
PARAMETER
Output current PHP
Relative output current variation PHP (see Figure 1)
ac electrical characteristics, VDD = V
(continued)
auxiliary divider
PARAMETERTEST CONDITIONS
ÁÁÁ
ÁÁÁ
ÁÁÁ
ÁÁÁ
f
AUXIN
ÁÁÁ
ÁÁÁ
reference divider
f
REFIN
V
I_REFIN
Auxiliary input frequency (ac-coupled)
p
p
PARAMETERTEST CONDITIONS
Reference input frequency
Reference input voltageac-coupled
p
p
CCP
= V
= 3.6 V, TA = 25°C (unless otherwise noted)
DDA
PA = 0:
V
= VDD = 3.6 V
DDA
V
I_AUXIN
V
I_AUXIN
PA = 0:
V
= VDD = 4.8 V
DDA
V
I_AUXIN
PA = 1:
V
= VDD = 3.6 V
DDA
V
I_AUXIN
PA = 1:
V
= VDD = 4.8 V
DDA
ББББББББ
V
I_AUXIN
= 560 mVpp
= 200 mVpp
= 200 mVpp
= 200 mVpp
= 200 mVpp
MIN
TYP
MAX
Á
Á
Á
Á
Á
125
Á
70
Á
Á
ÁÁÁÁÁ
ÁÁÁÁÁ
Á
Á
Á
110
Á
40
72
5
100
3
MIN
TYP
MAX
40
200
100
3
UNIT
Á
MHz
Á
MHz
Á
MHz
Á
Á
MHz
Á
MHz
kΩ
pF
UNIT
MHz
mVpp
kΩ
pF
timing requirements, serial data interface (see Figure 2)
f
CLOCK
t
w_CLKHI
t
w_CLKLO
t
su_Data
t
h_Data
t
h_Strobe
t
su_Strobe
t
w_STRBHI
Clock frequency10MHz
Clock high time pulse width, CLOCK high30ns
Clock low time pulse width, CLOCK low30ns
Setup time, data valid before CLOCK↑30ns
Hold time, data valid after CLOCK↑30ns
Hold time, STROBE high before CLOCK↑30ns
Setup time, STROBE lowafter CLOCK↑30ns
STROBE high time pulse width, STROBE high
The relative output current variation is defined as the percent difference between charge-pump current output
at two charge-pump output voltages and the mean charge-pump current output (see Figure 1):
D
I
OUT REL
Ť
I
OUT MEAN
+2
Ť
ǒ
I2–I
ǒ
Ť
I2)
Ǔ
1
×100%; with V1+
Ǔ
Ť
I
1
0.7 V, V2+
V
DDA
–0.8 V.
Output current matching is defined as the difference between charge-pump sinking current output and
charge-pump sourcing current output at a given charge-pump output (see Figure 1).
20603 1.6x.08PanasonicERJ–3GSYJ221
40603 1.6x.08PanasonicERJ–3GSYJ271
2.25” squareBourns3269W001102
10603 1.6x.08PanasonicERJ–3GSYJ series
20603 1.6x.08PanasonicERJ–3GSYJ series
10603 1.6x.08PanasonicERJ–3GSYJ series
20603 1.6x.08PanasonicERJ–3EKF49R9
60603 1.6x.08PanasonicERJ–3GSYJ series
10603 1.6x.08PanasonicERJ–3GSYJ series
10603 1.6x.08PanasonicERJ–3GSYJ series
10603 1.6x.08PanasonicERJ–3GSYJ series
20603 1.6x.08PanasonicERJ–3GSYJ series
10603 1.6x.08VenkelCR0603–16W–000J1
10603 1.6x.08PanasonicERJ–3GSYJ series
10603 1.6x.08PanasonicERJ–3GSYJ series
10603 1.6x.08PanasonicERJ–3GSYJ series
40603 1.6x.08PanasonicERJ–3GSYJ series
10603 1.6x.08PanasonicERJ–3GSYJ series
30603 1.6x.08PanasonicERJ–3GSYJ series
10603 1.6x.08PanasonicERJ–3GSYJ series
The TRF2050 internal registers are programmed using a three-wire (CLOCK, DA TA, STROBE) serial interface.
The serial data is structured into 24-bit standard-length or 32-bit long-length words of which one or four bits are
dedicated address bits. The flag LONG in the D-Word determines whether the A0 (LONG = 0) or A1
(LONG = 1) format is applicable. Figures 18 and 19 show the format of the serial data for two modes of TRF2050
operation: SA7025 and EPM, respectively. The least significant bit (LSB) of the C-Word determines the
operational mode of the TRF2050: 0 = SA7025, 1 = EPM.
In SA7025 mode, the TRF2050 emulates the Philips SA7025 with respect to serial programming.
Microcontroller software written for the SA7025 works transparently when the TRF2050 is operated in SA7025
emulation mode.
Figure 2 shows the timing diagram of the serial input. When the STROBE signal is low, the signal on the DAT A
input is clocked into a shift register on the positive edges of the CLOCK. When the STROBE signal is high,
depending on the 1 or 4 address bit(s), the data is latched into different working registers or temporary registers.
In order to fully program the synthesizer, four words must be sent: D, C, B, and A. The E-Word is for testing
purposes only.
TRF2050
The A-Word contains new data for the main divider. The A-Word is loaded only when a main divider
synchronization signal is also active. This is done to avoid phase jumps during reprogramming the main divider.
The synchronization signal is generated by the main divider.
When the TRF2050 is operated in SA7025 emulation mode, programming the A-Word sets the main charge
pumps, which are located on outputs PHP and PHI, into speed-up mode, as long as the STROBE is high. When
the TRF2050 is operated in EPM mode, speed-up mode duration is determined by field G in the B-Word.
NOTE:
The C-Word must be sent during the first programming cycle after power-up
in order to set the mode of operation (7025 or EPM).
T able 2. SA7025 Emulation Serial-Word-Format Function Listing
SYMBOL
CK
CL
CN
EA
ÁÁÁ
BITSFUNCTION
4Binary acceleration factor for integral charge pump current
2Binary acceleration factor for proportional charge pump current
8Binary current-setting factor for main charge pumps
1Auxiliary divider enable flag:
ÁÁÁÁ
0 = disabled
1 = enabled
EM1Main divider enable flag:
ÁÁÁ
0 = disabled
1 = enabled
FMOD
ÁÁÁ
ÁÁÁ
LONG
1Fractional-N modulus selection:
ÁÁÁÁ
ÁÁÁÁ
0 = modulo 5
1 = modulo 8
1A word format selection:
0 = 24-bit A0 format
ÁÁÁ
ÁÁÁÁ
1 = 32-bit A1 format
MS2Mode select
00 = 7025 Emulation Mode
NA12Auxiliary divider ratio
NF
NM1
NM2
ÁÁÁ
NM3
3Fractional-N increment
12Number of main divider cycles when prescaler modulus = 64
8 if PR = 01
4 if PR = 10
ÁÁÁÁ
Number of main divider cycles when prescaler modulus = 65
4 if PR = 10Number of main divider cycles when prescaler modulus = 72
NR12Reference divider ratio
PA1Auxiliary prescaler select:
ÁÁÁ
ÁÁÁ
PR
2Prescaler type:
0 = divide by 4
1 = divide by 1
PR = 01; modulus 2 prescaler (64/65)
ÁÁÁ
ÁÁÁÁ
PR = 10; modulus 3 prescaler (64/65/72)
SA2Reference select for auxiliary phase detector
SM2Reference select for main phase detector
T2Test mode connection of internal signals to the LOCK terminal:
YesBinary acceleration factor for integral charge pump current
YesBinary acceleration factor for proportional charge pump current
YesBinary current setting factor for main charge pumps
0 = positive
1 = negative
Auxiliary divider enable flag:
0 = disabled
ÁÁÁ
Á
ÁÁ
1 = enabled
Main divider enable flag:
EM
ÁÁÁ
FMOD
G
1Yes
Á
5NoFraction accumulator modulus
4
NoSpeed-up mode duration (See Table 9)
0 = disabled
1 = enabled
Main charge pump polarity:
MCP
ÁÁÁ
MS
N
NA
NF
NR
1
Á
2
18
12
4
No
ÁÁ
No
NoOverall main divider integer division ratio (NM)
YesAuxiliary divider ratio
NoFractional-N increment
12YesReference divider ratio
0 = positive
1 = negative
Mode select
01 = Extended Performance Mode
Auxiliary prescaler select:
PA
ÁÁÁ
1Yes
Á
0 = divide by 4
1 = divide by 1
SA2YesReference select for auxiliary phase detector
SM
2YesReference select for main phase detector
T2YesTest mode connection of internal signals to the LOCK terminal:
The differential RFIN inputs are amplified to internal ECL logic levels and provide excellent sensitivity (better
than –20 dBm at 1 GHz), making the prescaler ideally suited for direct interface with a VCO. The internal
dual-modulus (32/33) prescaler and counter sections divide the VCO frequency down to the reference phase
detector frequency . The prescaler division ratio (÷32 or ÷33) is controlled by a feedback signal that is a function
of the 18-bit N-field counters. The N-field counter section is composed of two separate counters: a 5-bit
A-Counter and a 13-bit B-Counter. The prescaler divides by 33 until the A-Counter reaches terminal count and
then divides by 32 until the B-Counter reaches terminal count, whereupon both counters reset and the cycle
repeats. The following equation relates the total N division as a function of the 32/33 prescaler:
N
= 32 (B – A) + 33(A), where 0 ≤ A ≤ 31, and 31 ≤ B ≤ 8191.
Total
It is not necessary to determine the values of A and B in the equation above; simply program the N field with
the total division ratio desired (fractional effects ignored).
The N-division ratio has a range of 992 ≤ N
RFIN
Structure of N-Word
AB
5 Bits13 Bits
LSBMSB
N
4
NF
FMOD
5
32/33 Prescaler
N
18
5-Bit
Fraction Accumulator
≤ 262143.
Total
13-Bit
B-Counter
5-Bit
A-Counter
5
18-Bit Register
18
18-Bit
Adder
to Phase Detector
13
Figure 20. Main Divider Organization
main divider – SA7025 emulation
The internal triple modulus prescaler configuration of the SA7025 provides for prescaler division ratios of
64/65/72. The TRF2050 has internal conversion logic that allows the TRF2050 to emulate the SA7025 main
divider operation. When operated in SA7025 emulation mode, the TRF2050 is programmed using the SA7025
serial interface format shown in Figure 18. The TRF2050 internal conversion is transparent and need not be
considered under normal use, thereby allowing use of existing SA7025 programming codes without change.
The following equations relate the total N-division as a function of the emulated 64/65 dual-modulus and
64/65/72 triple-modulus prescalers:
For contiguous channels, the following rules must be observed:
For PR = 01: 61 ≤ NM1 ≤ 4095 and 0 ≤ NM2 ≤ 63, which yields minimum and maximum divide ratios of 4032
and 266303, respectively.
For PR = 10: 14 ≤ NM1 ≤ 4095 and 0 ≤ NM2 ≤ 15, and 0 ≤ NM3 ≤ 15, which yields minimum and maximum divide
ratios of 1096 and 264335, respectively.
main divider – synchronization
The A-Word is loaded only when a main divider synchronization signal is active. This prevents phase jumps
when reprogramming the main divider. The synchronization signal is generated by the main divider, and it is
active while the main divider is counting down from the programmed value. When the main divider reaches its
terminal count, a main divider output pulse is sent to the main phase detector. Also at this time, the loading of
the A-Word is disabled. Therefore, to correctly load the new A-Word, the STROBE signal must be active high
for at least a minimum number of VCO input cycles at RFIN.
main divider – fractional accumulator
The TRF2050 main synthesizer loop can operate as a traditional integer-N feedback PLL or as a fractional-N
feedback PLL. The integer-N feedback loop divides the VCO frequency by integer values of N, which results
in phase detector reference comparisons at the desired channel spacing. A fractional-N feedback loop divides
the VCO frequency by an integer term plus a fractional term, which results in phase detector reference
comparisons at integer multiples of the desired system channel spacing.
TRF2050
Integer-N division: VCO frequency N = phase detector reference frequency
= channel spacing
Fractional-N division: VCO Frequency (N + NF/FMOD) = phase detector reference frequency
= FMOD × channel spacing
where 0 ≤ NF < FMOD and 1 ≤ FMOD ≤ 16.
Because the main counter and prescaler sections cannot divide by a fraction of an integer, the fractional-N
division is accomplished by averaging main divider cycles by N and N+1. A fractional accumulator is
programmed with values of NF and FMOD to control the main counter and prescaler sections to divide by N
or N+1.
The fractional accumulator operates modulo FMOD and is incremented by NF at the completion of each main
divider cycle. When the fractional accumulator overflows, division by N+1 occurs. Otherwise, the main counters
and prescaler divide by N; division by N+1 is transparent to the user. Table 4 shows the contents of the fractional
accumulator and the resulting N or N+1 division for two fractional division ratios.
For example, suppose that a typical AMPS channel of 953.25 MHz is desired. Because AMPS channel spacing
is 30 kHz, for fractional-N operation the main phase detector reference frequency must be a multiple of 30 kHz;
240 kHz is typical. A value of FMOD = 8 is selected because 240 kHz / 30 kHz = 8. Dividing the channel frequency
by the reference frequency results in 953.13 ÷ 240 kHz = 3971.375 = 3971 + 3/8. This example is shown in
T able 4 where NF = 3 and FMOD = 8. The table shows that over the period of a complete fractional accumulator
cycle, the fractional accumulator overflows three times for every eight main divider cycles. Figure 21 illustrates
the division by N or N+1 for this 3/8 fractional channel example.
Number of Main
Divider Pulses
N
(3971)
N
(3971)
N + 1
(3972)
ACCUMULATOR
NUMERATOR
N
(3971)
4
0
6
4
2
0
N
(3971)
STATE
÷ N
÷ N + 1, overflow
÷ N + 1, overflow
÷ N + 1, overflow
÷ N
÷ N + 1, overflow
÷ N + 1, overflow
÷ N + 1, overflow
N + 1
(3972)
N
(3971)
(3972)
N + 1
RF Input
Main Divider Out
Figure 21. 3/8 Fractional Channel Main Divider Operation
The mean division over the complete fractional accumulator cycle as shown in Figure 21 is:
N
MEAN
3971)3971)3972)3971)3971)3972)3971)3972
+
+
3971)3ń8
8
Therefore, fractional channels are available every 30 kHz or 240 kHz
1
FMOD
240 kHz
+
+
3971.375
8
.
main divider – integer channels
In the case where NF = 0, only division by N occurs, and the fractional accumulator is essentially in a steady
state with a numerator of 0. It never increments or overflows. A channel that requires NF = 0 is a pure integer
main divider – fractional-N sidebands and compensation
Programming a fractional-N channel means the main divider and prescaler divide by N or N + 1 as dictated by
the operation of the fractional accumulator. Because the main divider operation is integer in nature and the
desired VCO frequency is not, the output of the main phase detector is modulated with a resultant fractional-N
phase ripple that produces sideband energy if left uncompensated. This phase ripple is proportional and
synchronized to the contents of the fractional accumulator that is used to control fractional-N sideband
compensation. Only channels that require a nonzero value of NF have the fractional-N sideband energy. The
fractional-N sidebands, which appear at offset frequencies from the VCO fundamental tone, are multiples of
NF/FMOD. Figure 22 shows the fractional-N phase detector ripple for a 3/8 fractional channel.
240 kHz
Main Phase
Detector Reference
Main Phase
Detector VCO
Feedback
TRF2050
Detector Fractional-N
Main Phase
Ripple
Fractional
Accumulator State
036147250
Figure 22. Fractional-N Phase Detector Ripple for 3/8 Channel
The TRF2050 has internal circuitry that provides a means to compensate for the phase detector fractional-N
phase ripple, thereby significantly reducing the magnitude of the fractional-N sidebands. Because the current
waveform output of the main PLL proportional charge pumps is modulated with the phase detector fractional-N
phase ripple, a fractional-N compensation charge-pump output is summed with the main PLL proportional
charge pump.
Figure 23 shows the fractional-N ripple magnitude on the main PHP charge-pump output. The magnitude is
essentially constant, and the pulse width is modulated with the contents of the fractional accumulator. The area
under the main PHP charge-pump curve represents the amount of charge delivered to the loop filter network.
In order to minimize fractional-N sidebands in the VCO spectrum, the compensation current waveform is
generated to have
Figure 23. Main PHP and Compensation Charge Pump Fractional-N Waveforms for 3/8 Channel
The compensation waveform is pulse-amplitude modulated with the contents of the fractional accumulator. The
main PHP pulse magnitude is much larger than the compensation pulse magnitude but the compensation pulse
has a much longer duration than that of the main PHP pulse. The compensation pulse is optimally centered
about the main PHP charge pump pulse in order to avoid additional sideband energy due to the phase offset
between the main and compensation pulses.
The following example illustrates a method for determining correct values for RN, RF, and CN for minimal
fractional-N sidebands based on VCO frequency and reference frequency.
Assumptions:
The main VCO is locked on channel.
953 MHz ± 10 MHz main VCO operation, 942.99 – 962.91 MHz
19.44 MHz reference frequency
240 kHz phase detector reference frequency
500 µA peak main PHP current
1. Determine the fundamental fractional-N pulse width portion of the main PHP charge-pump output waveform
for the lower, upper, and mean frequencies.
Frac
Frac
Frac
PW–MEAN
PW–LWR
PW–UPR
+
+
+
1
f
PD
1
f
PD
Frac
N
–
f
VCO
N
–
f
VCO
PW*LWR
+
240 kHz
+
240 kHz
)
2
1
1
Frac
PW–UPR
3929
–
942.99 MHz
4012
–
962.91 MHz
+
132.557 ps,
+
129.815 ps,
132.557 ps)129.815 ps
+
2
+
131.186 ps.
The mean-unit pulse width of the fractional-N portion of the main PHP charge-pump output waveform over
the VCO frequencies of interest is 131.186
ps
. This fundamental pulse width is modulated by the contents
of the fractional accumulator. For the 3/8 fractional-N channel example, the pulse width varies as shown
in Table 5.
5. Determine the values of CN and RN for the main PHP charge-pump peak current of 500 µA. Assume that
a midrange value of CN equals 128.
ǒ
RN(k
W)+
6. The value of the fundamental compensation pulse magnitude calculated in step 3 is fixed and the
compensation pulse width calculated in step 2 is also fixed. However, because the VCO can tune over a
significant range of frequencies, the pulse width of the fractional-N portion of the main PHP charge-pump
waveform varies; thus, the area of the same waveform varies. In order to maintain equal areas under the
fractional-N portion of the main PHP charge-pump and compensation waveforms, CN must vary with the
VCO frequency . As the VCO frequency increases, the fractional-N portion of the main PHP charge-pump
waveform pulse width decreases proportionally, thereby decreasing the area under the same waveform.
Therefore, CN is adjusted to equalize the main PHP and compensation waveform areas, as follows:
Frac
PW-LWR
Frac
PW-UPR
The fundamental area of the fractional-N portion of the main PHP charge-pump waveform (step 1) is
calculated as 0.065593 picosecond x amperes. If you calculate the fundamental area of the fractional-N
portion of the main PHP charge-pump waveform using the actual pulse widths above in place of the average
pulse width calculated in step 1, the fractional-N main PHP areas is obtained as follows:
Frac
Area-L WR
Frac
Area-UPR
The actual areas under the fractional-N portion of the main PHP waveform require slight modification in the
charge-pump current. The variation of CN required for area equalization is determined using a simple ratio
form:
Therefore, for this example, CN can vary from 126-130 over the VCO frequency range of 942.99 – 962.91
MHz for optimum fractional-N sideband suppression. Due to component and circuit tolerances, additional
deviations in CN may be appropriate.
auxiliary divider
The input signal on AUXIN is amplified by a single-ended, ac-coupled input buffer/amplifier that has sufficient
sensitivity (200 mVpp at 200 MHz) for direct connection to a typical VCO. The 12-bit (NA) auxiliary divider
incorporates a divide by 1 (P A = 1) or divide by 4 (PA = 0) prescaler . The total division ratio can be expressed
as:
The input signal on REFIN is amplified by a single-ended, ac-coupled input buffer/amplifier that has sufficient
sensitivity (300 mVpp at 50 MHz) for direct connection to a typical TCXO. The 12-bit (NR) reference divider total
division ratio can be expressed as:
N
= NR, where NR = 4 to 4095
Total
A four-section postscaler is connected to the output of the reference divider section. The main and auxiliary
synthesizer sections can individually select a reference postscaler division of 1, 2, 4, or 8 by programming fields
SM and SA, respectively (see Figure 24).
MAIN SELECT
SM = “00”
TRF2050
Reference Input
Divide by NR
SM = “01”
SM = “10”
SM = “11”
÷ 2÷ 2÷ 2
AUXILIARY SELECT
SA = “11”
SA = “10”
SA = “01”
SA = “00”
Main Phase
Detector
Auxiliary
Phase Detector
Figure 24. Reference Divider
phase detectors
The main and auxiliary synthesizer sections (see Figure 25) incorporate dual D-type flip-flop phase-frequency
detectors (PFD). A PFD has gain with a phase error over a range of ±2π and exhibits an infinite pull-in range.
Dead-band compensation about zero-phase error is provided by forcing the sourcing and sinking charge pumps
to have a minimum on-time of 1/f
The phase detectors can be programmed for polarity sense. Normally , external system VCOs have a positive
slope control-voltage frequency characteristic. Some VCOs have a negative slope characteristic. The TRF2050
main and auxiliary phase detectors can be programmed for use with positive or negative slope VCOs using the
MCP
and
ACP
fields, respectively, in the B-Word (EPM mode).
when the loop is operating in a locked condition.
Ref
For positive slope VCOs: MCP = ACP = 0
For negative slope VCOs: MCP = ACP = 1
Figure 25. Main and Auxiliary Phase Detector Circuit
charge-pump current plans
The TRF2050 uses internal band-gap references and external resistors to develop biasing reference currents
for the various charge pumps sections. Three terminals are designated for the external resistors: RN, RF, and
RA. Internal, programmable coefficients CN, CL, and CK are also used. T able 7 shows how the external resistors
are used to achieve desired charge-pump peak currents.
Table 7. Charge Pump Current Plans
PARAMETERMODECONDITIONUNIT
x
x
Ǔ
CN
256
CN
Ǔ
256
xCKx2
CL)1
Ǔ
Peak proportional, normal mode current PHP
Peak proportional, speed-up mode current
18.75
PHP
PK*SM
Peak integral, speed-up mode current PHI
†
Peak compensation, normal mode current
Peak auxiliary current PHAPK+
†
The compensation charge
Divider – Fractional-N Sidebands and Compensation.
ǒ
+
RN)0.75
CN
Ǔ)ǒ
x
256
1.25
ǒ
RA
-pump current is a pulse-amplitude modulated with the contents of the fractional accumulator. See the section on Main
PK*NM
18.75
RN)0.75
PK*SM
CompPK+
Ǔ
x20
+
x
256
ǒ
+
RN)0.75
30
RF
18.75
ǒ
RN)0.75
CN
x2
18.75
CL)1
The average charge-pump current for the PHP, PHI, and PHA terminals is defined by:
The main and auxiliary loops can be enabled and disabled by the contents of the enable bits EM and EA,
respectively. When disabled, all currents in the RF input stages are switched off; the bias currents for the
respective charge-pump circuits are switched off as well. When both loops are disabled (EM = EA = 0), the
reference input stage currents are switched off. The reference chain can be turned off because the serial
interface operates independent of the reference input for the loading of serial words.
When the main synthesizer frequency is changed, it may be desirable to increase the loop bandwidth for a short
time in order to achieve a faster lock time. The proportional charge-pump current is increased and the integral
charge-pump current is switched on for the duration of speed-up mode. The section,
plans
, illustrates how the charge-pump currents are a function of the external resistor RN and the programmable
coefficients CN, CL, and CK.
The duration of the speed-up mode is determined by the operational mode of the TRF2050 device: enhanced
performance mode (EPM) or SA7025 emulation mode. In EPM mode, the speed-up mode duration is controlled
as a function of the G field in the B-Word and the reference frequency divider period.
Table 9. Speed-Up Mode
G VALUEDURATION
0–14[(G+1) × NR × SM × 16]/f
15< (NR ×SM)/(f
When the TRF2050 is operated in SA7025 emulation mode, the speed-up mode duration is a function of the
STROBE signal associated with the A-Word. When the STROBE signal followed by an A-Word write transaction
goes active, the speed-up mode currents begin and persist until the STROBE signal is returned to an inactive
state.
REFIN
REFIN
× 2); which is less than 1/2 a phase detector cycle
EPM
charge-pump current
lock detect
The lock condition of the PLL is defined as a phase difference of less than a ±1 cycle on the reference input
REFIN. The LOCK terminal can be polled to determine the synthesizer lock condition of either or both loops.
The lock detect function is described by the Boolean expression:
The LOCK terminal may be used for test operations by terminating pin 19 to ground. When test modes are
enabled, the LOCK
ones to the two LSBs of the E-Word. Test modes are disabled by terminating pin 19 to V
resistor of 10 kΩ.
T1T0MODE
00Buffered output of the fractional accumulator
01Buffered output of the auxiliary divider
10Buffered output of the main divider
11Buffered output of the reference divider
The test mode can be used to verify the division ratio of the reference divider, the auxiliary divider , and the main
divider and prescaler.
terminal is connected to internal nodes of the TRF2050. T est modes are enabled by writing
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
8
3,10
2,90
14
5,10
4,90
16
5,10
20
6,60
6,404,90
24
7,90
7,70
28
9,80
9,60
4040064/D 10/95
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
33
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
Loading...
+ hidden pages
You need points to download manuals.
1 point = 1 manual.
You can buy points or you can get point for every manual you upload.