Texas Instruments TRF2050PW Datasheet

LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER

SLWS030D– JUNE 1996 – REVISED OCTOBER 1998

D

1.2-GHz Operation

D

Two Operating Modes: – Philips SA7025 Emulation Mode

Pin-for-Pin and Programming Compatible

– Extended Performance Mode (EPM)

D

Dual RF – IF Phase-Locked Loops

D

Fractional-N or Integer-N Operation

D

Programmable EPM Fractional Modulus of 1–16

D

Normal, Speed-Up, and Fractional

CLOCK

DATA

STROBE

V

SS

RFIN RFIN

V

CCP

REFIN

RA

AUXIN

Compensation Charge Pumps

D

2.9-V to 5.1-V Operation

D

Low-Power Consumption

description

The TRF2050 is a low-voltage, low-power consumption 1.2-GHz fractional-N/integer-N frequency synthesizer component for wireless applications. Fractional-N division and an integral speed-up charge pump are used to achieve rapid channel switching. Two operating modes are available: 1) SA7025 emulation mode in which the part emulates the Philips SA7025 fractional-N synthesizer and 2) extended performance mode (EPM), which provides additional features including fractional accumulator modulos from 1 to 16 (compared to only 5 or 8 for the SA7025) and programmable control of the speed-up mode duration (compared to the SA7025 method of holding the strobe line high).

PW PACKAGE

(TOP VIEW)

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

TRF2050

V

DD

TSETUP LOCK/TEST RF RN V

DDA

PHP PHI V

SSA

PHA

Along with external loop filters, the TRF2050 provides all functions necessary for voltage-controlled oscillator (VCO) control in a dual phase-locked loop (PLL) frequency synthesizer system. A main channel is provided for radio frequency (RF) channels and an auxiliary channel for intermediate frequency (IF) channels. The current-output charge pumps directly drive passive resistance-capacitance (RC) filter networks to generate VCO control voltages. Rapid main-channel frequency switching is achieved with a charge pump arrangement that increases the current drive and alters the loop-filter frequency response during the speed-up mode portion of the switching interval.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1998, Texas Instruments Incorporated

1

TRF2050

/

LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER

SLWS030D– JUNE 1996 – REVISED OCTOBER 1998

functional block diagram

2

DATA

RFIN RFIN

1 3

5 6

8

10

EM

32/33 Prescaler

EM+EA

EA

FMOD

Accumulator

†

PA

4/1

5

Fraction

Main Divider

Reference

Divider

CLOCK

STROBE

REFIN

AUXIN

†

NF

(N/N+1)

NR

NA

Auxiliary

Divider

Serial Control Shift Registers

Common Registers EPM Registers 7025 Registers

‡

8

12

Conversion and Selection

4

N

18

12

SA

2

Control Lines

Fraction

Compensation

Phase

Detector

SM

2

Select

124

Select

Phase

Detector

CK

CN

4

Compensation

Charge Pump

CL

8

Proportional

Charge Pump

CL

8

Integral

Charge Pump

Auxiliary

Charge Pump

17

RF

2

14

PHP

16

RN

2

13

PHI

18

LOCK TEST

9

RA

11

PHA

†

Terminals 4, 7, 12, 15, and 20 are for supply voltage. Terminal 19 is for testing. These terminals are not shown.

‡

Conversion and selection block provides emulation of SA7025 64/65/72 triple-modulus prescaler operation using the TRF2050 32/33 dual-modulus prescaler .

2

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I/O

DESCRIPTION

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

Á

ÁÁÁ

TERMINAL

NAME NO.

AUXIN CLOCK DATA LOCK/

TEST

ÁÁ

PHA PHI PHP RFIN RFIN REFIN RA RN RF STROBE TSETUP

ÁÁ

V

CCP

V

DD

V

DDA

V

SS

V

SSA

10

1 2

18

ÁÁ

11 13 14

5 6 8

9 16 17

3 19

ÁÁ

7 20

15

4 12

TRF2050

LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER

SLWS030D– JUNE 1996 – REVISED OCTOBER 1998

Terminal Functions

I Auxiliary channel RF input I Serial interface clock signal I Serial interface data signal

O Lock detector/test mode output

O Auxiliary charge pump output O Integral charge pump output O Proportional charge pump output

I Prescaler positive RF input I Prescaler negative RF input I Reference frequency input signal I Resistor to V I Resistor to V I Resistor to V I Serial interface strobe signal I T est setup for pin 18. For lock detect output, pin 19 connects to VCC through a pullup resistor; for test mode output,

pin 19 terminates to ground. Prescaler positive supply voltage Digital supply voltage Analog supply voltage Digital ground Analog ground

sets auxiliary charge pump reference current

SSA

sets proportional and integral charge pump reference current

SSA

sets compensation charge pump reference current

SSA

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

Input voltage range, logic signals –0.6 V to 5.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating ambient temperature range, T Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: Voltage values are with respect to V

CCP,

VDD, V

stg

SSA

(see Note 1) –0.6 V to 5.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DDA

A

.

–55°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

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3

TRF2050

LOCK/TEST

DATA, CLOCK, STROBE

Á

LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER

SLWS030D– JUNE 1996 – REVISED OCTOBER 1998

recommended operating conditions

MIN NOM MAX UNIT

Supply voltage, V

CCP, VDD

High-level input voltage, VIH (CLOCK, DATA STROBE) 0.7 × V Low-level input voltage, VIL (CLOCK, DATA STROBE) –0.3 0.3 × V Operating free-air temperature, T

, V

DDA

A

2.9 DD

4.8 VDD +0.3 V

–40 25 85 °C

5.1

DD

V

dc electrical characteristics VDD = V

DDA

= V

= 3.6 V, over recommended operating free-air

CCP

temperature range. internal registers: CN = 128, CL = 1, CK = 3, N = 3969, NF = 1, FMOD = 8, SM = 0, NA = 296, SA = 0, P A = 1. external components: RN = 18 kΩ , RF = 24 kΩ, RA = 100 kΩ (unless otherwise noted)

supply current: I = IDD + I

PARAMETER TEST CONDITIONS

I

STANDBY

I

MAIN

I

AUX

I

TOTAL

Total standby supply currents EM = EA = 0 (see Notes 2 and 3) Operational supply currents EM = 1, EA = 0 (see Note 3) Operational supply currents EM = 0, EA = 1 (see Note 3) Operational supply currents

NOTES: 2. VRN = VRA = VRF = V

3. For optimum standby and operational current consumption, the following condition should be be maintained: VDD ≤ V

DDA

digital interface

V

OH

V

OL

I

IH

I

IL

High-level output voltage Low-level output voltage High-level input current Low-level input current

+ I

CCP

DDA

EM = EA = 1 (see Note 3)

DDA

< VDD + 1.

PARAMETER TEST CONDITIONS

IOH = 2 mA VDD –0.5 V IOL = – 2 mA 0.5 V

MIN

TYP

MAX

7.0

1.5

7.5

200

UNIT

µA mA mA mA

MIN TYP MAX UNIT

10 µA 10 µA

charge pump currents (see Figure 1)

auxiliary charge pump

|I

| Output current PHA

PHA

∆I

PHA

|I

|

ÁÁÁ

PHA

∆I

PHA

proportional charge pump, normal mode, VRF = V

|I

PHP-NM

∆I |I

PHP-NM

ÁÁÁ

∆I

4

PHP-NM

|

PARAMETER

Relative output current variation PHA (see Figure 1)

Output current matching PHA (see Figure 1)

DDA

PARAMETER

Output current PHP Relative output current variation PHP (see Figure 1)

ББББББББББББББ

Output current matching PHP (see Figure 1)

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TEST CONDITIONS

V

= 0.5 V

PHA

БББББÁÁÁÁ

V

PHA

= 0.5 V

DDA

TEST CONDITIONS MIN

V

= 0.5 V

PHP

БББББ

V

PHP

= 0.5 V

DDA

MIN

200

400

TYP

250

2%

TYP

500

2%

Á

MAX

300

10%

Á

±50

MAX

600

10%

Á

±50

UNIT

µA

Á

µA

UNIT

µA

Á

µA

Á

LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER

charge pump currents (see Figure 1) (continued)

TRF2050

SLWS030D– JUNE 1996 – REVISED OCTOBER 1998

proportional charge pump, speed-up mode, VRF = V

PARAMETER TEST CONDITIONS MIN

|I

PHP-SM

∆I |I

PHP-SM

∆I

integral charge pump, speed-up mode, VRF = V

|

PHP-SM

ÁÁÁ

|

PHP-SM

Output current PHP V Relative output current variation PHP (See Figure 1)

ББББББББББББББ

Output current matching PHP (See Figure 1) V

DDA

PARAMETER TEST CONDITIONS

|I ∆I

|

PHI-SM

ÁÁÁ

|

PHI-SM

Output current PHI V Relative output current variation PHI (see Figure 1)

ББББББББББББББ

Output current matching PHI (see Figure 1) V

fractional compensation proportional charge pump, normal mode, V

PARAMETER TEST CONDITIONS

|I

PHP-F-NM

ÁÁÁ

Output current PHP vs fractional numerator

|

(see Note 4)

(see the section on speed-up mode operation)

DDA

TYP

PHP

= 0.5 V

DDA

2

Á

(see the section on speed-up mode operation)

MIN

TYP

V

PHP

= 0.5 V

PHI

DDA

= 0.5 V

DDA

= V

RN

DDA

, FNUM = 1

4.8

ÁÁÁ

MIN

TYP

ÁÁÁ

1.25

NOTE: 4. Fractional compensation current is proportional to the numerator content of the fractional accumulator (FNUM).

charge pump leakage currents, VRN = VRA = V

PARAMETER

I

PHP

I

PHI

I

PHA

Output current PHP Output current PHI Output current PHA

RF

= V

DDA

TEST CONDITIONS

V

= 0.5 V V V

PHP PHI PHA

= 0.5 V

DDA

MIN

TYP

±10 ±10 ±10

2.5 2%

6

2%

MAX

Á

±300

MAX

Á

±600

MAX

ÁÁÁ

MAX

10%

7.2 8%

UNIT

3

mA

Á

µA

UNIT

mA

Á

µA

UNIT

µA

UNIT

nA

ac electrical characteristics, VDD = V

main divider

PARAMETER TEST CONDITIONS

f

RFIN

V

ID_RFIN

RF input frequency Differential RF input power

50-W single-ended characteristic impedance; ac-coupled

CCP

= V

= 3.6 V, TA = 25°C (unless otherwise noted)

DDA

MIN

TYP

–20

MAX

1.2

UNIT

GHz

0

dBm

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5

TRF2050

Á

AUXIN

yqy( )

Á

Z

AUXIN

Auxiliary in ut im edance

Z

REFIN

Reference in ut im edance

LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER

SLWS030D– JUNE 1996 – REVISED OCTOBER 1998

ac electrical characteristics, VDD = V (continued)

auxiliary divider

PARAMETER TEST CONDITIONS

ÁÁÁ

f

AUXIN

ÁÁÁ

reference divider

f

REFIN

V

I_REFIN

Auxiliary input frequency (ac-coupled)

p

PARAMETER TEST CONDITIONS

Reference input frequency Reference input voltage ac-coupled

p

CCP

= V

= 3.6 V, TA = 25°C (unless otherwise noted)

DDA

PA = 0: V

= VDD = 3.6 V

DDA

V

I_AUXIN

V

I_AUXIN

PA = 0: V

= VDD = 4.8 V

DDA

V

I_AUXIN

PA = 1: V

= VDD = 3.6 V

DDA

V

I_AUXIN

PA = 1: V

= VDD = 4.8 V

DDA

ББББББББ

V

I_AUXIN

= 560 mVpp = 200 mVpp

= 200 mVpp

MIN

TYP

MAX

Á

125

Á

70

Á

ÁÁÁÁÁ

Á

110

Á

40

72

5

100

3

MIN

TYP

MAX

40

200

100

3

UNIT

Á

MHz

Á

MHz

Á

MHz

Á

MHz

Á

MHz

kΩ pF

UNIT

MHz

mVpp

kΩ pF

timing requirements, serial data interface (see Figure 2)

f

CLOCK

t

w_CLKHI

t

w_CLKLO

t

su_Data

t

h_Data

t

h_Strobe

t

su_Strobe

t

w_STRBHI

Clock frequency 10 MHz Clock high time pulse width, CLOCK high 30 ns

Clock low time pulse width, CLOCK low 30 ns Setup time, data valid before CLOCK↑ 30 ns Hold time, data valid after CLOCK↑ 30 ns Hold time, STROBE high before CLOCK↑ 30 ns

Setup time, STROBE lowafter CLOCK↑ 30 ns STROBE high time pulse width, STROBE high

MIN MAX UNIT

50 ns

6

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LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER

PARAMETER MEASUREMENT INFORMATION

charge-pump current output definitions

Current

I

2

∆ I

REL

OUT

I

1

I

SINK

∆ I

OUT

TRF2050

SLWS030D– JUNE 1996 – REVISED OCTOBER 1998

MATCH

I

SOURCE

∆ I

OUT

REL

V

1

I

2

I

1

V

2

Voltage

Figure 1. Charge-Pump Output Current Definitions

The relative output current variation is defined as the percent difference between charge-pump current output at two charge-pump output voltages and the mean charge-pump current output (see Figure 1):

D

I

OUT REL

Ť

I

OUT MEAN

+2

Ť

ǒ

I2–I

ǒ

Ť

I2)

Ǔ

1

×100%; with V1+

Ǔ

Ť

I

1

0.7 V, V2+

V

DDA

–0.8 V.

Output current matching is defined as the difference between charge-pump sinking current output and charge-pump sourcing current output at a given charge-pump output (see Figure 1).

∆I

OUT MATCH

= I

SINK

– I

SOURCE

; with V1 ≤ Voltage ≤ V2.

serial-data interface timing

DATA

t

su_Data

CLOCK

STROBE

Valid

D0

Change

t

h_Data

D1

t

w_CLKHI

D30

t

su_Strobe

D31

t

w_CLKLO

t

h_Strobe

t

w_STRBHI

V

H

V

L

V

H

V

L

V

H

V

L

Figure 2. Serial-Data Interface Timing

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7

TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER

SLWS030D– JUNE 1996 – REVISED OCTOBER 1998

TYPICAL CHARACTERISTICS

MAIN DIVIDER INPUT POWER

FREQUENCY AND SUPPLY VOLTAGE

0

TA = 25°C N = 4000

–10

–20

5.1 V

–30

3.6 V

–40

Main Divider Input Power – dBm

–50

–60

500

550

600

4.4 V

650

700

750

800

f – Frequency – MHz

Figure 3

vs

850

900

950

2.9 V

1000

1050

1100

1150

1200

1250

MAIN DIVIDER MINIMUM INPUT POWER

vs

FREQUENCY AND TEMPERATURE

0

V

= VDD = V

CCP

N = 4000

–10

–20

–30

–40

–50

Main Divider Minimum Input Power – dBm

–60

500

550

600

t = 25°C

650

700

f – Frequency – MHz

750

DDA

800

= 4.8 V

t = 85°C

850

900

950

Figure 4

1000

t = –40°C

1100

1050

1150

1200

1250

REFERENCE DIVIDER MINIMUM INPUT POWER

vs

FREQUENCY AND SUPPLY VOLTAGE

10

TA = 25°C

5

N = 100

0

–5

–10 –15

–20 –25

–30

–35

Reference Divider Minimum Input Power –dBm

–40

10 15 20 25 30 35 40

5.1 V

4.4 V

3.6 V

f – Frequency – MHz

Figure 5

45 50 55

REFERENCE DIVIDER MINIMUM INPUT POWER

vs

FREQUENCY AND TEMPERATURE

10

V

= VDD = V

CCP

NR = 100

5

0

–5

–10

–15 –20

t = 85°C

–25

–30 –35

Reference Divider Minimum Input Power – dBm

–40

10 20 30 40 50 60 70

t = –40°C

f – Frequency – MHz

DDA

= 4.8 V

t = 25°C

Figure 6

8

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TRF2050

LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER

SLWS030D– JUNE 1996 – REVISED OCTOBER 1998

TYPICAL CHARACTERISTICS

AUXILIARY DIVIDER MINIMUM INPUT POWER

vs

FREQUENCY AND SUPPLY VOLTAGE

5

TA = 25°C

0

PA = 1

–5

N = 100 –10 –15 –20

–25 –30 –35 –40

–45

Auxiliary Divider Minimum Input Power – dBm

–50

5.1 V

51525

10 20 30 40 50 60

f – Frequency – MHz

3.6 V

35 45 55 65

Figure 7

AUXILIARY DIVIDER MINIMUM INPUT POWER

vs

FREQUENCY AND SUPPLY VOLTAGE

5

TA = 25°C

0

PA = 0 NA = 100

–5 –10 –15

–20 –25 –30

–35 –40

Auxiliary Divider Minimum Input Power – dBm

–45 –50

5 50 100

3.6 V

25 75 125 175

f – Frequency – MHz

4.4 V

5.1 V

Figure 9

4.4 V

150 200

AUXILIARY DIVIDER MINIMUM INPUT POWER

vs

FREQUENCY AND TEMPERATURE

5

V

= VDD = V

CCP

0

PA = 1 N = 100

–5 –10 –15 –20 –25 –30 –35 –40 –45

Auxiliary Divider Minimum Input Power – dBm

–50

10 15 20 25 35 40 45

530

f – Frequency – MHz

DDA

= 4.8 V

t = –40°C

t = 85°C

50 55 60 65 70 75

Figure 8

AUXILIARY DIVIDER MINIMUM INPUT POWER

vs

FREQUENCY AND TEMPERATURE

5

V

= VDD = V

CCP

0

PA = 0 N = 100

–5

–10

–15 –20 –25

–30 –35

–40 –45

Auxiliary Divider Minimum Input Power – dBm

–50

25 50 100 150 175

5 75 125 200

= 4.8 V

DDA

t = –40°C

t = 85°C

t = 25°C

f – Frequency – MHz

Figure 10

t = 25°C

80

85

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9

TRF2050 LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER

SLWS030D– JUNE 1996 – REVISED OCTOBER 1998

TYPICAL CHARACTERISTICS

CH1 S

1 µFS 2: 37.43 Ω –160.98 Ω 1.0245 pF

11

965.000 000 MHz

2

1

3

START 500.000 MHz STOP 1 400.000 MHz

Figure 11. Typical RFIN Impedance (S11)

1: 89.063 Ω –272.88 Ω 500 MHz 3: 16.773 Ω –127.36 Ω

1.4 GHz

10

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TRF2050

LOW-VOLTAGE 1.2-GHz FRACTIONAL-N/INTEGER-N SYNTHESIZER

SLWS030D– JUNE 1996 – REVISED OCTOBER 1998

APPLICATION INFORMATION

6

M_VCO

1

MOD

VT

MVT

VDD

JP1

µ.1 F

C7

5

GND

2

R9

10 k

Lock

31

Test

VDD

C8

100 pF

R10

18

R11

R15

18

R12

4

MQE001

VCC OUT

3

VOSC1

C5

49.9

18

C26

C30

R14

30 k

R13

18 k

VDDA

C10

µ.1 F

VDD

TSETUPRFRN

201918171615141312

VDD

TSET

U1

CLK

DATA

123456789

DTA

CLK

C39

100 pF

J1

22 pF

1000 pF

F µ.1

LOCK/TEST

RF

LOCK

STRB

VSS

AGND

STRB

C9

VDD

VOSC3

C33

C34

MVT

C16

180 pF

R19

3.9 k C17

470 pF

R20

12 k

C18

1200 pF

9.1 k

VSSA

RA

VOSC2

µ.022 F

PHA 11

PHA

AUX

10

AUX

R16

110 k

J3

NDK_OSC

C21

TRF2050

R22

VDDA

PHP

PHI

RN

PHI

PHP

VDDA

REF

VCCP

RFIN

REF

VDD

RFIN

100 pF

µ1F

C38

+

µ.1 F

C11

C23

1000 pF

22 pF

3

OUT

VCC

TCXO

VCONT

GND

2

14

µ.039 F

C31

1000 pF

C31

22 pF

AVT

0

R18

R17

12 k

121110

GND

13141516

VCC GND GND

123

AUX1_VCO

VCO190–S

C16

DNP

C14

180 pF

C13

47 pF

R21

36 k

C24

18

R23

R24

OUT

GND

GNDVTGND

AVT

18

9

4

C19

220pF

GND

1800 pF

R25

49.9

R26

18

GND GND MOD GND

C43

220pF

5678

C20

J2

µ.1 F

C22

Figure 12. Evaluation Board Schematic (Part 1 of 2)

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11