Texas Instruments TRF2020PW Datasheet

TRF2020

SYNTHESIZER FOR GLOBAL SYSTEM

FOR MOBILE (GSM) CELLULAR TELEPHONES

SLWS020B – FEBRUAR Y 1995 – REVISED JANUAR Y 1998

D

Three Separate Loops: 1 UHF and 2 VHF

D

Operation to 1.2-GHz for Main Synthesizer

D

Operation to 250 MHz for Auxiliary
Synthesizers

D

Fast Lock-up Time

D

High-Speed Serial Data Bus

D

Low Power Consumption

D

Ideal for Global Systems for Mobile
Communications (GSM) Applications

description

The Texas Instruments (TI) TRF2020 is an

V

DD

CLOCK

DATA

STROBE

LD

V

SS

REF_IN

V

SSP

PDA2

SW2

V

DDP2

AUX2_IN

PW PACKAGE

(TOP VIEW)

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integrated high performance frequency synthe­sizer device. The TRF2020 consists of one main

1.2-GHz synthesizer and two auxiliary 250-MHz
synthesizers. Each synthesizer has an independent dual-modulus prescaler and separate powerdown modes.
These features provide maximum flexibility for the design of 900-MHz wireless systems.

The main synthesizer consists of a 32/33-modulus prescaler with an 1 1-bit counter, a phase-frequency detector ,
and a charge pump. The phase-frequency detector is referenced to an internal reference frequency that is
derived from an external TCXO signal. The phase-frequency detector is also provided with a dead-zone
compensation circuit that reduces synthesizer phase noise during locked conditions.

Each auxiliary synthesizer consists of an independent 8/9-modulus prescaler with an 11-bit counter, a
phase-frequency detector, and a charge pump. Similar to the main synthesizer, each auxiliary synthesizer’s
phase-frequency detector is referenced to an internal reference frequency that is derived from an external
TCXO signal.

AUX1_IN
V

DDP1

PDA1
SW1
RPA
V

DDA

SWM
PDM
V

SSA

RPM
V

DDPM

RF_IN

The external TCXO signal is prescaled by an 11-bit counter and then distributed to three independent
postscalers. Each postscaler provides a selectable, divide-by-1, -2, -4, or -8 function before the reference signal
is distributed to the associated synthesizer phase detector. The reference frequency prescaler and independent
postscalers are software programmable.

To achieve minimum lock-up time, each synthesizer contains a speed-up mode charge pump capable of
providing 2 mA output current and an analog switch that can change the loop-filter time constant. The duration
of the speed-up mode operations can be independently controlled with software.

The states of the three internal lock detectors are provided on a programmable, combinational logic output; each
synthesizer can be selected independently or ANDed together.

The device is programmed over a three-wire, synchronous, serial data bus (clock, data, strobe) with achievable
bit rates as high as 20 Mbits/sec. The data is partitioned into words in such a manner that static parameters may
be sent once during initialization, and dynamic parameters, such as frequency , may be sent as often as needed.

The TRF2020 is offered in a 24-pin plastic thin-shrink small-outline package (TSSOP) and is characterized for
free-air operation from –40°C to 85°C.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TI is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  1998, Texas Instruments Incorporated

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

TRF2020
SYNTHESIZER FOR GLOBAL SYSTEM
FOR MOBILE (GSM) CELLULAR TELEPHONES

SLWS020B – FEBRUAR Y 1995 – REVISED JANUAR Y 1998

functional block diagram

R

RF_IN

AUX1_IN

13

S

24

1/32, 33

Prescaler

1/8, 9

Prescaler

5-Bit

Counter

Control Logic

RAB

3-Bit

Counter

11-Bit

Counter

511

11-Bit

Counter

Phase

Detector

FR

2

Charge

Pump

Speed-Up

Counter

6

C

Lock

Detect

15

RPM

18

SWM

17

PDM

U

2

5

LD

21

SW1

AUX2_IN

V

DDPM

V

DDP1

V

DDP2
V

SSP

REF_IN

Control Logic

311

T

12

14
23
11
8

1/8, 9

Prescaler

L

M

N

2
2
2

SDE

3-Bit

Counter

Control Logic

THJ

Main Reference Select
AUX-1 Reference Select
AUX-2 Reference Select

11-Bit

Counter

311

÷ 1 ÷ 2 ÷ 4 ÷ 8

7

11-Bit Reference

Counter

11

P

Reference Postscaler Select

Auxiliary Current Ratio

Phase

Detector

S

Speed-Up

Counter

6

G

Phase

Detector

T

Reference Counter

Power Enable

Lock Detect Select

Test Mode

AUX-2 Synthesizer

AUX-1 Synthesizer

Auxiliary Speed-Up

Main Current Ratio

Main Synthesizer

Charge

Pump

Current

Reference

Speed-Up

Counter

2

K

Charge

Pump

2

K

6

G

Address
Decoder

Word-3

Word-2

Word-1

Word-0

22

16
19

20

10

9

1
6

4

PDA1

V

SSA

V

DDA

RPA

SW2

PDA2

V

DD

V

SS

STROBE

3

2

DATA

CLOCK

22-Bit Shift Register

2

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2 Bit

I/O

DESCRIPTION

TRF2020

SYNTHESIZER FOR GLOBAL SYSTEM

FOR MOBILE (GSM) CELLULAR TELEPHONES

SLWS020B – FEBRUAR Y 1995 – REVISED JANUAR Y 1998

Terminal Functions

TERMINAL

NAME NO.

AUX1_IN 24 I RF input auxiliary-1 synthesizer
AUX2_IN 12 I RF input auxiliary-2 synthesizer
CLOCK 2 I Clock input
DATA 3 I Data input
LD 5 O Lock detect output
PDA1 22 O Auxiliary-1 synthesizer phase detector output
PDA2 9 O Auxiliary-2 synthesizer phase detector output
PDM 17 O Main synthesizer phase detector output
REF_IN 7 I Reference input
RF_IN 13 I Main synthesizer RF input
RPA 20 I Reference current input for AUX-1 and AUX-2 charge pumps
RPM 15 I Reference current input for main charge pump
STROBE 4 I Strobe input
SWM 18 O Main analog switch output
SW1 21 O Auxiliary-1 analog switch output
SW2 10 O Auxiliary-2 analog switch output
V

DD

V

DDA

V

DDPM

V

DDP1

V

DDP2

V

SS

V

SSA

V

SSP

1 Digital supply voltage
19 Analog supply voltage
14 Main prescaler supply voltage
23 Auxiliary-1 prescaler supply voltage
11 Auxiliary-2 prescaler supply voltage

6 Digital ground
16 Analog ground

8 Prescaler ground

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage V
Supply voltage V
Voltage applied to any other pin, V
Power dissipation at or below T
Junction temperature, T
Ambient operating temperature, T
Storage temperature, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

–0.3 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DDP

V

–0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DD,

DDA

150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

J

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

STG

–0.3 V to VDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IN

= 25°C 300 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A

–40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

A

†

recommended operating conditions

MIN NOM MAX UNIT

V

DDA

VDD, V
T

A

T

J

DDP

Analog supply voltage 2.75 3 4.5 V
Digital supply voltage 2.75 3 3.6 V
Operating free-air temperature –40 25 85 °C
Junction temperature –30 105 °C

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3

TRF2020

ť

ť

ť ť
ť

ť

ť ť

SYNTHESIZER FOR GLOBAL SYSTEM
FOR MOBILE (GSM) CELLULAR TELEPHONES

SLWS020B – FEBRUAR Y 1995 – REVISED JANUAR Y 1998

electrical characteristics with V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

OPER

I

STDBY

I

DDPM

I

DDP1

I

DDP2

NOTES: 1. Operational supply currents measured with RF_IN = 1200 MHz, AUX1_IN = 250 MHz, AUX2_IN = 250 MHz, f

Operational supply current R = S = T = 1 (see Note 1) 11 13 mA
Maximum standby current R = S = T = 0 10 µA
Main synthesizer operational supply current R = 1, S = T = 0 (see Note 1) 6 8 mA
Auxiliary-1 synthesizer operational supply current R = 0, S = 1, T = 0 (see Note 1) 3.3 4.5 mA

Auxiliary-2 synthesizer operational supply current R = 0, S = 0, T = 1 (see Note 1) 3.3 4.5 mA

All loops are in lock condition and normal mode. Operational supply current = I

DDA

= 4.5 V , V

= VDD = 3 V, TA = 25°C (unless otherwise noted)

DDP

= I

OPER

DDA

+ I

DDP1

+ I

DDP2

digital interface characteristics

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Clock

V

IH

V

IL

I

IH

I

IL

V

OH

V

OL

High-level input voltage

Low-level input voltage

High-level input current

Low-level input current

High-level output voltage LD IOH = 1 mA VDD – 0.4 V
Low-level output voltage LD IOH = –2 mA 0.4 V

Data
Strobe
Clock
Data
Strobe
Clock
Data
Strobe
Clock
Data
Strobe

0.7 V

DD

0 0.3 V

0 1 µA

0 1 µA

REF_IN

+ I

V

DD

= 39.6 MHz.

+ I

DDPM

DD

DD

V

V

ac electrical characteristics with V

DDA

main loop, RF_IN

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f

RF_IN

P

RF_IN

f

COMP

Input signal frequency 2.75 ≤ V
Input sensitivity
Phase detector comparison 2.75 ≤ VDD ≤ 3.5 V 0 2 MHz

auxiliary loops, AUX1_IN and AUX2_IN

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f

AUX_IN

P

AUX_IN

f

AUX_

COMP

Input signal frequency 2.75 ≤ V
Input sensitivity

Phase detector comparison 2.75 ≤ VDD ≤ 3.5 V 0 2 MHz

= 4.5 V , V

= VDD = 3 V , TA = 25°C (unless otherwise noted)

DDP

≤ 3.5 V 1200 MHz

DDP

2.75 ≤ V
R

source

2.75 ≤ V
R

source

≤ 3.5 V,

DDP
= 50 Ω

≤ 3.5 V 250 MHz

DDP

≤ 3.5 V,

DDP
= 50 Ω

–20 0 dBm

–20 0 dBm

4

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Z

Input impedance

|I

|

Output current PDM

V

0.5 V

|I

|

Output current PDA1

V

V

Á

Á

Á

Á

|I

|

Output current PDA2

V

V

Á

Á

Á

Á

reference divider, REF_IN

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

f

REF_IN

V

REF_IN

REF_IN

charge pump characteristics

main charge pump output

PDM

D

I

PDM

|I

PDM

∆I

PDM

|I

SWM

†

RPM = RPA = 27 kΩ to V

auxiliary-1 charge pump output

PDA1

D

I

PDA1

ÁÁ

|I

PDA1

∆I

PDA1

|I

SW1

†

RPM = RPA = 27 kΩ to V

auxiliary-2 charge pump output

PDA2

D

I

PDA2

ÁÁ

|I

PDA2

∆I

PDA2

|I

SW2

†

RPM = RPA = 27 kΩ to V

Input signal frequency 2.75 ≤ V
Input sensitivity 0.3 V

p

p

Resistive 100 kΩ
Capacitive 3 pF

PARAMETER TEST CONDITIONS

p

Relative output current variation PDM (see Figure 1)

|

Output current matching (see Figure 1)

|

Analog switch output current SWM, speed-up mode V

, F = K = 10.

SSA

PARAMETER TEST CONDITIONS

p

Relative output current variation PDA1
(see Figure 1)

|

БББББББББББ

Output current matching (see Figure 1)

|

Analog switch output current SW1, speed-up mode V

, F = K = 10.

SSA

PARAMETER TEST CONDITIONS

p

Relative output current variation PDA2

БББББББББББ

(see Figure 1)

|

Output current matching (see Figure 1)

|

Analog switch output current SW2, speed-up mode V

, F = K = 10.

SSA

normal mode
speed-up mode

normal mode
speed-up mode

normal mode
speed-up mode

TRF2020

SYNTHESIZER FOR GLOBAL SYSTEM

FOR MOBILE (GSM) CELLULAR TELEPHONES

SLWS020B – FEBRUAR Y 1995 – REVISED JANUAR Y 1998

≤ 3.5 V 40 MHz

DDP

– 0.8 V

=

PDM

DDA

RPM 5% tolerance,
V

+ 0.5 ≤ V

SSA

V

PDM
SWM

PDA1

= 0.5 V

= 0.5 V

= 0.5

PDM

DDA

DDA

DDA

RPA 5% tolerance
V

+ 0.5 ≤ V

SSA

V

PDA1
SW1

PDA2

= 0.5 V

= 0.5 V

= 0.5

PDA1

DDA

DDA

DDA

RPA 5% tolerance
V

+ 0.5 ≤ V

SSA

V

PDA2
SW2

= 0.5 V

= 0.5 V

PDA2

DDA

DDA

≤ V

≤ V

≤ V

DDA

DDA

DDA

†

– 0.5

†

†

– 0.5

– 0.5

MIN

400

1.5

1.5

MIN

400

1.5

1.5

MIN

400

1.5

1.5

DDP

TYP

MAX

500

600

2

2

TYP

MAX

500

600

2

ÁÁÁ

2

TYP

MAX

500

600

2

ÁÁÁ

2

2.5

15

2.5

2.5

15

2.5

2.5

15

2.5

p–p

UNIT

µA

mA

%

8

%

mA

UNIT

µA

mA

%

Á

8

%

mA

UNIT

µA

mA

Á

%

8

%

mA

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

TRF2020

IOZDisabled output current

RPM

RPA

V

DDA

10

nA

Normal and s eed u modes

SYNTHESIZER FOR GLOBAL SYSTEM
FOR MOBILE (GSM) CELLULAR TELEPHONES

SLWS020B – FEBRUAR Y 1995 – REVISED JANUAR Y 1998

Current

I

2

∆ I

REL

OUT

I

1

∆ I

I

SINK

OUT

MATCH

I

SOURCE

∆ I

OUT

REL

V

1

I

2

I

1

V

2

Voltage

Figure 1. Charge-Pump Output Current Definitions

The relative output current variation is defined as the percent difference between charge-pump current output
at two charge-pump output voltages and the mean charge-pump current output:

D

I

OUT REL

Ť

I

OUT MEAN

+2

Ť

(

I

2–I1

|(

I2)

)

x 100%; with V1 = 0.5 V, V2 = V

)|

I

1

DDA

– 0.5 V.

Output current matching is defined as the difference in charge-pump sinking current output and charge-pump
sourcing current output at a given charge-pump output (see Figure 1).

∆I

OUT MATCH

= I

SINK

– I

SOURCE

; with V1 ≤ Voltage ≤ V2.

charge-pump leakage currents, charge pumps not active

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

PDM
PDA1

p

PDA2
SWM
SW1
SW2

VO = 0.5V

=

Normal and speed-up modes

DDA

=

,

,

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

t

s

t

TRF2020

SYNTHESIZER FOR GLOBAL SYSTEM

FOR MOBILE (GSM) CELLULAR TELEPHONES

SLWS020B – FEBRUAR Y 1995 – REVISED JANUAR Y 1998

serial interface timing requirements with V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

C

I

R

I

f

clock

tr, t

f

tw(High) Pulse duration, CLOCK high 20 ns
tw(Low) Pulse duration, CLOCK low 20 ns

u

h

t

w(pulse)

Input capacitance 10 pF
Input resistance 10 k Ω
CLOCK frequency 13 20 MHz
CLOCK input rise and fall time 8 ns

Data before CLOCK high 15 ns

Strobe before CLOCK high

Data after CLOCK high 15 ns
Strobe after CLOCK high 15 ns

Strobe pulse width

= 4.5 V, V

DDA

= V

DDP

Under continuous operation 15 ns
First power on or programmed

from standby mode

= 3.0 V, TA = 25°C

DD

10C

60 kΩ

REF_IN

ext_coupling

2



PARAMETER MEASUREMENT INFORMATION

The timing relationship between the TRF2020 Data, Clock, and Strobe registers is shown in Figure 2.

DATA

CLOCK

STROBE

Data

Valid

D0 D1 D22 D23

Data

Change

t

su

t

h

t

w(LOW)

Clock Enabled

Shift in Data

t

w(HIGH)

t

su

Clock Disabled

t

w(PULSE)

Store Data

t

h

– V
– V

– V
– V

– V
– V

µs

s

IH
IL

IH
IL

IH
IL

Figure 2. Serial Data Interface Timing

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

TRF2020
SYNTHESIZER FOR GLOBAL SYSTEM
FOR MOBILE (GSM) CELLULAR TELEPHONES

SLWS020B – FEBRUAR Y 1995 – REVISED JANUAR Y 1998

TYPICAL CHARACTERISTICS

MAIN DIVIDER INPUT POWER

FREQUENCY AND SUPPLY VOLTAGE

0

TA = 25°C

–10

–20

–30

IP – Input Power – dBm

–40

–50

500

600

700

800

vs.

900

1100

1000

1200

1300

1400

f – Frequency – MHz

Figure 3

2.75 V

1500

3.5 V

1600

1700

1800

1900

2000

MAIN DIVIDER MINIMUM INPUT POWER

FREQUENCY AND TEMPERATURE

0

V

= V

DDA

–10

–20

–30

–40

MIP – Minimum Input Power – dBm

–50

500

600

700

= VDD = 2.75 V

DDP

TA = –40°C

TA = 25°C

800

900

1100

1000

f – Frequency – MHz

Figure 4

vs.

1200

1300

TA = 85°C

1400

1500

1600

1700

1800

1900

2000

REFERENCE DIVIDER MINIMUM INPUT VOLTAGE

vs.

FREQUENCY AND SUPPLY VOLTAGE

0.12

PP

MIV – Minimum Input Voltage – V

TA = 25°C

0.1

0.08

2.75 V

0.06

3.5 V

0.04

0.02

0

f – Frequency – MHz

Figure 5

REFERENCE DIVIDER MINIMUM INPUT VOLTAGE

vs.

FREQUENCY AND TEMPERATURE

0.12
V

= V

DDA

PP

0.1

0.08

0.06

0.04

MIV – Minimum Input Voltage – V

0.02

0

34323028262422201816141210864

403836

= VDD = 2.75 V

DDP

TA = –40°C

TA = 25°C

f – Frequency – MHz

TA = 85°C

34323028262422201816141210864

403836

Figure 6

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TRF2020

SYNTHESIZER FOR GLOBAL SYSTEM

FOR MOBILE (GSM) CELLULAR TELEPHONES

SLWS020B – FEBRUAR Y 1995 – REVISED JANUAR Y 1998

TYPICAL CHARACTERISTICS

AUXILIARY-1 DIVIDER MINIMUM INPUT POWER

vs.

FREQUENCY AND SUPPLY VOLTAGE

0

TA = 25°C

–5

–10

–15

–20

–25

MIP – Minimum Input Power – dBm

–30

–35

f – Frequency – MHz

3.5 V

2.75 V

40035030025020015010050

Figure 7

AUXILIARY-2 DIVIDER MINIMUM INPUT POWER

vs.

FREQUENCY AND SUPPLY VOLTAGE

0

TA = 25°C

–5

AUXILIARY-1 DIVIDER MINIMUM INPUT POWER

vs.

FREQUENCY AND TEMPERATURE

0

V

= V

DDA

–5

–10

–15

–20

–25

MIP – Minimum Input Power – dBm

–30

500450

–35

= VDD = 2.75 V

DDP

TA = 85°C

f – Frequency – MHz

TA = –40°C

TA = 25°C

40035030025020015010050

500450

Figure 8

AUXILIARY-2 DIVIDER MINIMUM INPUT POWER

vs.

FREQUENCY AND SUPPLY VOLTAGE

0

V

–5

DDA

= V

= VDD = 2.75 V

DDP

–10

–15

–20

–25

–30

MIP – Minimum Input Power – dBm

–35

–40

f – Frequency – MHz

Figure 9

–10

–15

3.5 V

2.75 V

40035030025020015010050

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

500450

–20

–25

–30

MIP – Minimum Input Power – dBm

–35

–40

TA = –40°C

TA = 25°C

f – Frequency – MHz

Figure 10

TA = 85°C

40035030025020015010050

500450

9

TRF2020
SYNTHESIZER FOR GLOBAL SYSTEM
FOR MOBILE (GSM) CELLULAR TELEPHONES

SLWS020B – FEBRUAR Y 1995 – REVISED JANUAR Y 1998

TYPICAL CHARACTERISTICS

CH1 S111 U FS

START .030 000 MHz

Figure 11. Typical RF_IN Input Impedance (S11)

CH1 S111 U FS

1: 34.688 Ω
–133.84 Ω

1.1 GHz
2: 29.848 Ω
–116.08 Ω

1.2 GHz
3: 45.211 Ω
–182.11 Ω
900 MHz

1

3

2

STOP 2 000.000 000 MHz

1: 58.672 Ω
–403.83 Ω
250 MHz
2: 33.328 Ω
–189.11 Ω
500 MHz
3: 109.47 Ω
–1,0037 kΩ
100 MHz

10

START .030 000 MHz

Figure 12. Typical AUX1_IN Input Impedance (S11)

1

3

2

STOP 2 000.000 000 MHz

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TRF2020

SYNTHESIZER FOR GLOBAL SYSTEM

FOR MOBILE (GSM) CELLULAR TELEPHONES

SLWS020B – FEBRUAR Y 1995 – REVISED JANUAR Y 1998

CH1 S111 U FS

START .030 000 MHz

Figure 13. Typical AUX2_IN Input Impedance (S11)

CH1 S111 U FS

1: 57.031 Ω
–398.92 Ω
250 MHz
2: 32.273 Ω
–188.6 Ω
500 MHz
3: 107.63 Ω
–982.31 Ω
100 MHz

1

3

2

STOP 2 000.000 000 MHz

1: 803.75 Ω
–4.9245 κΩ

16.8 MHz
2: 218.88 Ω
–2.148 kΩ
40 MHz
3: 601 Ω
–4.1308 Ω

20.0 MHz

START .030 000 MHz

Figure 14. Typical REF_IN Input Impedance (S11)

3

1

2

STOP 2 000.000 000 MHz

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11

TRF2020
SYNTHESIZER FOR GLOBAL SYSTEM
FOR MOBILE (GSM) CELLULAR TELEPHONES

SLWS020B – FEBRUAR Y 1995 – REVISED JANUAR Y 1998

APPLICATION INFORMATION

C12

VOSC1

14

VCC

VT

2

R17

VCO190–S VARIL

33 k

R21

C59

20 k

0.1 µ F

22 pF

C14

C13

47 pF

820 pF

C19

4700 pF

C43

J2

18

18

220 pF

AUX1_VCO

R25

50

10

RF_OUT

MOD

6

C20

0.1 µ F

220pF

R26

18

R24

R23

C24

DDA

V

R43

24 k

C42

C63

22 pF

VOSC2

C16

68 pF

1

36 k

R19

C18

680pF

18 k

MVCO

7

C6

0.1 µ F

4700 pF

R20

R22

12 k

VT

MOD

3

5

C7

VCCRF_OUT

F

0.1 µ

R12

C61

OUT

VCO191–U VARIL

0.1 µ F

J1

C46

100 pF

18

18

R15

12 k

R18

VDD

C41

0.1 µ F

2423222120191817161514

PDA1

VDDP1

AUX_IN

U1

VDD

CLOCK

DATA

123456789

C39

0.1 µ F

1000 pF

22 pF

OUT

GND

VDD

22 nF

J4

NDK–OSC

VOSC2

C62

C60

REFIN

C23

3

VCC

TCXO

VCONT

2

14

RPA

SW1

VDDA

STROBELDVSS

C15

SWM

REF_IN

DNP

PDM

VSSA

VSSP

PDA2

R56

2

VT

AUX2_VCO

VCC

14

DD

V

RPM

VDDPM

SW2

VDDP2

101112

R54

R59

15 k

C57

51 k

C55

6

10

C64

22 pF

R9

24 k

C44

13

RF_IN

AUX2_IN

C40

12 k

330 pF

33 pF

C52

MOD

RF_OUT

VCO190–S VARIL

0.1 µ F

0.1 µ F

C58

µF

0.1

TRF2020

12 nF

C48

R49

R50

220 pF

18

R47

18

R46

18

18

R11

R10

50

C8

100 pF

50

C45

J3

220pF

12

C22

0.1 µF
VOSC1

C51

0.1 µF

Figure 15. Evaluation Board Schematic (Part 1 of 2)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TRF2020

SYNTHESIZER FOR GLOBAL SYSTEM

FOR MOBILE (GSM) CELLULAR TELEPHONES

SLWS020B – FEBRUAR Y 1995 – REVISED JANUAR Y 1998

APPLICATION INFORMATION

POWER

GND

DGND

FOR PC INTERFACE ONLY

POWER

HUB

1
14
2
15
3

16
4
17
5

18
6

19
7

20
8
21
9

22
10
23
11
24

12
25

13

+

C1

AGND

CLOCK1

DATA1

STROBE1

µ4.7 F

CLOCK

VR1

1

VT

2

VONCVO

3

VO

VO

4

ANC

LM317LBD

W

R5

CWCCW

1 k

VOPTO

8
7
6
5

R1

220

1.8 k

VDDA

R27

VDDA

+

C2

µ1F

R31

3.6 k

4N28S

VR2

1

VT

2

VONCVO

3

VO

4

ANC

LM317LBD

W

R6

1 k

U2

CWCCW

R28

1.8 k

CLOCK

VO

4N28S

8
7
6
5

R2
220

VDD

R32

3.6 k

+

VDD

C3

µ1F

R29

1.8 k

DATA

U3

1

VT

2

VONCVO

3

VO

4

ANC

R33

3.6 k

4N28S

VR3

LM317LBD

R7
820

VO

VDD

U4

8
7
6
5

R3

270

STROBE

VOSC1

2.7 k

+

R30

C4

µ1F

5

4

MOC8030

VR4

1

VT

2

VONCVO

3

VO

VO

4

ANC

LM317LBD

R8
390

U5

8
7
6
5

R13

270

6

VOSC2

+

C5

1

9

µ1F

R34

1.8 k

LOCK

STROBE

DATA

CLOCK

1

VT

2

VONCVO

3

VO

4

ANC

LM317LBD

VR5

R38
820

To U1/5

To U1/4
To U1/3

To U1/2

VO

8
7
6
5

R37

270

VOPTO

+

C25

µ1F

NOTE: Evaluation board dc supply circuitry

Figure 15. Evaluation Board Schematic (Part 2 of 2)

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TRF2020
SYNTHESIZER FOR GLOBAL SYSTEM
FOR MOBILE (GSM) CELLULAR TELEPHONES

SLWS020B – FEBRUAR Y 1995 – REVISED JANUAR Y 1998

APPLICATION INFORMATION

Table 1. TRF2020 Evaluation Board Parts List

DESIGNATORS DESCRIPTION VALUE QTY

C1 Capacitor 4.7 uF 1 “A” 3.2x1.6 Venkel TA025TCM series

C2, 3, 4, 5, 25 Capacitor 1 uF 5 “A” 3.2x1.6 Venkel TA025TCM series

C6, 19 Capacitor 4700 pF 2 0603 1.6x.08 Murata GRM39X7R series

C7, 12, 20, 22,

39, 40, 41, 42,

44, 51, 52, 61

C8, 46 Capacitor 100 pF 2 0603 1.6x.08 Murata GRM39X7R series

C13 Capacitor 820 pF 1 0603 1.6x.08 Murata GRM39X7R series
C14 Capacitor 47 pF 1 0603 1.6x.08 Murata GRM39X7R series
C15 Capacitor DNP 1 0603 1.6x.08
C16 Capacitor 68 pF 1 0603 1.6x.08 Murata GRM39X7R series
C18 Capacitor 680 pF 1 0603 1.6x.08 Murata GRM39X7R series
C23 Capacitor 22 nF 1 0603 1.6x.08 Murata GRM39X7R series

C24, 43, 45, 48 Capacitor 220 pF 4 0603 1.6x.08 Murata GRM39X7R series

C55 Capacitor 33 pF 1 0603 1.6x.08 Murata GRM39X7R series
C57 Capacitor 330 pF 1 0603 1.6x.08 Murata GRM39X7R series
C58 Capacitor 12 nF 1 0603 1.6x.08 Murata GRM39X7R series

C59, 60, 63, 64 Capacitor 22 pF 4 0603 1.6x.08 Murata GRM39X7R series

C62 Capacitor 1000 pF 1 0603 1.6x.08 Murata GRM39X7R series

R1, 2 Resistor 220 2 0603 1.6x.08 Panasonic ERJ–3GSYJ series

R3, 13, 37 Resistor 270 3 0603 1.6x.08 Panasonic ERJ–3GSYJ series

R5, 6 Resistor 1K 2 .25” square Bourns 3269W001 series

R7, 38 Resistor 820 2 0603 1.6x.08 Panasonic ERJ–3GSYJ series

R8 Resistor 390 1 0603 1.6x.08 Panasonic ERJ–3GSYJ series

R9, 43 Resistor 24K 2 0603 1.6x.08 Panasonic ERJ–3GSYJ series

R10, 25, 46 Resistor 50 3 0603 1.6x.08 Panasonic ERJ–3GSYJ series

R11, 12, 15, 23,

24, 26, 47, 49, 50

R17 Resistor 33K 1 0603 1.6x.08 Panasonic ERJ–3GSYJ series

R18, 20, 54 Resistor 12K 3 0603 1.6x.08 Panasonic ERJ–3GSYJ series

R19 Resistor 36K 1 0603 1.6x.08 Panasonic ERJ–3GSYJ series
R21 Resistor 20K 1 0603 1.6x.08 Panasonic ERJ–3GSYJ series
R22 Resistor 18K 1 0603 1.6x.08 Panasonic ERJ–3GSYJ series

R27, 28, 29, 34 Resistor 1.8K 4 0603 1.6x.08 Panasonic ERJ–3GSYJ series

R30 Resistor 2.7K 1 0603 1.6x.08 Panasonic ERJ–3GSYJ series

R31, 32, 33 Resistor 3.6K 3 0603 1.6x.08 Panasonic ERJ–3GSYJ series

R56 Resistor 51K 1 0603 1.6x.08 Panasonic ERJ–3GSYJ series
R59 Resistor 15K 1 0603 1.6x.08 Panasonic ERJ–3GSYJ series

U1 Integrated Circuit 1 TI TRF2020

U2, 3, 4 Optoelectronics 3 730C–04 Motorola 4N28S

Capacitor 0.1 uF 12 0603 1.6x.08 Murata GRM39X7R series

Resistor 18 9 0603 1.6x.08 Panasonic ERJ–3GSYJ series

SIZE
(mm)

MANUFACTURER

MANUFACTURER

P/N

14

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TRF2020

SYNTHESIZER FOR GLOBAL SYSTEM

FOR MOBILE (GSM) CELLULAR TELEPHONES

SLWS020B – FEBRUAR Y 1995 – REVISED JANUAR Y 1998

APPLICATION INFORMATION

Table 1. TRF2020 Evaluation Board Parts List (Continued)

DESIGNATORS DESCRIPTION VALUE QTY

U5 Optoelectronics 1 730C–04 Motorola MOC8030S

VR1, 2, 3, 4, 5 Voltage regulator 5 SO–8

P1 Para. connector 1 AMP 747238–4

J1, 2, 3, 4 SMA connector 4 EF Johnson 142–0701–831

MVCO

TCXO

AUX 1_VCO

AUX 2_VCO

DATA, VDDA,

VDD, LOCK,

POWER,

CLOCK, GND,

STROBE

Voltage-controlled

oscillator

Temp.-compensated

crystal oscillator

Voltage-controlled

oscillator

Voltage-controlled

oscillator

Test point 8 Components Corp. TP–105–01 series

ATTEN 10 dB
RL 0 dBm

VAVG 50

1 Vari-L Comp. VCO190–U

1 Toyocom TCO–980 series
1 Vari-L Comp. VCO190–S

1 Vari-L Comp. VCO190–S

10 dB/

SIZE

(mm)

MANUFACTURER

National

Semiconductor

MKR –85.33 dB
200 kHz

MANUFACTURER

LM317LBD

P/N

MKR
200 kHz

D

–85.33 dB

CENTER 1.1089992 GHz
RBW 3 kHz VBW 3 kHz

Figure 16. Typical Main Synthesizer Reference Spurs

SPAN 500 kHz

SWP 140 ms

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15

TRF2020
SYNTHESIZER FOR GLOBAL SYSTEM
FOR MOBILE (GSM) CELLULAR TELEPHONES

SLWS020B – FEBRUAR Y 1995 – REVISED JANUAR Y 1998

APPLICATION INFORMATION

ATTEN 10 dB
RL 0 dBm

MKR
4 kHz

D

–45.83 dB

CENTER 1.10899908 GHz
RBW 300 Hz VBW 300 Hz

VAVG 50

10 dB/

MKR –45.83 dB
4 kHz

SPAN 30 kHz
SWP 840 ms

Figure 17. Typical Main Synthesizer Close-in Noise at 4 kHz Offset

ATTEN 10 dB
RL 0 dBm

VAVG 50

10 dB/

MKR –51.50 dB
1 kHz

MKR
1 kHz

D

–51.50 dB

CENTER 1.10899918 GHz
RBW 100 Hz VBW 100 Hz

SPAN 10 kHz
SWP 802 ms

Figure 18. Typical Main Synthesizer Close-in Noise at 1 kHz Offset

16

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TRF2020

SYNTHESIZER FOR GLOBAL SYSTEM

FOR MOBILE (GSM) CELLULAR TELEPHONES

SLWS020B – FEBRUAR Y 1995 – REVISED JANUAR Y 1998

APPLICATION INFORMATION

TRACE A: Ch1 FM Main Time

LinMag

A Marker 652.3438 us 643.05 Hzpk

25

kHzpk

5

kHz

/div

–25

kHzpk

Start: 0 s Stop: 1.99609375 ms

Figure 19. Typical Main Synthesizer Transient Response For 35-MHz Jump From 1074 MHz to 1109 MHz

TRACE A: Ch1 FM Main Time

LinMag

A Marker 652.4375 us 893.77 Hzpk

25

kHzpk

5
kHz
/div

–25

kHzpk

Start: 0 s Stop: 1.99609375 ms

Figure 20. Typical Main Synthesizer Transient Response For 35-MHz Jump From 1109 MHz to 1074 MHz

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

17

TRF2020
SYNTHESIZER FOR GLOBAL SYSTEM
FOR MOBILE (GSM) CELLULAR TELEPHONES

SLWS020B – FEBRUAR Y 1995 – REVISED JANUAR Y 1998

APPLICATION INFORMATION

ATTEN 10 dB
RL 0 dBm

MKR
200 kHz

D

–88.17 dB

CENTER 248 MHz
RBW 3 kHz VBW 3 kHz

VAVG 50

10 dB/

MKR –88.17 dB
200 kHz

SPAN 500 kHz

SWP 140 ms

Figure 21. T ypical Auxiliary-1 Synthesizer Reference Spurs

ATTEN 10 dB
RL 0 dBm

MKR
200 kHz

D

–87.33 dB

VAVG 50

10 dB/

MKR –87.33 dB
200 kHz

18

CENTER 45.2000 MHz
RBW 3 kHz VBW 3 Hz

SPAN 500 kHz

SWP 140 ms

Figure 22. T ypical Auxiliary-2 Synthesizer Reference Spurs

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SYNTHESIZER FOR GLOBAL SYSTEM

FOR MOBILE (GSM) CELLULAR TELEPHONES

SLWS020B – FEBRUAR Y 1995 – REVISED JANUAR Y 1998

PRINCIPLES OF OPERATION

serial port operation

The TRF2020 device registers are manipulated via a synchronous serial data port. The timing relationships are
defined in Figure 2, in the parameter measurement information section. Four 24-bit words are clocked into
temporary holding registers with the least significant bit clocked first. The operation registers are loaded with
the new data residing in the temporary registers with the rising edge of the strobe input.

Each word can be written to the device independently . In this manner, only the words containing the information
required to change the current state of the device need to be written. T o fully program the device, the words are
written in the following order:

Word-1 Auxiliary-1 synthesizer
Word-2 Auxiliary-2 synthesizer
Word-3 Device
Word-0 Main synthesizer

Word-3 follows Word-1 and Word-2 because the frequency information for the auxiliary synthesizers is stored
in the operational registers with Word-1 and Word-2. It is necessary to load this frequency information before
the speed-up mode is activated by the auxiliary synthesizers’ power enable bits in Word-3.

TRF2020

Word-0 is written last because the speed-up mode for the main synthesizers is activated by the writing of
Word-0. If the main synthesizer is to be enabled, the power enable bit is written to the device in the preceding
Word-3.

The two most significant bits of each word contain the unique address of the word; the balance of the 22 bits
contains the data fields.

serial word format

23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDR DATA
0 0 C B A
0 1 G F E D
1 0 N M L K J H
1 1 V U T S R P

serial word format function

A: 5-bit NM2 data for main divider coefficient
B: 11-bit NM1 data for main divider coefficient
C: 6-bit data to control speed-up mode time of main synthesizer analog switch
D: 3-bit NM2 data for auxiliary-1 divider coefficient
E: 11-bit NM1 data for auxiliary-1 divider coefficient
F: 2-bit data to select main synthesizer speed-up/normal mode current ratio
G: 6-bit data to control speed-up mode time of auxiliary synthesizers
H: 3-bit NM2 data for auxiliary-2 divider coefficient

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19

TRF2020
SYNTHESIZER FOR GLOBAL SYSTEM
FOR MOBILE (GSM) CELLULAR TELEPHONES

SLWS020B – FEBRUAR Y 1995 – REVISED JANUAR Y 1998

PRINCIPLES OF OPERATION

serial word format function (continued)

J: 11-bit NM1 data for auxiliary-2 divider coefficient
K: 2-bit data to select auxiliary synthesizers speed-up/normal mode current ratio
L: 2-bit data to select reference postscaler for main synthesizer
M: 2-bit data to select reference postscaler for auxiliary-1
N: 2-bit data to select reference postscaler for auxiliary-2
P: 11-bit data for reference divider coefficient
R: 1-bit data to enable main synthesizer power. When 1, power is enabled
S: 1-bit data to enable auxiliary-1 synthesizer power. When 1, power is enabled
T: 1-bit data to enable auxiliary-2 synthesizer power. When 1, power is enabled
U: 2-bit data to select lock detect for main, auxiliary-1, and auxiliary-2 synthesizers
V: 6-bit data reserved for test purposes

main prescaler

Main prescaler and speed-up mode coefficients are defined by Word-0 at address 00.
The total division of the main synthesizer prescaler is defined as follows:
TOTAL
where 31 ≤ B < 2

†

The above equation defines a synthesizer operation where contiguous channels exist for all combinations of A and B. If B < 31, the synthesizer
no longer provides contiguous channels. In either case, it is important that the value assigned to A is never greater than the value assigned to
B.

= 32 × B + A,

MAIN

11†

, and 0 ≤ A < 25.

The speed-up mode total-time duration of the main synthesizer analog switch is defined by field C in Word-0
as follows:

TIME

MAIN–SP

+2 C

where 1 ≤ C < 2

6

, and f

1

,

f

ref

is the corresponding phase detector reference frequency.

ref

auxiliary-1 prescaler

Auxiliary-1 prescaler coefficients are defined by Word-1 at address 01. The total division of the auxiliary-1
synthesizer prescaler is defined as follows:

TOTAL
where 7 ≤ E < 2

‡

The above equation defines a synthesizer operation where contiguous channels exist for all combinations of D and E. If E < 7, the synthesizer
no longer provides contiguous channels. In either case, it is important that the value assigned to D is never greater than the value assigned to
E.

AUX–1

= 8 × E + D,

11‡

, and 0 ≤ D < 23.

20

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SYNTHESIZER FOR GLOBAL SYSTEM

FOR MOBILE (GSM) CELLULAR TELEPHONES

SLWS020B – FEBRUAR Y 1995 – REVISED JANUAR Y 1998

PRINCIPLES OF OPERATION

auxiliary-1 prescaler (continued)

The speed-up total-time duration of the auxiliary synthesizer boost charge pumps is defined as follows:

TRF2020

TIME

AUX–SP

+2 G

where 1 ≤ G < 2

6

, and f

1

,

f

ref

is the corresponding phase detector reference frequency.

ref

The speed-up mode of both auxiliary synthesizers is controlled by field G in Word-1, although each auxiliary
synthesizer has its own independent speed-up mode counter.

auxiliary-2 prescaler

Auxiliary-2 prescaler coefficients are defined by Word-2 at address 10.

The total division of the auxiliary-2 synthesizer prescaler is defined as follows:
TOTAL
where 7 ≤ J < 2

†

The above equation defines a synthesizer operation where contiguous channels exist for all combinations of H and J. If J < 7, the synthesizer
no longer provides contiguous channels. In either case, it is important that the value assigned to H is never greater than the value assigned to
J.

AUX–2

= 8 × J + H,

11†

, and 0 ≤ H < 23.

reference divider postscalers

Each synthesizer section is referenced to the main reference divider through a selectable divide-by-1, -2, -4,
or -8 postscaler (see the reference divider section below). Selection of the additional 1, 2, 4, or 8 division is
determined by the state of bits L, M, and N, as depicted in Word-2 as follows:

Additional Postscaler Division

N1, M1, OR L1 N0, M0, OR L0 ADDITIONAL DIVISION

0 0 1
0 1 2
1 0 4
1 1 8

reference divider

The reference divider coefficients are defined by Word-3 at address 1 1. The total division of the 1 1-bit reference
counter is defined as follows:

TOTAL

REF

where 1 ≤ P < 2

+

1

,

P

11

.

power enable

Each synthesizer section can be enabled/disabled by manipulation of fields R, S, and T of Word-3. The
appropriate synthesizer section is enabled if a logic one (1) is written to the appropriate field.

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21

TRF2020
SYNTHESIZER FOR GLOBAL SYSTEM
FOR MOBILE (GSM) CELLULAR TELEPHONES

SLWS020B – FEBRUAR Y 1995 – REVISED JANUAR Y 1998

PRINCIPLES OF OPERATION

lock detect (LD) selection

The phase-locked state of each synthesizer section is indicated by the logic state of the LD terminal. Each
synthesizer section can be selected individually or as an ANDed function by the manipulation of field U in Word-3
as follows:

Additional Postscaler Division

U1 U0 LOCK DETECT

0 0 MAIN
0 1 AUX-1
1 0 AUX-2
1 1 ANDed

The terms in the ANDed function are dependent on the power enable bit state of each synthesizer section. Only
if the synthesizer section is enabled is its term significant in the ANDed term of the lock detect output. This is
depicted in the following logic equation:

LD

U1 = U0 = 1

= (MAIN ) R)  (AUX1 ) S)  (AUX2 ) T) S (R + S+ T)

where R, S, and T are the power enable bits of Word-3.

test mode selection

Internal signals can be routed to the LD terminal by manipulating the test mode field V in Word-3 as shown in
Table 2.

Table 2. Test Mode Selection

V4 V3 V2 V1 V0 ROUTING TO LD TERMINAL

0 0 1 0 1 Main prescaler output
0 0 1 1 0 Main 11-bit counter output
0 0 1 1 1 Main 5-bit counter output
1 1 0 0 1 Main phase comparator down pulse output
1 1 0 1 0 Main phase comparator up pulse output
1 1 0 1 1 Main timer output
1 0 1 0 1 Auxiliary-1 prescaler output
1 0 1 1 0 Auxiliary-1 11-bit counter output
1 0 1 1 1 Auxiliary-1 3-bit counter output
0 1 1 0 1 Auxiliary-1 phase comparator down pulse output
0 1 1 1 0 Auxiliary-1 phase comparator up pulse output
0 1 1 1 1 Auxiliary-1 timer output
1 1 1 0 1 Auxiliary-2 prescaler output
1 1 1 1 0 Auxiliary-2 11-bit counter output
1 1 1 1 1 Auxiliary-2 3-bit counter output
1 0 0 0 1 Auxiliary-2 phase comparator down pulse output
1 0 0 1 0 Auxiliary-2 phase comparator up pulse output
1 0 0 1 1 Auxiliary-2 timer output
0 1 0 0 1 Main reference clock

22

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SYNTHESIZER FOR GLOBAL SYSTEM

FOR MOBILE (GSM) CELLULAR TELEPHONES

SLWS020B – FEBRUAR Y 1995 – REVISED JANUAR Y 1998

PRINCIPLES OF OPERATION

test mode selection (continued)

Table 2. Test Mode Selection (continued)

V4 V3 V2 V1 V0 ROUTING TO LD TERMINAL

0 1 0 1 0 Auxiliary-1 reference clock
0 1 0 1 1 Auxiliary-2 clock reference clock

NOTE: All other binary combinations of the test mode field V not shown above are reserved for future use.

Bit 5 in the V-word is used to select an external pulse mode. In the external pulse mode, the CMOS main and
subcounters are fed externally sourced clock pulses through pin 18 instead of from the prescaler inputs as
normally operated. This mode makes testing of the internal CMOS counters easy.

speed-up switching time

main synthesizer

When the main frequency synthesizer is changed in frequency, it may be desirable to increase the loop
bandwidth for a short time in order to achieve a faster lock time. An analog switch is provided that can vary the
topography of the loop filter in order to achieve a faster loop gain. When the frequency is changed (and speed-up
operation is desired), the following actions occur:

TRF2020

1. The new frequency coefficients for the main synthesizer are sent to the device over the serial bus.

2. After the data is clocked in, the strobe is toggled to high.

3. The positive edge of the strobe loads the new frequency into the main synthesizer prescaler (using the next
reference frequency pulse to synchronize).

4. With loading of the main synthesizer prescaler, the speed-up mode analog switch is activated to a
low-impedance state and the speed-up mode charge-pump boost circuit is activated.

5. The speed-up mode is maintained until the main synthesizer speed-up counter, previously loaded with field
C of Word-0, counts down to zero (0). The speed-up counter is clocked with the main synthesizer phase
detector reference frequency.

6. With the speed-up counter reaching a terminal count of zero (0), the speed-up analog switch reverts to the
normal mode high-impedance state, and the speed-up mode charge pump boost circuit is deactivated.

auxiliary synthesizer

Because the frequency of the auxiliary synthesizers is rarely changed during normal operation, speed-up mode
occurs during the independent power enable of the auxiliary synthesizer sections as controlled by fields S and
T in Word-3. Upon the transition of these 1-bit fields from a logic zero (0) to a logic one (1), the following actions
occur:

1. It is assumed that the proper frequency coefficients were written to the corresponding auxiliary synthesizer
prescaler field.

2. The power enable bit for the corresponding auxiliary synthesizer is changed from a zero (0) to a one (1).

3. The positive edge of the strobe loads Word-3, which contains the power enable bit fields (using the next
reference frequency pulse to synchronize).

4. With the loading of Word-3, the speed-up mode charge-pump boost circuit is activated and the analog
switch is activated to a low-impedance state.

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23

TRF2020
SYNTHESIZER FOR GLOBAL SYSTEM
FOR MOBILE (GSM) CELLULAR TELEPHONES

SLWS020B – FEBRUAR Y 1995 – REVISED JANUAR Y 1998

PRINCIPLES OF OPERATION

auxiliary synthesizer (continued)1234

5. The speed-up mode is maintained until the corresponding speed-up mode counter counts down to a
terminal count of zero. The speed-up counter is clocked with the corresponding auxiliary synthesizer phase
detector reference frequency.

6. With the corresponding speed-up counter reaching terminal count, the speed-up mode charge-pump boost
circuit and the analog switch for the corresponding auxiliary synthesizer revert to the normal mode,
high-impedance, off state.

using the speed-up mode

By changing the loop filter frequency response or the charge-pump output current, the overall closed-loop
response of the synthesizer system is altered. Without careful consideration, synthesizer lock-up times may
degrade rather than improve using the speed-up mode.

selecting current ratios

The normal mode and speed-up mode charge-pump current ratios for the main synthesizer and the auxiliary
synthesizers are selected using field F of Word-1 and field K of Word-2, respectively, as shown in Table 3.

Table 3. Charge-Pump Current Ratio Selection

F AND K FIELDS SPEED-UP/NORMAL MODE RATIO

11 8 (2 mA/0.25 mA)
10 4 (2 mA/0.5 mA)
01 2 (2 mA/ 1 mA)
00 1 (2 mA/2 mA)

external charge-pump scaling resistors

Two external scaling resistors are connected between RPM, RPA, and V
the speed-up mode charge-pump output current for the main synthesizer and the two auxiliary synthesizers as
defined in the following equations. The external scaling resistors in conjunction with the programmable
charge-pump current ratios determine speed-up and normal mode currents.

Main charge-pump speed-up mode current =

Auxiliary charge-pump speed-up mode current =

1

RPM

2mA 27 k

1

RPA

W(5kWv

2mA 27 k

(analog ground) in order to scale

SSA

RPM

vR),

W(5kWv

RPM

vR),

24

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TRF2020

SYNTHESIZER FOR GLOBAL SYSTEM

FOR MOBILE (GSM) CELLULAR TELEPHONES

SLWS020B – FEBRUAR Y 1995 – REVISED JANUAR Y 1998

MECHANICAL DATA

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PIN SHOWN

0,65

14

1

1,20 MAX

A

7

0,05 MIN

0,30
0,19

8

6,60

4,50
4,30

6,20

M

0,10

Seating Plane

0,10

0,15 NOM

Gage Plane

0,25

0°–8°

0,75
0,50

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

8

3,10

2,90

14

5,10

4,90

16

5,10

20

6,60

6,404,90

24

7,90

7,70

28

9,80

9,60

4040064/E 08/96

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

25

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