TEXAS INSTRUMENTS TPS65930-20 Technical data
TPS65930/TPS65920
Integrated Power Management
\Audio Codec (TPS65930 Only)
Silicon Revision 1.2
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SWCS037G
May 2008–Revised April 2011
TPS65930/TPS65920
SWCS037G–MAY 2008– REVISED APRIL 2011
www.ti.com
Contents
1 Introduction ........................................................................................................................ 9
1.1 Features .................................................................................................................... 10
1.2 TPS65920 and TPS65930 Device Block Diagrams ................................................................... 11
2 Terminal Description .......................................................................................................... 13
2.1 Ball Characteristics ........................................................................................................ 13
2.2 Signal Description ......................................................................................................... 17
3 Electrical Characteristics .................................................................................................... 23
3.1 Absolute Maximum Ratings .............................................................................................. 23
3.2 Minimum Voltages and Associated Currents .......................................................................... 23
3.3 Recommended Operating Conditions .................................................................................. 24
3.4 Digital I/O Electrical Characteristics ..................................................................................... 24
4 Power Module ................................................................................................................... 27
4.1 Power Providers ........................................................................................................... 28
4.1.1 VDD1 dc-dc Regulator ......................................................................................... 29
4.1.1.1 VDD1 dc-dc Regulator Characteristics .......................................................... 29
4.1.1.2 External Components and Application Schematics ........................................... 30
4.1.2 VDD2 dc-dc Regulator ......................................................................................... 32
4.1.2.1 VDD2 dc-dc Regulator Characteristics .......................................................... 32
4.1.2.2 External Components and Application Schematics ........................................... 33
4.1.3 VIO dc-dc Regulator ............................................................................................ 35
4.1.3.1 VIO dc-dc Regulator Characteristics ............................................................ 35
4.1.3.2 External Components and Application Schematics ........................................... 36
4.1.4 VDAC LDO Regulator .......................................................................................... 38
4.1.5 VPLL1 LDO Regulator ......................................................................................... 39
4.1.6 VMMC1 LDO Regulator ....................................................................................... 40
4.1.7 VAUX2 LDO Regulator ........................................................................................ 41
4.1.8 Output Load Conditions ........................................................................................ 42
4.1.9 Charge Pump ................................................................................................... 43
4.1.10 USB LDO Short-Circuit Protection Scheme ................................................................. 44
4.2 Power References ......................................................................................................... 45
4.3 Power Control .............................................................................................................. 45
4.3.1 Backup Battery Charger ....................................................................................... 45
4.3.2 Battery Monitoring and Threshold Detection ................................................................ 46
4.3.2.1 Power On/Power Off and Backup Conditions .................................................. 46
4.3.3 VRRTC LDO Regulator ........................................................................................ 46
4.4 Power Consumption ....................................................................................................... 47
4.5 Power Management ....................................................................................................... 49
4.5.1 Boot Modes ...................................................................................................... 49
4.5.2 Process Modes .................................................................................................. 49
4.5.2.1 MC021 Mode ....................................................................................... 49
4.5.3 Power-On Sequence ........................................................................................... 49
4.5.3.1 Timing Before Sequence_Start .................................................................. 49
4.5.3.2 Power-On Sequence .............................................................................. 51
4.5.3.3 Power On in Slave_C021 Mode ................................................................. 51
4.5.4 Power-Off Sequence ........................................................................................... 53
4.5.4.1 Power-Off Sequence .............................................................................. 53
2 Contents Copyright © 2008–2011, Texas Instruments Incorporated
TPS65930/TPS65920
www.ti.com
SWCS037G–MAY 2008– REVISED APRIL 2011
5 Real-Time Clock and Embedded Power Controller ................................................................. 54
5.1 RTC ......................................................................................................................... 54
5.1.1 Backup Battery .................................................................................................. 54
5.2 EPC ......................................................................................................................... 54
6 Audio/Voice Module (TPS65930 Device Only) ........................................................................ 55
6.1 Audio/Voice Downlink (RX) Module ..................................................................................... 55
6.1.1 Predriver for External Class-D Amplifier ..................................................................... 55
6.1.1.1 Predriver Output Characteristics ................................................................. 56
6.1.1.2 External Components and Application Schematics ........................................... 56
6.1.2 Vibrator H-Bridge ............................................................................................... 57
6.1.2.1 Vibrator H-Bridge Output Characteristics ....................................................... 57
6.1.2.2 External Components and Application Schematics ........................................... 57
6.1.3 Carkit Output .................................................................................................... 58
6.1.4 Digital Audio Filter Module .................................................................................... 59
6.1.5 Boost Stage ..................................................................................................... 59
6.2 Audio Uplink (TX) Module ................................................................................................ 61
6.2.1 Microphone Bias Module ...................................................................................... 61
6.2.1.1 Analog Microphone Bias Module Characteristics .............................................. 61
6.2.1.2 Silicon Microphone Module Characteristics .................................................... 63
6.2.2 FM Radio/Auxiliary Input ....................................................................................... 65
6.2.2.1 External Components ............................................................................. 65
6.2.3 Uplink Characteristics .......................................................................................... 65
6.2.4 Microphone Amplification Stage .............................................................................. 66
6.2.5 Carkit Input ...................................................................................................... 67
6.2.6 Digital Audio Filter Module .................................................................................... 68
7 USB Transceiver ............................................................................................................... 69
7.1 USB Transceiver ........................................................................................................... 69
7.1.1 Features ......................................................................................................... 69
7.1.2 HS USB Port Timing ........................................................................................... 70
7.1.3 USB-CEA Carkit Port Timing .................................................................................. 71
7.1.4 PHY Electrical Characteristics ................................................................................ 73
7.1.4.1 HS Differential Receiver ........................................................................... 73
7.1.4.2 HS Differential Transmitter ........................................................................ 74
7.1.4.3 CEA/UART Driver .................................................................................. 75
7.1.4.4 Pullup/Pulldown Resistors ........................................................................ 75
7.1.5 OTG Electrical Characteristics ................................................................................ 75
7.1.5.1 OTG VBUS Electrical Characteristics ........................................................... 76
7.1.5.2 OTG ID Electrical Characteristics ................................................................ 76
8 MADC ............................................................................................................................... 78
8.1 General Description ....................................................................................................... 78
8.2 MADC Electrical Characteristics ......................................................................................... 78
8.3 Channel Voltage Input Range ........................................................................................... 79
8.3.1 Sequence Conversion Time (Real-Time or Nonaborted Asynchronous) ................................ 79
9 LED Drivers ...................................................................................................................... 81
9.1 General Description ....................................................................................................... 81
10 Keyboard .......................................................................................................................... 82
10.1 Keyboard Connection ..................................................................................................... 82
11 Clock Specifications .......................................................................................................... 83
Copyright © 2008–2011, Texas Instruments Incorporated Contents 3
TPS65930/TPS65920
SWCS037G–MAY 2008– REVISED APRIL 2011
11.1 Clock Features ............................................................................................................. 83
11.2 Input Clock Specifications ................................................................................................ 84
11.2.1 Clock Source Requirements .................................................................................. 84
11.2.2 HFCLKIN ......................................................................................................... 84
11.2.3 32-kHz Input Clock ............................................................................................. 86
11.2.3.1 External Crystal Description ...................................................................... 87
11.2.3.2 External Clock Description ........................................................................ 88
11.3 Output Clock Specifications .............................................................................................. 91
11.3.1 32KCLKOUT Output Clock .................................................................................... 91
11.3.2 HFCLKOUT Output Clock ..................................................................................... 92
11.3.3 Output Clock Stabilization Time .............................................................................. 93
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12 Timing Requirements and Switching Characteristics ............................................................. 94
12.1 Timing Parameters ........................................................................................................ 94
12.2 Target Frequencies ........................................................................................................ 95
12.3 I
12.4 Audio Interface: TDM/I2S Protocol ...................................................................................... 97
12.5 JTAG Interfaces .......................................................................................................... 101
2
C Timing .................................................................................................................. 96
12.4.1 I2S Right- and Left-Justified Data Format ................................................................... 98
12.4.2 TDM Data Format ............................................................................................. 100
13 Debouncing Time ............................................................................................................. 103
14 External Components ....................................................................................................... 104
15 TPS65920/TPS65930 Package ............................................................................................ 107
15.1 TPS65920/TPS65930 Standard Package Symbols ................................................................. 107
15.2 Package Thermal Resistance Characteristics ....................................................................... 107
15.3 Mechanical Data ......................................................................................................... 108
15.4 ESD Specifications ...................................................................................................... 109
16 Glossary ......................................................................................................................... 110
4 Contents Copyright © 2008–2011, Texas Instruments Incorporated
TPS65930/TPS65920
www.ti.com
SWCS037G–MAY 2008– REVISED APRIL 2011
List of Figures
1-1 TPS65920 Block Diagram....................................................................................................... 12
1-2 TPS65930 Block Diagram....................................................................................................... 12
2-1 PBGA Bottom View .............................................................................................................. 13
4-1 Power Provider Block Diagram................................................................................................. 27
4-2 VDD1 dc-dc Regulator Efficiency .............................................................................................. 30
4-3 VDD1 dc-dc Application Schematic............................................................................................ 31
4-4 VDD2 dc-dc Regulator Efficiency .............................................................................................. 33
4-5 VDD2 dc-dc Application Schematic............................................................................................ 34
4-6 VIO dc-dc Regulator Efficiency................................................................................................. 36
4-7 VIO dc-dc Application Schematic .............................................................................................. 37
4-8 Timing Before Sequence Start ................................................................................................. 50
4-9 Timings–Power On in OMAP3 Mode.......................................................................................... 51
4-10 Timings—Power On in Slave_C021 Mode.................................................................................... 52
4-11 Power-Off Sequence in Master Modes ....................................................................................... 53
6-1 Audio/Voice Module Block Diagram ........................................................................................... 55
6-2 Predriver for External Class D.................................................................................................. 57
6-3 Vibrator H-Bridge................................................................................................................. 58
6-4 Carkit Output Downlink Path Characteristics................................................................................. 58
6-5 Digital Audio Filter Downlink Path Characteristics........................................................................... 59
6-6 Analog Microphone Pseudodifferential ........................................................................................ 62
6-7 Analog Microphone Differential................................................................................................. 63
6-8 Silicon Microphone ............................................................................................................... 64
6-9 Audio Auxiliary Input ............................................................................................................. 65
6-10 Uplink Amplifier................................................................................................................... 65
6-11 Carkit Input Uplink Path Characteristics ...................................................................................... 67
6-12 Digital Audio Filter Uplink Path Characteristics .............................................................................. 68
7-1 USB 2.0 PHY Block Diagram................................................................................................... 69
7-2 USB System Application Schematic........................................................................................... 70
7-3 HS-USB Interface—Transmit and Receive Modes (ULPI 8-bit)............................................................ 71
7-4 USB-CEA Carkit UART Data Flow............................................................................................. 72
7-5 USB-CEA Carkit UART Timings................................................................................................ 73
8-1 Conversion Sequence General Timing Diagram............................................................................. 80
9-1 LED Driver Block Diagram ...................................................................................................... 81
10-1 Keyboard Connection............................................................................................................ 82
11-1 Clock Overview................................................................................................................... 83
11-2 HFCLKIN Clock Distribution .................................................................................................... 84
11-3 Example of Wired-OR Clock Request ......................................................................................... 85
11-4 HFCLKIN Squared Input Clock................................................................................................. 86
11-5 32-kHz Oscillator Block Diagram In Master Mode With Crystal............................................................ 87
11-6 32-kHz Crystal Input ............................................................................................................. 88
11-7 32-kHz Oscillator Block Diagram Without Crystal Option 1................................................................. 89
11-8 32-kHz Oscillator Block Diagram Without Crystal Option 2................................................................. 90
11-9 32-kHz Oscillator in Bypass Mode Block Diagram Without Crystal Option 3 ............................................ 90
11-10 32-kHz Square- or Sine-Wave Input Clock ................................................................................... 91
11-11 32.768-kHz Clock Output Block Diagram ..................................................................................... 91
11-12 32KCLKOUT Output Clock...................................................................................................... 92
11-13 HFCLKOUT Output Clock....................................................................................................... 93
Copyright © 2008–2011, Texas Instruments Incorporated List of Figures 5
TPS65930/TPS65920
SWCS037G–MAY 2008– REVISED APRIL 2011
www.ti.com
11-14 32KCLKOUT and HFCLKOUT Clock Stabilization Time.................................................................... 93
11-15 HFCLKOUT Behavior ........................................................................................................... 93
12-1 I
2
C Interface—Transmit and Receive in Slave Mode........................................................................ 96
12-2 I2S Interface—I2S Master ModeI .............................................................................................. 98
12-3 I2S Interface—I2S Slave Mode................................................................................................. 98
12-4 TDM Interface—TDM Master Mode.......................................................................................... 100
12-5 JTAG Interface Timing ......................................................................................................... 102
13-1 Debouncing Sequence Chronogram Example.............................................................................. 103
15-1 Printed Device Reference ..................................................................................................... 107
15-2 TPS65920/TPS65930 Mechanical Package Bottom View ................................................................ 108
15-3 Ball Size.......................................................................................................................... 108
6 List of Figures Copyright © 2008–2011, Texas Instruments Incorporated
TPS65930/TPS65920
www.ti.com
SWCS037G–MAY 2008– REVISED APRIL 2011
List of Tables
2-1 Ball Characteristics............................................................................................................... 13
2-2 Signal Description ................................................................................................................ 17
3-1 Absolute Maximum Ratings..................................................................................................... 23
3-2 VBAT Minimum Required Per VBAT Ball and Associated Maximum Current ........................................... 23
3-3 Recommended Operating Maximum Ratings ................................................................................ 24
3-4 Digital I/O Electrical Characteristics ........................................................................................... 24
4-1 Summary of the Power Providers.............................................................................................. 28
4-2 Part Names With Corresponding VDD1 Current Support................................................................... 29
4-3 VDD1 dc-dc Regulator Characteristics........................................................................................ 29
4-4 VDD2 dc-dc Regulator Characteristics........................................................................................ 32
4-5 VIO dc-dc Regulator Characteristics........................................................................................... 35
4-6 VDAC LDO Regulator Characteristics......................................................................................... 38
4-7 VPLL1 LDO Regulator Characteristics ........................................................................................ 39
4-8 VMMC1 LDO Regulator Characteristics....................................................................................... 40
4-9 VAUX2 LDO Regulator Characteristics ....................................................................................... 41
4-10 Output Load Conditions ......................................................................................................... 42
4-11 Charge Pump Output Load Conditions........................................................................................ 43
4-12 Voltage Reference Characteristics............................................................................................. 45
4-13 Backup Battery Charger Characteristics ...................................................................................... 45
4-14 Battery Threshold Levels........................................................................................................ 46
4-15 VRRTC LDO Regulator Characteristics....................................................................................... 46
4-16 Power Consumption ............................................................................................................. 47
4-17 Regulator State Depending on Use Case..................................................................................... 48
4-18 BOOT Mode Description ........................................................................................................ 49
4-19 MC021 Mode...................................................................................................................... 49
5-1 System States .................................................................................................................... 54
6-1 Predriver Output Characteristics ............................................................................................... 56
6-2 Vibrator H-Bridge Output Characteristics ..................................................................................... 57
6-3 USB-CEA Carkit Audio Downlink Electrical Characteristics................................................................ 58
6-4 Digital Audio Filter RX Electrical Characteristics............................................................................. 59
6-5 Boost Electrical Characteristics Versus FSFrequency (F
6-6 Boost Electrical Characteristics Versus FSFrequency (F
6-7 Analog Microphone Bias Module Characteristics With Bias Resistor ..................................................... 61
6-8 Analog Microphone Bias Module Characteristics With Bias Resistor ..................................................... 61
6-9 Silicon Microphone Module Characteristics................................................................................... 64
6-10 Uplink Characteristics............................................................................................................ 65
6-11 USB-CEA Carkit Audio Uplink Electrical Characteristics.................................................................... 67
6-12 Digital Audio Filter TX Electrical Characteristics ............................................................................. 68
7-1 HS-USB Interface Timing Requirements...................................................................................... 71
7-2 HS-USB Interface Switching Requirements .................................................................................. 71
7-3 USB-CEA Carkit Interface Timing Parameters............................................................................... 72
7-4 USB-CEA Carkit UART Timings................................................................................................ 73
7-5 HS Differential Receiver......................................................................................................... 74
7-6 HS Differential Transmitter...................................................................................................... 74
7-7 CEA/UART Driver ................................................................................................................ 75
7-8 Pullup/Pulldown Resistors....................................................................................................... 75
7-9 OTG VBUS Electrical Characteristics ......................................................................................... 76
Copyright © 2008–2011, Texas Instruments Incorporated List of Tables 7
≤ 22.05 kHz) ................................................. 60
S
≥ 24 kHz)..................................................... 60
S
TPS65930/TPS65920
SWCS037G–MAY 2008– REVISED APRIL 2011
www.ti.com
7-10 OTG ID Electrical Characteristics.............................................................................................. 76
8-1 MADC Electrical Characteristics ............................................................................................... 78
8-2 Analog Input Voltage Range.................................................................................................... 79
8-3 Sequence Conversion Timing Characteristics................................................................................ 79
9-1 LED Driver Electrical Characteristics .......................................................................................... 81
11-1 TPS65920/TPS65930 Input Clock Source Requirements .................................................................. 84
11-2 HFCLKIN Input Clock Electrical Characteristics ............................................................................. 86
11-3 HFCLKIN Square Input Clock Timing Requirements with Slicer in Bypass.............................................. 86
11-4 Crystal Electrical Characteristics............................................................................................... 87
11-5 Base Oscillator Switching Characteristics..................................................................................... 88
11-6 32-kHz Crystal Input Clock Timing Requirements ........................................................................... 88
11-7 32-kHz Input Square- or Sine-Wave Clock Source Electrical Characteristics............................................ 90
11-8 32-kHz Square-Wave Input Clock Source Timing Requirements.......................................................... 90
11-9 32KCLKOUT Output Clock Electrical Characteristics ....................................................................... 92
11-10 32KCLKOUT Output Clock Switching Characteristics....................................................................... 92
11-11 HFCLKOUT Output Clock Electrical Characteristics ........................................................................ 92
11-12 HFCLKOUT Output Clock Switching Characteristics........................................................................ 92
12-1 Timing Parameters............................................................................................................... 94
12-2 TPS65920/TPS65930 Interface Target Frequencies........................................................................ 95
12-3 I
12-4 I
2
C Interface—Timing Requirements .......................................................................................... 96
2
C Interface—Switching Requirements ...................................................................................... 97
12-5 I2S Interface—Timing Requirements.......................................................................................... 99
12-6 I2S Interface—Switching Characteristics...................................................................................... 99
12-7 TDM Interface Master Mode—Timing Requirements ...................................................................... 101
12-8 TDM Interface Master Mode—Switching Characteristics ................................................................. 101
12-9 JTAG Interface—Timing Requirements...................................................................................... 102
12-10 JTAG Interface—Switching Characteristics ................................................................................. 102
13-1 Debouncing...................................................................................................................... 103
14-1 TPS65920/TPS65930 External Components ............................................................................... 104
15-1 TPS65920/TPS65930 Nomenclature Description .......................................................................... 107
15-2 TPS65920 Thermal Resistance Characteristics............................................................................ 107
15-3 TPS65930 Thermal Resistance Characteristics............................................................................ 107
8 List of Tables Copyright © 2008–2011, Texas Instruments Incorporated
TPS65930/TPS65920
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1 Introduction
The TPS65920/TPS65930 devices are power-management ICs for OMAP™ and other mobile
applications. The devices include power-management, a universal serial bus (USB) high-speed (HS)
transceiver, light -emitting diode (LED) drivers, an analog-to-digital converter (ADC), a real-time clock
(RTC), and embedded power control (EPC). In addition, the TPS65930 includes a full audio codec with
two digital-to-analog converters (DACs) and two ADCs to implement dual voice channels, and a stereo
downlink channel that can play all standard audio sample rates through a multiple format inter-integrated
sound (I2S™)/time division multiplexing (TDM) interface.
These optimized devices support the power and peripheral requirements of the OMAP application
processors. The power portion of the devices contains three buck converters, two controllable by a
dedicated SmartReflex™ class-3 interface, multiple low dropout (LDO) regulators, an EPC to manage the
power sequencing requirements of OMAP, and an RTC and backup module. The RTC can be powered by
a backup battery when the main supply is not present, and the devices include a coin-cell charger to
recharge the backup battery as needed.
The USB module provides a HS 2.0 OTG transceiver suitable for direct connection to the OMAP UTMI+
low pin interface (ULPI), with an integrated charge pump and full support for the carkit CEA-936A
specification. An ADC is provided for monitoring signals, such as supply voltage, entering the device, and
two additional external ADC inputs are provided for system use.
SWCS037G–MAY 2008– REVISED APRIL 2011
Integrated Power Management
\Audio Codec (TPS65930 Only)
Check for Samples: TPS65930/TPS65920
The devices provide driver circuitry to power two LED circuits that can illuminate a panel or provide user
indicators. The drivers also provide pulse width modulation (PWM) circuits to control the illumination levels
of the LEDs. A keypad interface implements a built-in scanning algorithm to decode hardware-based key
presses and reduce software use, with multiple additional general-purpose input/output devices (GPIOs)
that can be used as interrupts when configured as inputs.
This TPS65920/TPS65930 data manual presents the electrical and mechanical specifications for the
TPS65920 and TPS65930 devices . It covers the following topics:
• TPS65920/TPS65930 terminals: Assignment, multiplexing, electrical characteristics, and functional
description (see Section 2, Terminal Description)
• Electrical characteristic requirements: Maximum and recommended operating conditions, digital
input/output (I/O) characteristics (see Section 3, Electrical Characteristics)
• Power module: Power provider, power references, power control, power consumption, and power
management, with the on and off sequence (see Section 4, Power Module)
• RTC and EPC (see Section 5, Real-Time Clock and Embedded Power Controller)
• Audio/voice module (TPS65930 device only): Electrical characteristics and application schematics for
the downlink and uplink paths (see Section 6, Audio/Voice Module (TPS65930 Device Only))
• Various modules: USB transceiver, monitoring analog-to-digital converter (MADC), LED drivers, and
keyboard (see Section 8, MADC, Section 9, LED Driver, and Section 10, Keyboard)
• Clock specifications: Clock slicer; input and output clocks (see Section 11, Clock Specifications)
• Timing requirements and switching characteristics (ac timings) of the interfaces (see Section 12,
Timing Requirements and Switching Characteristics)
• Debouncing time (see Section 13, Debouncing Time)
• External components for the application schematics (see Section 14, External Components)
• Thermal resistance characteristics, device nomenclature, and mechanical data about the available
packaging (see Section 15, TPS65920/TPS65930 Package )
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2008–2011, Texas Instruments Incorporated
TPS65930/TPS65920
SWCS037G–MAY 2008– REVISED APRIL 2011
•
Glossary of acronyms and abbreviations used in this data manual (see Section 16, Glossary)
1
1.1 Features
The TPS65930 and TPS65920 devices offer the following features:
• Power:
– Three efficient stepdown converters
– Four external linear LDOs for clocks and peripherals
– SmartReflex dynamic voltage management
• Audio (TPS65930 device only):
– Differential input main microphones
– Mono auxiliary/FM input
– External predrivers for class D (stereo)
– TDM interface
– Automatic level control (ALC)
– Digital and analog mixing
– 16-bit linear audio stereo DAC (96, 48, 44.1, and 32 kHz and derivatives)
– 16-bit linear audio stereo ADC (48, 44.1, and 32 kHz and derivatives)
– Carkit
• USB:
– USB 2.0 on-the-go (OTG)-compliant HS transceivers
– 12-bit universal transceiver macro interface ULPI
– USB power supply (5-V charge pump for VBUS)
– Consumer Electronics Association (CEA)-2011: OTG transceiver interface specification
– CEA-936A: Mini-USB analog carkit specification
• Additional Features:
– LED driver circuit for two external LEDs
– Two external 10-bit MADC inputs
– Real-time clock (RTC) and retention modules
– HS I2C serial control
– Thermal shutdown and hot-die detection
– Keypad Interface (up to 6 × 6)
– External vibrator control
– 15 GPIOs
– 0.65 mm pitch, 139 pin, 10 × 10 mm package
• Charger:
– Backup battery charger
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1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
10 Introduction Copyright © 2008–2011, Texas Instruments Incorporated
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Powercontrol
(BBS-backup
VRRTC-UVLO)
Powerreferences
(Vref-Iref-bandgap)
Powerprovider
(LDOs-DcDcs)
RTC
32kHz
Clockslicer Rcoscillator
Thermalmonitor
system
Powersubchip(A-D)
Poweranalog
Powerdigital
Auxiliarysubchip(A-D)
Interfacesubchip(D)
MADCTOP
MADC
digital
state-machine
MADCanalog
(SAR-Vref)
USBsubchip(A-D)
SIH
CardDet1
CardDet2
GPIO
PIH
TAP OCP
SIH
RTC RFIDEN
PMCmaster
PMCslave
LEDdigital
LEDanalog
LEDTOP
Vibrator
control(D)
Keypad
(D)
USB
digital
(ULPI
regist
ers,
interr
upts,
TPS65920
Shundan
Smart
Reflex
OTG
module
USB2.0
transceiver
USBpower
supply
Digitalsignal(s)
Analogsignal(s)
Clock
generator
LedSync
ULPI(12)
UART(2)
BERCLK
BERDATA
Clocks
OCP
SIH_INT
TAP
OCP
Clocks
SIH_INT
TAP
I2C A pad
I2CBpad
ClkIn/Out
GPIO pad
OCP SR
SIH_INT
OCP
TAP
Clocks
SIH_INT
OCP
Clocks
TAP
TPS65930/TPS65920
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1.2 TPS65920 and TPS65930 Device Block Diagrams
SWCS037G–MAY 2008– REVISED APRIL 2011
Figure 1-1. TPS65920 Block Diagram
Copyright © 2008–2011, Texas Instruments Incorporated Introduction 11
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Powercontrol
(BBS-backup
VRRTC-UVLO)
Powerreferences
(Vref-Iref-bandgap)
Powerprovider
(LDOs-DcDcs)
RTC
32kHz
Clockslicer Rcoscillator
Thermalmonitor
system
Powersubchip(A-D)
Poweranalog
Powerdigital
Auxiliarysubchip(A-D)
Audiosubchip(A-D)
Interfacesubchip(D)
Audio
PLL
AUDIOdigital
TDM/I2S
interface
Audiofilters
(RXand TXpaths)
and
vibratorcontrol
AUDIO
analog
Wrapper
digital
Analogand
micbias
AudioRXamplifiers
Micamplifiers
Analogvolumecontrol
D/A converters
A/Dconverters
Differentialvibrator
Carkitpreamplifiers
MADCTOP
MADC
digital
state-machine
MADCanalog
(SAR-Vref)
USBsubchip(A-D)
SIH
CardDet1
CardDet2
GPIO
PIH
TAP OCP
SIH
RTC
RFIDEN
PMCmaster
PMCslave
LEDdigital
LEDanalog
LEDTOP
Vibrator
control(D)
Keypad
(D)
USB
digital
ULPI/
registers
interrupts
CEA and
carkit
TPS65930
Shundan
Smart
Reflex
Analog
carkit
interfaces
OTG
module
USB2.0
transceiver
USBpower
supply
Clocks
Digitalsignal(s)
Analogsignal(s)
Clock
generator
TDM
LedSync
ULPI(12)
UART(2)
BERCLK
BERDATA
Clocks
OCP
SIH_INT
TAP
OCP
Clocks
SIH_INT
TAP
I2C A pad
I2CBpad
ClkIn/
Out
GPIO
pad
037-002
OCP SR
SIH_INT
OCP
TAP
Clocks
TAP
SIH_INT
OCP
Clocks
TAP
TPS65930/TPS65920
SWCS037G–MAY 2008– REVISED APRIL 2011
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Figure 1-2. TPS65930 Block Diagram
12 Introduction Copyright © 2008–2011, Texas Instruments Incorporated
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037-003
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2 Terminal Description
Figure 2-1 shows the ball locations for the 139 -ball plastic ball grid array (PBGA) package. Use this array
with Table 2-1 to locate signal names and ball grid numbers.
SWCS037G–MAY 2008– REVISED APRIL 2011
Figure 2-1. PBGA Bottom View
2.1 Ball Characteristics
Table 2-1 describes the terminal characteristics and the signals multiplexed on each pin. The following list
describes the table column headers:
1. Ball: Ball number(s) associated with each signal(s)
2. Pin Name: The names of all the signals that are multiplexed on each ball
3. A/D: Analog or digital signal
4. Type: The terminal type when a particular signal is multiplexed on the terminal:
– I = Input
– O = Output
5. Reference Level: See the power module chapter for values.
6. PU/PD: Denotes the presence of an internal pullup or pulldown. Pullups and pulldowns can be enabled
or disabled by software.
7. Buffer Strength: Drive strength of the associated output buffer
Table 2-1. Ball Characteristics
TPS65920 TPS65930 Pin A/D Reference Level
Ball[1] Ball[1] Name[2] [3] RL[5]
H2 H2 ADCIN0 A I/O VINTANA1.OUT
F2 F2 ADCIN2 A I VINTANA2.OUT
M5 M5 PCHGAC A I VACCHARGER
N1 N1 VPRECH A O VPRECH
N5 N5 VBAT A Power VBAT
F7 F7 75 100 202 59 100 144
GPIO0/CD1 D I/O IO_1P8 8
JTAG.TDO D I/O IO_1P8 8
Type[4] Strength
PU[6] (kΩ) PD[6] (kΩ) Buffer
Min Typ Max Min Typ Max
(mA)[7]
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Table 2-1. Ball Characteristics (continued)
TPS65920 TPS65930 Pin A/D Reference Level
Ball[1] Ball[1] Name[2] [3] RL[5]
E7 E7 75 100 202 59 100 144
P2 P2 156 220 450 59 100 144
P13 P13 156 220 450 59 100 144
L5 L5 PWM0 D O IO_1P8 75 100 202 59 100 144 4
J7 J7 75 100 202 59 100 144
D8 D8 SYSEN D Open drain/I IO_1P8 4.7 7.35 10 2
A4 A4 CLKEN D O IO_1P8 2
B13 B13 CLKREQ D I IO_1P8 60 100 146
C10 C10 INT1 D O IO_1P8 2
C8 C8 NRESPWRON D O IO_1P8 2
B9 B9 NRESWARM D I IO_1P8 2
D10 D10 PWRON D I VBAT
G5 G5 NSLEEP1 D I IO_1P8
E10 E10 CLK256FS
E4 E4 VMODE1 D I IO_1P8
E8 E8 BOOT0 A/D I/O VBAT
D7 D7 BOOT1 A/D I/O VBAT
B8 B8 REGEN D Open drain VBAT 5.5 8 12 2
H4 H4 MSECURE D I IO_1P8
L13 L13 VREF A Power VREF
K13 K13 AGND A ground GND
B3 B3
C5 C5
C3 C3 I2C.CNTL.SDA D I/O IO_1P8 2.5 3.4 12
B4 B4 I2C.CNTL.SCL D I IO_1P8 2.5 3.4 12
(2)
See
(2)
See
(2)
See
(2)
See
(2)
See
(2)
See
A10 A10 VBAT.RIGHT A Power VBAT
(2)
See
(2)
See
(2)
See
(2)
See
(2)
See
GPIO1 D I/O IO_1P8 2
JTAG.TMS D I IO_1P8
GPIO2 D I/O IO_1P8 2
TEST1 D I/O IO_1P8 2
GPIO15 D I/O IO_1P8 2
TEST2 D I/O IO_1P8 2
GPIO6 D I/O IO_1P8 2
TEST3 D I/O IO_1P8 2
GPIO7 D I/O IO_1P8 2
VIBRA.SYNC D I IO_1P8
PWM1 D O IO_1P8 4
TEST4 D I/O IO_1P8 2
(1)
N.C.
I2C.SR.SDA D I/O IO_1P8 2.5 3.4 12
VMODE2 D I IO_1P8 2
I2C.SR.SCL D I/O IO_1P8 2.5 3.4 12
H3 I2S.CLK D I/O IO_1P8 2
K2 I2S.SYNC D I/O IO_1P8 2
K4 I2S.DIN D I IO_1P8 2
K3 I2S.DOUT D O IO_1P8 2
D1 MIC.MAIN.P A I MICBIAS1.OUT
E1 MIC.MAIN.M A I MICBIAS1.OUT
PreDriv.LEFT A O VINTANA2.OUT
A7
VMID A Power VINTANA2.OUT
PreDriv.RIGHT A O VINTANA2.OUT
A8
ADCIN7 A I VINTANA2.OUT
G1 AUXR A I VINTANA2.OUT
MICBIAS1.OUT A Power VINTANA2.OUT
E2
VMIC1.OUT A Power VINTANA2.OUT
D2 MICBIAS.GND Power GND GND
Type[4] Strength
D O IO_1P8 2
Power
(GND)
PU[6] (kΩ) PD[6] (kΩ) Buffer
Min Typ Max Min Typ Max
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(mA)[7]
(1) To avoid reflection on this pin as a result of impedance mismatch, a serial resistance of 33 Ω must be added. This clock output is
available in TPS65920 also. Can be used as a clock source, if required.
(2) Balls A7, A8, D1, D2, E1, E2, G1, H3, K2, K3, and K4 are present on TPS65920 package. However, there is no function associated with
these pins. These can be left floating.
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Table 2-1. Ball Characteristics (continued)
TPS65920 TPS65930 Pin A/D Reference Level
Ball[1] Ball[1] Name[2] [3] RL[5]
G2 G2 AVSS1 A Power GND GND
L7 L7 AVSS2 A Power GND GND
N14 N14 AVSS3 A Power GND GND
C7 C7 AVSS4 A Power GND GND
M10 M10 32KCLKOUT D O IO_1P8
L14 L14 32KXIN A I IO_1P8
K14 K14 32KXOUT A O IO_1P8
A11 A11 HFCLKIN A I IO_1P8
M11 M11 HFCLKOUT D O IO_1P8
P8 P8 VBUS A Power VBUS
N10 N10 DP/UART3.RXD A I/O VBUS 2
P10 P10 DN/UART3.TXD A I/O VBUS 2
G6 G6 ID A I/O VBUS 2
K11 K11 UCLK D I IO_1P8 16
H12 H12 75 100 202 59 100 144
H11 H11 75 100 202 59 100 144
J8 J8 75 100 202 59 100 144
L10 L10
K10 K10
G11 G11
G10 G10 UART4.CTSO D O IO_1P8 16
E12 E12 75 100 202 59 100 144
G9 G9 75 100 202 59 100 144
G12 G12 75 100 202 59 100 144
E11 E11 75 100 202 59 100 144
P14 P14 TEST.RESET A/D I VBAT 30 50 70
P1 P1 TESTV1 A I/O VBAT
A14 A14 TESTV2 A I/O VINTANA2.OUT
A1 A1 TEST D I IO_1P8 60 100 146
A13 A13 D I IO_1P8
B14 B14 D I IO_1P8
P7 P7 CP.IN A Power VBAT/VBUS
N7 N7 CP.CAPP A O CP.CAPP
N6 N6 CP.CAPM A O CP.CAPM
P5 P5 CP.GND A Power GND GND
N9 N9 VBAT.USB A Power VBAT
M8 M8 VUSB.3P1 A Power VUSB.3P1
L1 L1 VAUX12S.IN A Power VBAT
N2 N2 VAUX2.OUT A Power VAUX2.OUT
H14 H14 VPLLA3R.IN A Power VBAT
K12 K12 VRTC.OUT A Power VRTC.OUT
STP D I IO_1P8 16
GPIO9 D I/O IO_1P8 2
DIR D O IO_1P8 16
GPIO10 D I/O IO_1P8 2
NXT D O IO_1P8 16
GPIO11 D I/O IO_1P8 2
DATA0 D I/O IO_1P8 16
UART4.TXD D I IO_1P8
DATA1 D I/O IO_1P8 16
UART4.RXD D O IO_1P8 2
DATA2 D I/O IO_1P8 16
UART4.RTSI D I IO_1P8
DATA3 D I/O IO_1P8 16
GPIO12 D I/O IO_1P8 75 100 202 59 100 144 16
DATA4 D I/O IO_1P8 16
GPIO14 D I/O IO_1P8 2
DATA5 D I/O IO_1P8 16
GPIO3 D I/O IO_1P8 2
DATA6 D I/O IO_1P8 16
GPIO4 D I/O IO_1P8 2
DATA7 D I/O IO_1P8 16
GPIO5 D I/O IO_1P8 2
JTAG.TDI/
BERDATA
JTAG.TCK/
BERCLK
Type[4] Strength
PU[6] (kΩ) PD[6] (kΩ) Buffer
Min Typ Max Min Typ Max
60 100 140 60 100 140
(mA)[7]
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Table 2-1. Ball Characteristics (continued)
TPS65920 TPS65930 Pin A/D Reference Level
Ball[1] Ball[1] Name[2] [3] RL[5]
G14 G14 VPLL1.OUT A Power VPLL1.OUT
A2 A2 VMMC1.IN A Power VBAT
B1 B1 VMMC1.OUT A Power VMMC1.OUT
M7 M7 A Power VINTUSB1P5.OUT
N8 N8 A Power VINTUSB1P8.OUT
K1 K1 VDAC.IN A Power VBAT
L2 L2 VDAC.OUT A Power VDAC.OUT
H13 H13 VINT.IN A Power VBAT
H1 H1 VINTANA1.OUT A Power VINTANA1.OUT
J2 J2 VINTANA2.OUT A Power VINTANA2.OUT
A5 A5 VINTANA2.OUT A Power VINTANA2.OUT
J13 J13 VINTDIG.OUT A Power VINTDIG.OUT
D13 D13 VDD1.IN A Power VBAT
D12 D12 VDD1.IN A Power VBAT
D14 D14 VDD1.IN A Power VBAT
C11 C11 VDD1.SW A O VBAT
C12 C12 VDD1.SW A O VBAT
C13 C13 VDD1.SW A O VBAT
E14 E14 VDD1.FB A I
A12 A12 VDD1.GND A Power GND GND
B11 B11 VDD1.GND A Power GND GND
B12 B12 VDD1.GND A Power GND GND
M13 M13 VDD2.IN A Power VBAT
M12 M12 VDD2.IN A Power VBAT
N13 N13 VDD2.FB A I
N11 N11 VDD2.SW A O VBAT
P11 P11 VDD2.SW A O VBAT
N12 N12 VDD2.GND A Power GND GND
P12 P12 VDD2.GND A Power GND GND
M2 M2 VIO.IN A Power VBAT
M3 M3 VIO.IN A Power VBAT
M4 M4 VIO.FB A I
N4 N4 VIO.SW A O VBAT
P4 P4 VIO.SW A O VBAT
N3 N3 VIO.GND A Power GND GND
P3 P3 VIO.GND A Power GND GND
H9 H9 BKBAT A Power VBACK
B7 B7 IO.1P8 A Power IO_1P8
H10 H10 DGND A Power GND GND
F13 F13 LEDGND A Power GND GND
B10 B10 75 100 202 59 100 144
E13 E13
G13 G13
G4 G4 KPD.C0 D Open drain IO_1P8
G3 G3 KPD.C1 D Open drain IO_1P8
E5 E5 KPD.C2 D Open drain IO_1P8
B2 B2 KPD.C3 D Open drain IO_1P8
E3 E3 KPD.C4 D Open drain IO_1P8
D5 D5 KPD.C5 D Open drain IO_1P8
K7 K7 KPD.R0 D I IO_1P8 8 10 12
VINTUSB1P5.
OUT
VINTUSB1P8.
OUT
GPIO13 D I/O IO_1P8
LEDSYNC D I IO_1P8
LEDA A Open drain VBAT
VIBRA.P A Open drain VBAT
LEDB A Open drain VBAT
VIBRA.M A Open drain VBAT
Type[4] Strength
PU[6] (kΩ) PD[6] (kΩ) Buffer
Min Typ Max Min Typ Max
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(mA)[7]
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Table 2-1. Ball Characteristics (continued)
TPS65920 TPS65930 Pin A/D Reference Level
Ball[1] Ball[1] Name[2] [3] RL[5]
H5 H5 KPD.R1 D I IO_1P8 8 10 12
K5 K5 KPD.R2 D I IO_1P8 8 10 12
H6 H6 KPD.R3 D I IO_1P8 8 10 12
K8 K8 KPD.R4 D I IO_1P8 8 10 12
L8 L8 KPD.R5 D I IO_1P8 8 10 12
Type[4] Strength
PU[6] (kΩ) PD[6] (kΩ) Buffer
Min Typ Max Min Typ Max
2.2 Signal Description
Table 2-2 describes the signals on the TPS65920 and TPS65930 devices; some signals are available on
multiple pins.
Table 2-2. Signal Description
Module Description Type
ADC
Charger
GPIOs/ TEST2 I/O
JTAG
Signal TPS65920 TPS65930 Features
Name Ball Ball Not Used
ADCIN0 Battery type I/O H2 H2 ADCIN0 GND
ADCIN2 General-purpose ADC input I F2 F2 ADCIN2 I GND
PCHGAC I M5 M5 PCHGAC I GND
VPRECH Precharge regulator output O N1 N1 VPRECH O Cap to GND
VBAT Battery voltage sensing Power N5 N5 VBAT Power VBAT
GPIO0/CD1 GPIO0/card detection 1 I/O
JTAG.TDO JTAG test data output I/O
GPIO1 GPIO1 I/O
JTAG.TMS JTAG test mode state I
GPIO2 GPIO2 I/O
TEST1 I/O
GPIO15 GPIO15 I/O
GPIO6 GPIO6 I/O
PWM0 Pulse width driver 0 O
TEST3 I/O
GPIO7 GPIO7 I/O
VIBRA.SYNC Vibrator on-off synchronization I
PWM1 Pulse width driver O
TEST4 I/O
AC precharge sense signal. Also
used for EEPROM.
TEST1 pin used in test mode
only
TEST2 pin used in test mode
only
TEST3 pin used in test mode
only (controlled by JTAG)
TEST4 pin used in test mode
only (controlled by JTAG)
F7 F7 GPIO0 I PD Floating
E7 E7 GPIO1 I PD Floating
P2 P2 GPIO2 I PD Floating
P13 P13 GPIO15 I PD Floating
L5 L5 GPIO6 I PD Floating
J7 J7 GPIO7 I PD Floating
SWCS037G–MAY 2008– REVISED APRIL 2011
Default Configuration After Reset
Released
Internal
Signal Type Pull or
Not
(mA)[7]
(1)
(2)
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Table 2-2. Signal Description (continued)
Default Configuration After Reset
Module Description Type
CONTROL
VREF
I2C
Smart
Reflex
I2C
TDM
ANA.MIC
HandsFree
Headset
AUX Input AUXR Auxiliary audio input right I G1 AUXR I Cap to GND
Signal TPS65920 TPS65930 Features
Name Ball Ball Not Used
SYSEN System enable output D8 D8 SYSEN OD PU Floating
CLKEN Clock enable O A4 A4 CLKEN O Floating
CLKREQ Clock request I B13 B13 CLKREQ I PD GND
INT1 Output interrupt line 1 O C10 C10 INT1 O Floating
NRESPWRON O C8 C8 NRESPWRON O Floating
NRESWARM I B9 B9 NRESWARM I GND
PWRON I D10 D10 PWRON I VBAT
NSLEEP1 Sleep request from device 1 I G5 G5 NSLEEP1 I GND
CLK256FS O E10 E10 CLK256FS O Floating
VMODE1 I E4 E4 VMODE1 I GND
BOOT0 Boot pin 0 I E8 E8 BOOT0 I PD N/A
BOOT1 Boot pin 1 I D7 D7 BOOT1 I PD N/A
REGEN Enable signal for external LDO B8 B8 REGEN OD PU Floating
MSECURE I H4 H4 MSECURE I N/A
VREF Reference voltage Power L13 L13 VREF Power N/A
AGND K13 K13 AGND GND
N.C. Not connected
I2C.SR.SDA I/O
VMODE2 I
I2C.SR.SCL I/O
I2C.CNTL.SDA I/O C3 C3 I2C.CNTL.SDA I/O PU N/A
I2C.CNTL.SCL I/O B4 B4 I2C.CNTL.SCL I/O PU N/A
I2S.CLK Clock signal (audio port) I/O H3 I2S.CLK I/O Floating
I2S.SYNC I/O K2 I2S.SYNC I/O Floating
I2S.DIN Data receive (audio port) I K4 I2S.DIN I GND
I2S.DOUT Data transmit (audio port) O K3 I2S.DOUT O Floating
MIC.MAIN.P Main microphone left input (P) I D1 MIC.MAIN.P I Cap to GND
MIC.MAIN.M Main microphone left input (M) I E1 MIC.MAIN.M I Cap to GND
VBAT.RIGHT Battery voltage input Power A10 A10 VBAT.RIGHT Power VBAT
PreDriv.LEFT O
VMID Power
PreDriv.RIGHT O
ADCIN7 General-purpose ADC input 7 I
Output control the NRESPWRON
of the application processor
Input; detect user action on the
reset button
Input; detect a control command
to start or stop the system
Digital voltage scaling linked with
VDD1
Security and digital rights
management
Analog ground for reference Power Power
voltage GND GND
SmartReflex I2C data
Digital voltage scaling linked with
VDD2
SmartReflex I2C data
General-purpose I2C data
General-purpose I2C clock
Synchronization signal (audio
port)
Predriver output left P for
external class-D amplifier
Predriver output right P for
external class-D amplifier
Open
drain/I
Open
drain
B3 B3 Floating
C5 C5 VMODE2 I GND
A7 VMID Power Floating
A8 ADCIN7 I GND
Signal Type Pull or
Signal not
functional
Released
Internal
Not
(3)
(1)
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Table 2-2. Signal Description (continued)
Default Configuration After Reset
Module Description Type
VMIC
BIAS
CLOCK 32KXOUT Output of the 32-kHz oscillator O K14 K14 32KXOUT O Floating
USB PHY
ULPI G11 G11 DATA2 O Floating
Signal TPS65920 TPS65930 Features
Name Ball Ball Not Used
MICBIAS1.
OUT
VMIC1.OUT Power
MICBIAS.GND D2 MICBIAS.GND GND
AVSS1 G2 G2 AVSS1
AVSS2 L7 L7 AVSS2
AVSS3 N14 N14 AVSS3
AVSS4 C7 C7 AVSS4
32KCLKOUT O M10 M10 32KCLKOUT O Floating
32KXIN Input of the 32-kHz oscillator I L14 L14 32KXIN I N/A
HFCLKIN I A11 A11 HFCLKIN I N/A
HFCLKOUT HS clock output O M11 M11 HFCLKOUT O Floating
VBUS VBUS power rail Power P8 P8 VBUS Power N/A
DP/ data/universal asynchronous DP/UART3.RX
UART3.RXD receiver/transmitter (UART)3 D
DN/ USB data N/USB carkit transmit DN/UART3.TX
UART3.TXD data/UART3 transmit data D
ID USB ID I/O G6 G6 ID I/O
UCLK HS USB clock I K11 K11 UCLK O Floating
STP HS USB stop I
GPIO9 GPIO9 I/O
DIR HS USB direction O
GPIO10 GPIO10 I/O
NXT HS USB next O
GPIO11 GPIO11 I/O
DATA0 HS USB Data0 I/O
UART4.TXD UART4.TXD I
DATA1 HS USB Data1 I/O
UART4.RXD UART4.RXD O
DATA2 HS USB Data2 I/O
UART4.RTSI UART4.RTSI I
DATA3 HS USB Data3 I/O
UART4.CTSO UART4.CTSO O G10 G10 DATA3 O Floating
GPIO12 GPIO12 I/O
DATA4 HS USB Data4 I/O
GPIO14 GPIO14 I/O
DATA5 HS USB Data5 I/O
GPIO3 GPIO3 I/O
DATA6 HS USB Data6 I/O
GPIO4 GPIO4 I/O
DATA7 HS USB Data7 I/O
GPIO5 GPIO5 I/O
Analog microphone bias 1 Power
Digital microphone power supply
1
Dedicated ground for Power Power
microphones GND GND
Analog ground GND
Buffered output of the 32-kHz
digital clock
Input of the digital (or sine) HS
clock
USB data P/USB carkit receive
receive data
Power Power
GND GND
I/O N10 N10 I/O N/A
I/O P10 P10 I/O N/A
H12 H12 STP I PU Floating
H11 H11 DIR O Floating
J8 J8 NXT O Floating
L10 L10 DATA0 O Floating
K10 K10 DATA1 O Floating
E12 E12 DATA4 O Floating
G9 G9 DATA5 O Floating
G12 G12 DATA6 O Floating
E11 E11 DATA7 O Floating
E2 MICBIAS1.OUT Power Floating
Signal Type Pull or
Released
Internal
Not
Connected to
VRUSB3V1
(1)
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Table 2-2. Signal Description (continued)
Default Configuration After Reset
Module Description Type
TEST
USB CP
VBAT.US USB LDOs (VINTUSB1P5,
B VINTUSB1P8, VUSB.3P1) VBAT
USB.LDO VUSB.3P1 USB LDO output Power M8 M8 VUSB.3P1 Power N/A
VAUX1 VAUX12S.IN Power L1 L1 VAUX12S.IN Power VBAT
VAUX2 VAUX2.OUT VAUX2 LDO output voltage Power N2 N2 VAUX2.OUT Power Floating
VPLLA3R VPLLA3R.IN Power H14 H14 VPLLA3R.IN Power VBAT
VRTC VRTC.OUT Power K12 K12 VRTC.OUT Power N/A
VPLL1 VPLL1.OUT LDO output voltage Power G14 G14 VPLL1.OUT Power Floating
VMMC1
VINTUSB1 VINTUSB1P5. VINTUSB1P5 internal LDO VINTUSB1P5.
P5 OUT output (internal use only) OUT
VINTUSB1 VINTUSB1P8. VINTUSB1P8 internal LDO VINTUSB1P8.
P8 OUT output (internal use only) OUT
Video
DAC
VINT VINT.IN Input for VINTDIG LDO Power H13 H13 VINT.IN Power VBAT
VINTANA1 Power H1 H1 Power N/A
VINTANA2
VINTDIG VINTDIG.OUT Power J13 J13 VINTDIG.OUT Power N/A
Signal TPS65920 TPS65930 Features
Name Ball Ball Not Used
TEST.RESET I P14 P14 TEST.RESET I PD GND
TESTV1 Analog test I/O P1 P1 TESTV1 I/O Floating
TESTV2 Analog test I/O A14 A14 TESTV2 I/O Floating
TEST and application mode for I A1 A1 TEST I PD Floating
JTAG.TDI/ JTAG.TDI/
BERDATA BERDATA
JTAG.TCK/ JTAG.TCK/
BERCLK BERCLK
CP.IN Charge pump input voltage Power P7 P7 CP.IN Power VBAT
CP.CAPP Charge pump flying capacitor P O N7 N7 CP.CAPP O Floating
CP.CAPM Charge pump flying capacitor M O N6 N6 CP.CAPM O Floating
CP.GND Charge pump ground P5 P5 CP.GND GND
VBAT.USB Power N9 N9 VBAT.USB Power VBAT
VMMC1.IN VMMC1 LDO input voltage Power A2 A2 VMMC1.IN Power VBAT
VMMC1.OUT VMMC1 LDO output voltage Power B1 B1 VMMC1.OUT Power Floating
VDAC.IN Power K1 K1 VDAC.IN Power VBAT
VDAC.OUT Output voltage of the regulator Power L2 L2 VDAC.OUT Power Floating
VINTANA1. VINTANA1 internal LDO output VINTANA1.OU
OUT (internal use only) T
VINTANA2. VINTANA2 internal LDO output VINTANA2.OU
OUT (internal use only) T
VINTANA2. VINTANA2 internal LDO output VINTANA2.OU
OUT (internal use only) T
Reset T2 device (except power
state-machine)
Selection between JTAG mode
JTAG/GPIOs (with PU or PD)
JTAG.TDI/BERDATA I A13 A13 I GND
JTAG.TCK/BERCLK I B14 B14 I GND
Power Power
GND GND
VAUX1/VAUX2/VSIM LDO input
voltage
Input for VPLL1, VPLL2, VAUX3,
and VRTC LDOs
VRTC internal LDO output
(internal use only)
Power M7 M7 Power Floating
Power N8 N8 Power Floating
Input for VDAC, VINTANA1, and
VINTANA2 LDOs
Power J2 J2 Power N/A
Power A5 A5 Power N/A
VINTDIG internal LDO output
(internal use only)
Signal Type Pull or
Released
Internal
Not
(1)
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Table 2-2. Signal Description (continued)
Default Configuration After Reset
Module Description Type
VDD1
VDD2
VIO
Backup
battery
Digital TPS65920/TPS65930 device I/O
VDD input
Digital Power Power
ground GND GND
LED driver
Signal TPS65920 TPS65930 Features
Name Ball Ball Not Used
VDD1.IN VDD1 dc-dc input voltage Power D13 D13 VDD1.IN Power VBAT
VDD1.IN VDD1 dc-dc input voltage Power D12 D12 VDD1.IN Power VBAT
VDD1.IN VDD1 dc-dc input voltage Power D14 D14 VDD1.IN Power VBAT
VDD1.SW VDD1 dc-dc switch O C11 C11 VDD1.SW O Floating
VDD1.SW VDD1 dc-dc switch O C12 C12 VDD1.SW O Floating
VDD1.SW VDD1 dc-dc switch O C13 C13 VDD1.SW O Floating
VDD1.FB I E14 E14 VDD1.FB I GND
VDD1.GND VDD1 dc-dc ground A12 A12 VDD1.GND GND
VDD1.GND VDD1 dc-dc ground B11 B11 VDD1.GND GND
VDD1.GND VDD1 dc-dc ground B12 B12 VDD1.GND GND
VDD2.IN VDD2 dc-dc input voltage Power M13 M13 VDD2.IN Power VBAT
VDD2.IN VDD2 dc-dc input voltage Power M12 M12 VDD2.IN Power VBAT
VDD2.FB I N13 N13 VDD2.FB I GND
VDD2.SW VDD2 dc-dc switch O N11 N11 VDD2.SW O Floating
VDD2.SW VDD2 dc-dc switch O P11 P11 VDD2.SW O Floating
VDD2.GND VDD2 dc-dc ground N12 N12 VDD2.GND GND
VDD2.GND VDD2 dc-dc ground P12 P12 VDD2.GND GND
VIO.IN VIO dc-dc input voltage Power M2 M2 VIO.IN Power VBAT
VIO.IN VIO dc-dc input voltage Power M3 M3 VIO.IN Power VBAT
VIO.FB I M4 M4 VIO.FB I GND
VIO.SW VIO dc-dc switch O N4 N4 VIO.SW O Floating
VIO.SW VIO dc-dc switch O P4 P4 VIO.SW O Floating
VIO.GND VIO dc-dc ground N3 N3 VIO.GND GND
VIO.GND VIO dc-dc ground P3 P3 VIO.GND GND
BKBAT Backup battery Power H9 H9 BKBAT Power GND
IO.1P8 Power B7 B7 IO.1P8 Power N/A
DGND Digital ground H10 H10 DGND GND
LEDGND LED driver ground F13 F13 LEDGND GND
GPIO13 GPIO13 I/O
LEDSYNC LED synchronization input I
LEDA LED leg A
VIBRA.P H-bridge vibrator P
LEDB LED leg B
VIBRA.M H-bridge vibrator M
VDD1 dc-dc output voltage
(feedback)
VDD2 dc-dc output voltage
(feedback)
VIO dc-dc output voltage
(feedback)
Power Power
GND GND
Power Power
GND GND
Power Power
GND GND
Power Power
GND GND
Power Power
GND GND
Power Power
GND GND
Power Power
GND GND
Power Power
GND GND
B10 B10 GPIO13 I PD Floating
Open Signal not
drain functional
Open Signal not
drain functional
E13 E13 Floating
G13 G13 Floating
Signal Type Pull or
Released
(3)
(3)
Internal
Not
(1)
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Table 2-2. Signal Description (continued)
Default Configuration After Reset
Module Description Type
Keypad
Signal TPS65920 TPS65930 Features
Name Ball Ball Not Used
KPD.C0 Keypad column 0 G4 G4 KPD.C0 OD Floating
KPD.C1 Keypad column 1 G3 G3 KPD.C1 OD Floating
KPD.C2 Keypad column 2 E5 E5 KPD.C2 OD Floating
KPD.C3 Keypad column 3 B2 B2 KPD.C3 OD Floating
KPD.C4 Keypad column 4 E3 E3 KPD.C4 OD Floating
KPD.C5 Keypad column 5 D5 D5 KPD.C5 OD Floating
KPD.R0 Keypad row 0 I K7 K7 KPD.R0 I PU Floating
KPD.R1 Keypad row 1 I H5 H5 KPD.R1 I PU Floating
KPD.R2 Keypad row 2 I K5 K5 KPD.R2 I PU Floating
KPD.R3 Keypad row 3 I H6 H6 KPD.R3 I PU Floating
KPD.R4 Keypad row 4 I K8 K8 KPD.R4 I PU Floating
KPD.R5 Keypad row 5 I L8 L8 KPD.R5 I PU Floating
Open
drain
Open
drain
Open
drain
Open
drain
Open
drain
Open
drain
Signal Type Pull or
(1) This column provides the connection when the associated feature is not used or not connected. When there is a pin muxing, not all
functions on the muxed pin are used. But even if a function is not used, the Default Configuration After Reset Released column still
applies.
Connection criteria:
– Analog pins:
– For input: GND
– For output: Floating (except VPRECH is connected to GND)
– For I/O if input by default: GND (except for audio features input: capacitor to ground with a 100-nF typical value capacitor)
– Digital pins:
– For input: GND (except keypad and STP are left floating)
– For input and pullup: Floating
– For output: Floating
– For I/O and pullup: Floating
N/A (not applicable): When the associated feature is mandatory for correct functioning of the TPS65920/TPS65930 device
(2) The signal VPRECH must be connected to the CPRECH capacitor to GND.
(3) Signal not functional indicates that no signal is presented on the pad after a release reset.
Released
Internal
Not
(1)
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3 Electrical Characteristics
3.1 Absolute Maximum Ratings
Table 3-1 lists the absolute maximum ratings.
Table 3-1. Absolute Maximum Ratings
Parameter Test Conditions Min Typ Max Unit
Main battery supply voltage
Voltage on any input Supply represents the voltage applied to the 0.0 1.0*Supply V
Storage temperature range –55 125 °C
Ambient temperature range –40 85 °C
Junction temperature (TJ) At 1.4 W (Theta JB 11°C/W 2S2P board) 105 °C
Junction temperature (TJ) for parametric –40 105 °C
compliance
(1) The product has negligible reliability impact if voltage spikes of 5.2 V occur for a total duration of 10 milliseconds.
3.2 Minimum Voltages and Associated Currents
Table 3-2 lists the VBAT minimum and maximum currents per VBAT ball.
Table 3-2. VBAT Minimum Required Per VBAT Ball and Associated Maximum Current
(1)
power supply pin associated with the input
2.1 4.5 V
Category Pin and Module Maximum Current Output Voltage (V) VBAT Minimum (V)
VBAT pin name VDD_VPLLA3R_IN_6POV 340
VPLL1 (LDO) 40 1.0 / 1.2 / 1.3 / 1.8 / 2.8 / Maximum
Internal module
supplied VDD2 core (DCDC) < 1 2.7
VBAT pin name VDD_VDAC_IN_6POV 370
Internal module
supplied
VBAT pin name VDD_VAUXI2S_IN_6POV 350
Internal module
supplied
VBAT pin name VDD_VMMC1_IN_6POV 220
Internal module VMMC1 (LDO) 220 1.85 / 2.85 / 3.0 / 3.15 Maximum
supplied (2.7, output voltage selected + 250 mV)
VBAT pin name VDD_VINT_IN_6POV 131
VDD1 core (DCDC) < 1 2.7
SYSPOR (power ref) < 1 2.7
PBIAS (power ref) < 1 2.7
VDAC (LDO) 70 1.2 / 1.3 / 1.8 Maximum
VINTANA1 (LDO) 50 1.5 Maximum
VINTANA2 (LDO) 250 2.5 / 2.75 Maximum
VIO core (DCDC) < 1 2.7
VAUX2 (LDO) 100 1.3 / 1.5 / 1.6 / 1.7 / 1.8 / Maximum
Power_REGBATT 0.001 2.7
Specified (mA)
3.0 (2.7, output voltage selected + 250 mV)
(2.7, output voltage selected + 250 mV)
(2.7, output voltage selected + 250 mV)
(2.7, output voltage selected +250 mV)
1.9 / 2.0 / 2.1 / 2.2 / 2.3 / (2.7, output voltage selected + 250 mV)
2.4 / 2.5 / 2.8
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Table 3-2. VBAT Minimum Required Per VBAT Ball and Associated Maximum Current (continued)
Category Pin and Module Maximum Current Output Voltage (V) VBAT Minimum (V)
VINTDIG (LDO) 80 1.0 / 1.2 / 1.3 / 1.5 Maximum
Internal module VRRTC (LDO) 30 1.5 Maximum
supplied (2.7, output voltage selected + 250 mV)
VBACKUP (LDO) 1 2.5 / 3.0 / 3.1 / 3.2 Maximum
Specified (mA)
(2.7, output voltage selected + 250 mV)
(2.7, output voltage selected + 250 mV)
3.3 Recommended Operating Conditions
Table 3-3 lists the recommended operating maximum ratings.
Table 3-3. Recommended Operating Maximum Ratings
Parameter Test Conditions Min Typ Max Unit
Main battery supply voltage 2.7
Backup battery supply voltage 1.8 3.2 3.3 V
Ambient temperature range –40 85 °C
(1) 2.7 V is the minimum threshold for the battery at which the device will turn OFF. However, the minimum voltage at which the device will
power ON is 3.2 V ±100 mV (if PWRON does not have a switch and is connected to VBAT) considering battery plug as the device
switch on event. If PWRON has a switch then 3.2 V is the minimum for the device to turn ON.
(1)
3.6 4.5 V
3.4 Digital I/O Electrical Characteristics
Table 3-4 describes the digital I/O electrical characteristics. The following list defines abbreviations used in
the table:
• RL: Reference level voltage applied to the I/O cell
• VOL: Low-level output voltage
• VOH: High-level output voltage
• VIL: Low-level input voltage
• VIH: High-level input voltage
• Min: Minimum value
• Max: Maximum value
Table 3-4. Digital I/O Electrical Characteristics
Pin Name Fall Time (ns)
GPIO0/CD1
JTAG.TDO
GPIO0
JTAG.TMS
GPIO2
TEST1
GPIO15
TEST2
GPIO6
PWM0 0 0.45 RL–0.45 RL 0 0.35xRL 0.65xRL RL 3 30 5.2 5.2
TEST3
GPIO7
VIBRA.SYNC
PWM1
TEST4
VOL (V) VOH (V) VIL (V) VIL (V)
Min Max Min Max Min Max Min Max
0 0.45 RL–0.45 RL 0 0.35xRL 0.65xRL RL 33 30 5.2 5.2
0 0.45 RL–0.45 RL 0 0.35xRL 0.65xRL RL 33 30 5.2 5.2
0 0.45 RL–0.45 RL 0 0.35xRL 0.65xRL RL 3 30 5.2 5.2
0 0.45 RL–0.45 RL 0 0.35xRL 0.65xRL RL 3 30 5.2 5.2
0 0.45 RL–0.45 RL 0 0.35xRL 0.65xRL RL 3 30 5.2 5.2
Max Freq Load (pF) Rise
(MHz) Output Mode Time (ns)
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Table 3-4. Digital I/O Electrical Characteristics (continued)
Pin Name Fall Time (ns)
SYSEN 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 5.2 5.2
CLKEN 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 30 33.3 33.3
CLKREQ 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 33.3 33.3
INT1 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 30 33.3 33.3
NRESPWRON 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 30 33.3 33.3
NRESWARM 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 30 33.3 33.3
PWRON 0 0.35×1.8V 0.65×1.8V VBAT 3 33.3 33.3
NSLEEP1 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 33.3 33.3
CLK256FS 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 12.288 30 16.3 16.3
VMODE1 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 33.3 33.3
BOOT0 0 RL 3 33.3 33.3
BOOT1 0 RL 3 33.3 33.3
REGEN 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 30 33.3 33.3
MSECURE 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 33.3 33.3
I2C.SR.SDA 0 0.4 –0.5 0.3×RL 0.7×RL RL+0.5 3.4 Up to 400
VMODE2 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3.4 29.4 29.4
I2C.SR.SCL 0 0.4 –0.5 0.3×RL 0.7×RL RL+0.5 3.4 10.0 10.0
I2C.CNTL.SDA 0 0.4 –0.5 0.3×RL 0.7×RL RL+0.5 3.4 Up to 400
I2C.CNTL.SCL 0 0.4 –0.5 0.3×RL 0.7×RL RL+0.5 3.4 10.0 10.0
I2S.CLK 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 6.5 30 33.0 33.0
I2S.SYNC 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 6.5 30 33.0 33.0
I2S.DIN 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3.25 30 33.0 33.0
I2S.DOUT 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3.25 30 29.0 29.0
32KCLKOUT 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 0.032 30 16 16
HFCLKOUT 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 38.4 30 2.6 2.6
UCLK 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 60 10 1.0 1.0
STP
GPIO9
DIR
GPIO10
NXT
GPIO11
DATA0
UART4.TXD
DATA1
UART4.RXD
DATA2
UART4.RTSI
DATA3
UART4.CTSO
GPIO12 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 30 10 1.0 1.0
DATA4
GPIO14
DATA5
GPIO3
DATA6
GPIO4
DATA7
GPIO5
TEST.RESET 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 33.0 33.0
TEST 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 30 29.0 29.0
JTAG.TDI/
BERDATA
JTAG.TCK/
BERDATA
VOL (V) VOH (V) VIL (V) VIL (V)
Min Max Min Max Min Max Min Max
0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 30 10 1.0 1.0
0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 30 10 1.0 1.0
0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 30 10 1.0 1.0
0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 30 10 1.0 1.0
0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 30 10 1.0 1.0
0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 30 10 1.0 1.0
0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 30 10 1.0 1.0
0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 30 10 1.0 1.0
0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 30 10 1.0 1.0
0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 30 10 1.0 1.0
0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 30 10 1.0 1.0
0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 33.0 33.0
0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 3 33.0 33.0
Max Freq Load (pF) Rise
(MHz) Output Mode Time (ns)
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Table 3-4. Digital I/O Electrical Characteristics (continued)
Pin Name Fall Time (ns)
GPIO13
LEDSYNC
KPD.C0 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 0.033 30 29.0 29.0
KPD.C1 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 0.033 30 29.0 29.0
KPD.C2 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 0.033 30 29.0 29.0
KPD.C3 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 0.033 30 29.0 29.0
KPD.C4 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 0.033 30 29.0 29.0
KPD.C5 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 0.033 30 29.0 29.0
KPD.C6 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 0.033 30 29.0 29.0
KPD.C7 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 0.033 30 29.0 29.0
KPD.R0 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 0.033 3051.8 3051.8
KPD.R1 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 0.033 3051.8 3051.8
KPD.R2 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 0.033 3051.8 3051.8
KPD.R3 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 0.033 3051.8 3051.8
KPD.R4 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 0.033 3051.8 3051.8
KPD.R5 0 0.45 RL–0.45 RL 0 0.35×RL 0.65×RL RL 0.033 3051.8 3051.8
KPD.R6 0 0.45 0.45 RL 0 0.35×RL 0.65×RL RL 0.033 3051.8 3051.8
KPD.R7 0 0.45 0.45 RL 0 0.35×RL 0.65×RL RL 0.033 3051.8 3051.8
VOL (V) VOH (V) VIL (V) VIL (V)
Min Max Min Max Min Max Min Max
0 0.45 RL–0.45 RL 0 0.35×RL 0.35×RL 3 30 33.3 33.3
Max Freq Load (pF) Rise
(MHz) Output Mode Time (ns)
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VRUSB_1V8
1.81V
30mA
VRUSB_3V1
3.1V
15mA
Mainbattery
VIO.L
VIO.OUT
VIO.GND
VIO.INx2
VDD2.L
VDD2.OUT
VDD2.GND
(2)
(2)
VDD2
(DC-DC)
0.6Vto1.5V
600mA
VDD2.INx2
VMMC1
1.85/2.85
/3.0/3.15V
220mA
VMMC1.OUT
VAUX2
1.3/1.5/1.7/1.8/1.9/2.0/
2.1/2.2/2.3/2.4/2.5/2.8V
100mA
VAUX2.OUT
VPLL1
1.0/1.2/1.3/1.8V
40mA
VPLL1.OUT
VINTANA.OUT
VINTANA1
1.5V
50mA
VINTDIG.OUT
VINTDIG
1.0/1.2/1.3/1.5V
80mA
VDAC
1.2/1.3/1.8V
70mA
VDAC.OUT
VINTANA2.OUT
VINTANA2
2.5/2.75V
250mA
VDD1.L
VDD1.OUT
VDD1.GND
(3)
VDD1
(DC-DC)
0.6Vto1.45V
1200mA
VDD1.INx3
VUSB.3P1
VINTUSB1P8.OUT
VRUSB_1V5
1.525V
30mA
VINTUSB1P5.OUT
VIO
(DC-DC)
1.8V/1.85V
700mA
(3)
(2)
(2)
037-010
CVINTDIG.OUT
CVINTANA1.OUT
CVINTANA2.OUT
CVDAC.OUT
LVDD1
CVDD1.OUT
LVDD2
CVDD2.OUT
LVIO
CVIO.OUT
VINT.IN
VDAC.IN
VDAC.IN
VDAC.IN
VPLLA3R.IN
VMMC1.IN
VAUX12S.IN
VBAT.USB
VBAT.USB
VBAT.USB
CVPLL1.OUT
CVMMC1.OUT
CVAUX2.OUT
CVUSB.3P1
CVINTUSB1P8.OUT
CVINTUSB1P5.OUT
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4 Power Module
This section describes the electrical characteristics of the voltage regulators and timing characteristics of
the supplies digitally controlled in the TPS65920 and TPS65930 devices .
Figure 4-1 is the power provider block diagram.
SWCS037G–MAY 2008– REVISED APRIL 2011
Two internal regulators, VRRTC and VBRTC, are not shown. VRRTC provides power to the RTC, and VBRTC is not
used in this configuration.
Figure 4-1. Power Provider Block Diagram
For the component values, see Table 14-1.
NOTE
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4.1 Power Providers
Table 4-1 summarizes the power providers.
Table 4-1. Summary of the Power Providers
Name Usage Type Voltage Range (V) Default Voltage
VAUX2 External LDO 1.3, 1.5, 1.7, 1.8, 1.9, 2.0, 2.1, 2.2, 2.3, 2.4, 2.5, 2.8 1.8 V 100 mA
VMMC1 External LDO 1.85, 2.85, 3.0, 3.15 3.0 V 220 mA
VPLL1 External LDO 1.0, 1.2, 1.3, 1.8, 2.8, 3.0 1.8 V 40 mA
VDAC External LDO 1.2, 1.3, 1.8 1.8 V 70 mA
VIO External SMPS 1.8, 1.85 1.8 V 700 mA
VDD1 External SMPS 0.6 ... 1.45 1.2 V 1200 mA
VDD2 External SMPS 0.6 ... 1.5 1.2 V 600 mA
VINTANA1 Internal LDO 1.5 1.5 V 50 mA
VINTANA2 Internal LDO 2.5, 2.75 2.75 V 250 mA
VINTDIG Internal LDO 1.0, 1.2, 1.3, 1.5 1.5 V 80 mA
USBCP Internal Charge pump 5 5 V 100 mA
VUSB1V5 Internal LDO 1.5 1.5 V 30 mA
VUSB1V8 Internal LDO 1.8 1.8 V 30 mA
VUSB3V1 Internal LDO 3.1 3.1 V 15 mA
VRRTC Internal LDO 1.5 1.5 V 30 mA
VBRTC Internal LDO 1.3 1.3 V 100 μA
Maximum
Current
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4.1.1 VDD1 dc-dc Regulator
4.1.1.1 VDD1 dc-dc Regulator Characteristics
The VDD1 dc-dc regulator is a stepdown dc-dc converter with a configurable output voltage. The
programming of the output voltage and the characteristics of the dc-dc converter are
SmartReflex-compatible. The regulator can be put in sleep mode to reduce its leakage (PFM) or in
power-down mode when it is not in use. Table 4-3 describes the regulator characteristics.
Table 4-2. Part Names With Corresponding VDD1 Current Support
Device Name VDD1 Current Support
TPS65920A2ZCH (some bug fixes, see errata) 1.2 A
TPS65920A2ZCHR (some bug fixes, see errata) 1.2 A
TPS65930A2ZCH (some bug fixes, see errata) 1.2 A
TPS65930A2ZCHR (some bug fixes, see errata) 1.2 A
Table 4-3. VDD1 dc-dc Regulator Characteristics
Parameter Comments Min Typ Max Unit
Input voltage range 2.7 3.6 4.5 V
Output voltage 0.6 1.45 V
Output voltage step Covering the 0.6-V to 1.45-V range 12.5 mV
Output accuracy
Switching frequency 3.2 MHz
Conversion efficiency
mode
Output current
Ground current (IQ) Off at 30°C 3 μA
Short-circuit current VIN= V
Load regulation 0 < IO< I
Transient load regulation
Line regulation 10 mV
Transient line regulation 300 mVPPac input, 10-μs rise and fall time 10 mV
Start-up time 0.25 1 ms
Recovery time From sleep mode to on mode with constant <10 100 μs
Slew rate (rising or falling)
Output shunt resistor (pulldown) 500 700 Ω
External coil Data capture record (DCR) 0.1 Ω
(1)
(2)
, Figure 4-2 in active
(3)
(4)
0.6 V to < 0.8 V –6% 6%
0.8 V to 1.45 V –4% 4%
IO= 10 mA, sleep 82%
100 mA < IO< 400 mA 85%
400 mA < IO< 600 mA 80%
600 mA < IO< 800 mA 75%
Active mode 1.2 A
Sleep mode 10 mA
Sleep, unloaded 30 50
Active, unloaded, not switching 300
Max
Max
IO= 10 mA to (I
Maximum slew rate is I
load
Value 0.7 1 1.3 μH
Saturation current 1.8 A
/2) + 10 mA,
Max
/2/100 ns
Max
–65 50 mV
2.2 A
20 mV
4 8 16 mV/μs
(1) Accuracy includes all variations (line and load regulations, line and load transients, temperature, and process)
(2) VBAT = 3.8 V, VDD1 = 1.3 V, Fs = 3.2 MHz, L = 1 μH, L
(3) Output voltage must discharge the load current completely and settle to its final value within 100 μs.
(4) Load current varies proportionally with the output voltage. The slew rate is for increasing and decreasing voltages, and the maximum
load current is 1.1 A.
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= 100 mΩ, C = 10 μF, ESR = 10 mΩ
DCR
SWCS037-018
VDD1EFFICIENCY vsOUTPUT CURRENT
Outputvoltage=1.3V,Vbat=3.6V
90
80
70
60
50
40
30
20
10
00
0.0001 0.001 0.01 0.1 1
ILOAD(A)
Effciency(%)
TPS65930/TPS65920
SWCS037G–MAY 2008– REVISED APRIL 2011
Table 4-3. VDD1 dc-dc Regulator Characteristics (continued)
Parameter Comments Min Typ Max Unit
External capacitor
(5) Under current load condition step:
Imax/2 (550 mA) in 100 ns with a ±20% external capacitor accuracy or
Imax/3 (367 mA) in 100 ns with a ±50% external capacitor accuracy
(5)
Value 8 10 12 μF
Equivalent series resistance (ESR) at 0 20 mΩ
switching frequency
See Table 2-2 for how to connect the VDD1/2 dc-dc converter when it is not in use.
Figure 4-2 shows the efficiency of the VDD1 dc-dc regulator in active mode and sleep mode.
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Figure 4-2. VDD1 dc-dc Regulator Efficiency
4.1.1.2 External Components and Application Schematics
Figure 4-3 is an application schematic with the external components on the VDD1 dc-dc regulator.
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