TEXAS INSTRUMENTS TPS65150 Technical data

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VIN

DRVN
FBN
REF

COMP

DLY1

DLY2

FDLY

SW SW

SUP

DRVP

GD

CPI

FBP

GND
PGND
PGND

VCOM

TPS65150

ADJ

CTRL

VGH

FB

IN

Vin
5 V

R8

500 k

C6

1 nF

R7

500 k

L1

3.9 H

D1

C1

22 F

C7

0.33 FD2

R3
620 k

D3

C3

0.33 F

R4
150 k

C8

220 nF

VGH

Control Signal

C9

2.2 nF

C10

22 pF

C11

10 nF

C12

10 nF

C13

100 nF

CPI

C16

0.33 F

D4

C5
1 F

C4

0.33 F

VGH
23 V/20 mA

V

COM

Output

C14
1 F

C15
22 pF

R1
820 k

R2
75 k

C2
22 F

R6
56 k

R5
1 M

CPI

V

S

13.5 V/450 mA

D5

VGL

−5 V/20 mA

V

IN

Low Input Voltage, Compact LCD Bias IC With VCOM Buffer

FEATURES APPLICATIONS

• 1.8-V to 6-V Input Voltage Range

• Integrated VCOM Buffer

• High Voltage Switch to Isolate VGH

• Gate Voltage Shaping of VGH

• 2-A Internal MOSFET Switch

• Main Output Vs up to 15 V With <1% Output

Voltage Accuracy

• Virtual Synchronous Converter Technology

• Negative Regulated Charge Pump Driver VGL

• Positive Regulated Charge Pump Driver VGH

• Adjustable Power On Sequencing

• Adjustable Fault Detection Timing

• Gate Drive Signal for external isolation

MOSFET

• Thermal Shutdown

• Available in TSSOP-24 Package

• Available in QFN-24 Package

TPS65150

SLVS576 – SEPTEMBER 2005

• TFT LCD Displays for Notebooks

• TFT LCD Display for Monitor

• Car Navigation Display

DESCRIPTION

The TPS65150 offers a very compact and small
power supply solution that provides all three voltages
required by thin film transistor (TFT) LCD displays.
With an input voltage range of 1.8 V to 6.0 V the
device is ideal for notebooks powered by a 2.5-V or

3.3-V input rail or monitor applications with a 5-V input voltage rail. Additionally the TPS65150 provides an integrated high current buffer to provide the VCOM voltage for the TFT backplane.

Two regulated adjustable charge pump driver provide
the positive VGH and negative VGL bias voltages for
the TFT. The device incorporates adjustable power
on sequencing for VGL as well as for VGH. This
avoids any additional external components to
implement application specific sequencing. The
device has an integrated high voltage switch to
isolate VGH.

TYPICAL APPLICATION

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPad is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2005, Texas Instruments Incorporated

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TPS65150

SLVS576 – SEPTEMBER 2005

These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION (CONTINUED)

The same internal circuit can also be used to provide a gate shaping signal of VGH for the LCD panel controlled
by the signal applied to the CTRL input. For highest safety the TPS65150 has an integrated adjustable shutdown
latch feature to allow application specific flexibility. The device monitors the outputs (Vs, VGL, VGH); and, as
soon as one of the outputs falls below its power good threshold, the device enters shutdown latch, after its
adjustable delay time has passed by.

ORDERING INFORMATION

T

A

–40 ° C to 85 ° C

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

Web site at www.ti.com .

(2) The PWP package is available taped and reeled. Add R suffix to the device type (TPS65150PWPR) to order quantities of 2000 and

(TPS65150RGER) to order quantities of 3000 devices per reel. Without suffix the device is shipped in tubes.

ORDERING NUMBER PACKAGE

TPS65150PWP TSSOP24 (PWP) TPS65150

TPS65150RGE QFN-24 (RGE) TPS65150

(1)

(2)

PACKAGE MARKING

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

Voltages on pin VIN
Voltages on pin SUP –0.3 V to 15.5 V
Voltage on pin SW 20 V
Voltage on CTRL –0.3 V to 7 V
Voltage on GD 15.5 V
Voltage on CPI 32V
Continuous power dissipation See Dissipation Rating Table
Operating junction temperature range –40 ° C to 150 ° C
Storage temperature range –65 ° C to 150 ° C
Lead temperature (soldering, 10 sec) 260 ° C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal.

(2)

(1)

UNIT

–0.3 V to 7 V

DISSIPATION RATINGS

PACKAGE θ

24 pin TSSOP 30.13 C ° /W ( PowerPad™ 3.3 W 1.83 W 1.32 W

24 pin QFN 30 C ° /W (PowerPad

JA

soldered)

TM

soldered) 3.3 W 1.8 W 1.3 W

TA≤ 25 ° C TA= 70 ° C TA= 85 ° C

POWER RATING POWER RATING POWER RATING

RECOMMENDED OPERATING CONDITIONS

MIN TYP MAX UNIT

VIN Input voltage range 1.8 6.0 V
V
L Inductor

T
(1) Refer to application section for further information.
2

Output voltage range of the main boost converter V

S

A

(1)

Operating ambient temperature –40 85 ° C

S

15 V

4.7 µH

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TPS65150

SLVS576 – SEPTEMBER 2005

RECOMMENDED OPERATING CONDITIONS (continued)

MIN TYP MAX UNIT

T

ELECTRICAL CHARACTERISTICS

VIN = 3.3 V, Vs = 10 V, TA= –40 ° C to 85 ° C, typical values are at TA= 25 ° C (unless otherwise noted)

SUPPLY CURRENT

V

I

QVIN

I

QSUP

I

QVCOM

V

V

LOGIC SIGNALS CTRL

V

V

I

I

MAIN BOOST CONVERTER

V

V

I

FB

R

I

MAX

I

LIM

Ileak Switch leakage current V

Vovp Output overvoltage protection V

f

OSC

NEGATIVE CHARGE PUMP VGL

VGL Output voltage range –2 V

V

V

I

FB

R

V

POSITIVE CHARGE PUMP OUTPUT

V

Operating junction temperature –40 125 ° C

J

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

IN

Input voltage range 1.8 6.0 V
No load quiescent current into Vin Device is not switching 14 25 µA
No load quiescent current into SUP Device is not switching 1.9 3 mA
VCOM quiescent current into SUP 750 1500 µA

UVLO
hys

Undervoltage lockout threshold VINfalling 1.6 1.8 V
Undervoltage lockout threshold VINrising 1.7 1.9 V
Thermal shutdown Temperature rising 155 ° C
Thermal shutdown hysteresis 10 ° C

IH
IL

High level input voltage 1.6 V
Low level input voltage 0.4 V
Input leakage current CTRL=GND or VIN 0.01 0.2 µA

S
FB

Output voltage range 15 V
Feedback regulation voltage 1.136 1.146 1.154 V
Feedback input bias current 10 100 nA

N-MOSFET on-resistance (Q1) m Ω

DS(on)

P-MOSFET on-resistance (Q2) Ω

Vs = 10 V; Isw = 500 mA 200 300
Vs = 5 V; Isw = 500 mA 305 450
Vs = 10 V; Isw = 500 mA 8 15

Vs = 5 V; Isw = 500 mA 12 22
Maximum P-MOSFET peak switch current 1 A
N-MOSFET switch current limit (Q1) 2.0 2.5 3.4 A

= 15 V 1 10 µA

sw

rising 16 20 V

OUT

Oscilator frequency 1.02 1.2 1.38 MHz
Line regulation Vin=1.8V to 5.0V, Iload=1mA 0.007 %/V
Load regulation Vin=5V, Iload=0A to 400mA 0.16 %/A

REF
FB

Reference Voltage on pin REF 1.205 1.213 1.219 V
Feedback regulation voltage –36 0 36 mV
Feedback input bias current 10 100 nA

DS(on)

DropN

Q4 P-Channel switch RDSon I

Current sink voltage drop

(1)

= 20 mA 4.4 Ω

OUT

I

= 50 mA, 130 300

DRN

V

= V

FBN

FBNNominal

I

= 100 mA, 280 450

DRN

V

= V

FBN

FBNNominal

– 5%

– 5%

Load regulation VGL=-5V, Iload=0mA to 20mA 0.016 %/mA

CPO

Output voltage range CTRL = GND, VGH = open 30 V

mV

(1) The maximum charge pump output current is half the drive current of the internal current source or sink.

3

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TPS65150

SLVS576 – SEPTEMBER 2005

ELECTRICAL CHARACTERISTICS (continued)

VIN = 3.3 V, Vs = 10 V, TA= –40 ° C to 85 ° C, typical values are at TA= 25 ° C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

FB

I

FB

R

DS(on)

V

DropN

VGH ISOLATION SWITCH, GATE VOLTAGE FALL TIME CONTROL

R

DS(on)

Iadj Capacitor charge current Vadj = 20 V, CPI = 30 V 160 200 240 µA

I

VGH

TIMING CIRCUITS DLY1, DLY2, FDLY

I

DLY1

I

DLY2

R

FDLY

GATE DRIVE (GD)

V

(GD, Vs)

V

OL

I

LKG

Vcom Buffer

V

CM

V

os

I

B

I

peak

Feedback regulation voltage CTRL = GND, VGH = open 1.187 1.214 1.238 V
Feedback input bias current CTRL = GND, VGH = open 10 100 nA
Q3 P-Channel switch RDSon I

Current sink voltage drop

(1)

= 20 mA 1.1 Ω

OUT

I

= 50 mA, 420 650

DRP

V

= V

FBP

FBPNominal

I

= 100 mA, 900 1400

DRP

V

= V

FBP

FBPNominal

– 5%

– 5%

Load regulation VGH=24V, Iload=0mA to 20mA 0.07 %/mA

Q5 - Pass MOSFET R

DSon

Minimum output voltage Vadj = 0 V, I

I

= 20 mA 12 30 Ω

OUT

= 10 mA 2 V

VGH

Maximum output current 20 mA

Drive current into delay capacitor DLY1 V
Drive current into delay capacitor DLY1 V
Fault time delay resistror

Gate drive threshold

(2)

(3)

= 1.213 V 3 5 7 µA

DLY1

= 1.213 V 3 5 7 µA

DLY2

250 450 650 k Ω

Vs rising –12% of –4% of V

Vs Vs
Gate drive output low voltage I
Gate drive output leakage current V

= 500 µA 0.5 V

(sink)

= 15 V 0.001 1 µA

GD

Common mode input range 2.25 (Vs) –2V V
Input offset voltage I

= 0 mA –25 25 mV

OUT

Io = ± 25 mA –37 37

DC load regulation mV

Io = ± 50 mA –77 55
Io = ± 100 mA –85 85

Io = ± 150 mA –110 110
VCOMIN Input bias current –300 –30 300 nA
Peak output current Vs = 15 V 1.2

Vs = 10 V 0.65 A

Vs = 5 V 0.15

mV

(2) The fault time is calculated as: tF= C × R = C × 450 k Ω
(3) The GD signal is latched low when the main boost converter output Vs is within regulation. The GD signal is reset when the input

voltage or enable of the boost converter is cycled low.

4

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1
2
3
4

5
6

7
8

9
10
11
12

24
23
22
21

20
19

18
17
16
15
14
13

FB
DLY1
DLY2

VIN
SW

SW
PGND
PGND

SUP

VCOM

IN

FBP

FDLY
GD
COMP
FBN
REF
GND
DRVN
DRVP
CPI
VGH
ADJ
CTRL

Thermal PowerPAD*

1
2
3
4
5
6

18
17

16
15
14
13

7 8 9 10 11 12

19

20212223

24

Exposed

Thermal Die*

COMP

GD

FDLY

FB
DLY1
DLY2

VINSWSW

PGND

PGND

SUP

VGH

ADJ
CTRL

FBP

IN

VCOM

FBN

REF

GND

DRVN

DRVP

CPI

TPS65150

SLVS576 – SEPTEMBER 2005

PIN ASSIGNMENT

* The thermal die (PowerPAD

TSSOP-24 Package

Top View

TM

) is connected to GND.

QFN-24 Package

Top View

TERMINAL FUNCTIONS

TERMINAL

NAME

ADJ 17 14 I/O

COMP 1 22 O
CPI 19 16 I Input of the VGH isolation switch and gate voltage shaping circuit.

CTRL 16 13 I function is not required, this pin needs to be connected to VIN. By doing this, the internal

DLY1 5 2 I/O delay time between the boost converter output Vs and the negative charge pump VGL

DLY2 6 3 I/O

DRVN 21 18 I/O Charge pump driver to generate the negative voltage VGL.
DRVP 20 17 I/O Charge pump driver to generate the positive output voltage VGH.
FB 4 1 I Feedback of the main boost converter generating Vsource (Vs).
FBN 24 21 I Feedback pin of the negative charge pump VGL.
FBP 15 12 I Feedback pin of the positive charge pump.

FDLY 3 24 I/O

GD 2 23 I
GND 22 19 Analog ground

NO. I/O DESCRIPTION

QFN TSSOP

Gate voltage shaping circuit. Connecting a capacitor to this pin sets the fall time of the
positive gate voltage (VGH).

This is the compensation pin for the main boost converter. A small capacitor and if required
a series resistor is connected to this pin.

Control signal for the gate voltage shaping signal. Apply the control signal for the gate
voltage control. Usually the timing controller of the LCD panel generates this signal. If this

switch between CPI and VGH provides isolation for the positive charge pump output VGH.
DLY2 sets the delay time for VGH to come up.

Power-on sequencing adjust. Connecting a capacitor from this pin to GND allows to set the
during startup.

Power-on sequencing adjust. Connecting a capacitor from this pin to GND allows to set the
delay time between the negative charge pump VGL and the positive charge pump during
startup. Note that Q5 in the Gate Voltage Shaping block only turns on when the positive
charge pump (FBP) is within regulation. (This provides input to output isolation of VGH).

Fault delay. Connecting a capacitor from this pin to Vin allows to set the delay time from
the point when one of the outputs (VS, VGH, VGL) drops below its power good threshold
until the devices enters the shutdown latch. To re-start the device the input voltage has to
be cycled to GND. This feature can be disabled by connecting the FDLY pin to Vin.

Active low open drain output. This output is latched low when the boost converter Vs is in
regulation. This signal can be used to drive an external MOSFET to provide isolation for Vs.

5

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TPS65150

SLVS576 – SEPTEMBER 2005

TERMINAL FUNCTIONS (continued)

TERMINAL

NAME

IN 14 11 I Input of the Vcom buffer. If this pin is connected to GND, the Vcom buffer is disabled.
PGND 10, 11 7, 8 Power ground
REF 23 20 O Internal reference output typically 1.213 V

SUP 12 9 I/O This pin needs to be connected to the output of the main boost converter and can’t be

SW 8, 9 5, 6 I Switch pin of the boost converter
VGH 18 15 O
VIN 7 4 I This is the input voltage pin of the device.

VCOM 13 10 O VCOM buffer output. Typically a 1-µF output capacitor is required on this pin.
PowerPAD

exposed thermal NA NA The PowerPAD
die

TM

,

NO. I/O DESCRIPTION

QFN TSSOP

Supply pin of the positive, negative charge pump and Boost Converter Gate Drive Circuit.
connected to any other voltage rail.

Positive output voltage to drive the TFT gates with an adjustable falltime. This pin is
internally connected with a MOSFET switch to the positive charge pump input CPI.

TM

needs to be soldered to GND

6

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0 0.1 0.2 0.3 0.4 0.5 0.6

100

90

80

70

60

50

40

VS = 13.5 V ,
VGH = VGL = No Load, Switching

VIN = 2.5 V

VIN = 3.3 V

VIN = 5 V

Efficiency − %

IO − Load Current − A

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

100

90

80

70

60

50

40

VS = 10 V ,
VGH = VGL = No Load, Switching

VIN = 2.5 V

VIN = 3.3 V

VIN = 5 V

Efficiency − %

IO − Load Current − A

TPS65150

SLVS576 – SEPTEMBER 2005

TYPICAL CHARACTERISTICS

TABLE OF GRAPHS

FIGURES

Main Boost Converter

η Efficiency vs Load current Vs=10 V 1
η Efficiency vs Load current Vs=13.5 V 2
η Efficiency vs Load current Vs=15 V 3

f

SW

Negative Charge Pump Driver

V

GL

Positive Charge Pump Driver

V

GH

V

GH

VCOM Buffer

Switching frequency vs Input voltage and temperature 4
PWM operation at nominal load current 5
PWM operation at light load current 6
Load transient response 7
Softstart boost converter 8
Power-on sequencing 9
Power-on sequencing External MOSFET in series to Vs 10
Gate voltage shaping of V

GH

Adjustable Fault detection 12

V

GL

V

GH

V

GH

vs load current 13

vs load current; Charge pump doubler stage 14
vs load current; Charge pump tripler stage 15

VCOM Buffer transconductance 16

11

EFFICIENCY EFFICIENCY

vs vs

LOAD CURRENT LOAD CURRENT

Figure 1. Figure 2.

7

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−40 −20 0 20 40 60 80 100 120

1.155

1.150

1.145

1.140

1.135

1.130

1.125

1.120

VS = 13.5 V

VIN = 7 V

VIN = 3.6 V

V

IN

= 1.8 V

f − Frequency − MHz

TA − Free-Air Temperature − C

0 0.05 0.1 0.15 0.2

100

90

80

70

60

50

40

Efficiency − %

IO − Load Current − A

0.25 0.3 0.35 0.4

VS = 15 V ,
VGH = VGL = No Load, Switching

VIN = 2.5 V

VIN = 3.3 V

VIN = 5 V

VIN = 5 V ,
VO = 13.5 V/300 mA

250 ns/div

V

SW

10 V/div

V

O

50 mV/div

I

L

1 A/div

V

SW

10 V/div

V

O

50 mV/div

I

L

1 A/div

VIN = 5 V
VO = 13.5 V/10 mA

250 ns/div

TPS65150

SLVS576 – SEPTEMBER 2005

EFFICIENCY SWITCHING FREQUENCY

vs vs

LOAD CURRENT TEMPERATURE

PWM OPERATION PWM OPERATION

NOMINAL LOAD CURRENT LIGHT LOAD CURRENT

Figure 3. Figure 4.

Figure 5. Figure 6.

8

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VO1

100 mV/div

I

O

30 mA to 330 mA

VIN = 3.3 V
VS = 10 V, CO = 22 F

100 s/div

V

IN

5 V/div

V

S

5 V/div

I

IN

500 mA/div

VIN = 5 V
VO = 13.5 V
I

out

= 200 mA

2.5 ms/div

V

S

5 V/div

VGH

10 V/div

VGL

5 V/div

VCOM

2 V/div

1 ms/div

VIN = 5 V
VO = 13.6 V/ 300 mA
VCOM CIN = 1 nF

V

S

5 V/div

VGH

10 V/div

VGL

5 V/div

VCOM

5 V/div

2.5 ms/div

LOAD TRANSIENT RESPONSE SOFT START BOOST CONVERTER

Figure 7. Figure 8.

TPS65150

SLVS576 – SEPTEMBER 2005

POWER-ON SEQUENCING POWER-ON SEQUENCING WITH

EXTERNAL ISOLATION MOSFET AT V

Figure 9. Figure 10.

S

9