Texas Instruments TPS40345EVM-353 User Manual

TPS40345EVM-353 Evaluation Module

1.2-V output at up to 20 A from a 12-V input bus. The EVM is designed to start-up from a single supply, which means no additional bias voltage is required for start-up. The module uses the TPS40345 high­performance, mid-input voltage synchronous buck controller and TI’s NexFET™ high performance MOSFETs.
Contents
1 Description.................................................................................................................... 3
1.1 Applications.......................................................................................................... 3
1.2 Features.............................................................................................................. 3
2 TPS40345EVM-353 Electrical Performance Specifications............................................................ 3
3 TPS40345EVM-353 Schematic............................................................................................ 4
4 Connector and Test Point Descriptions................................................................................... 5
4.1 Enable Jumper (JP2)............................................................................................... 5
4.2 Frequency Spread Spectrum – FSS Jumper (JP1) ............................................................ 5
4.3 Test Point Descriptions ............................................................................................ 5
5 Test Setup .................................................................................................................... 7
5.1 Equipment ........................................................................................................... 7
5.2 Equipment Setup.................................................................................................... 7
5.3 Start-Up/Shutdown Procedure .................................................................................... 9
5.4 Output Ripple Voltage Measurement Procedure ............................................................... 9
5.5 Control Loop Gain and Phase Measurement Procedure...................................................... 9
5.6 Equipment Shutdown ............................................................................................. 10
6 TPS40345EVM-353 Test Data ........................................................................................... 10
6.1 Efficiency ........................................................................................................... 10
6.2 Line and Load Regulation........................................................................................ 11
6.3 Output Voltage Ripple ............................................................................................ 11
6.4 Switch Node........................................................................................................ 12
6.5 Control Loop Bode Diagram ..................................................................................... 12
6.6 Additional Waveforms ............................................................................................ 13
7 TPS40345EVM-353 Assembly Drawings and Layout................................................................. 13
8 TPS40345EVM-353 Bill of Materials..................................................................................... 17
User's Guide
SNVU588–November 2017
1 TPS40345EVM-353 Schematic............................................................................................ 4
2 TPS40345EVM-353 Recommended Test Set-Up....................................................................... 8
3 Output Ripple Measurement – Tip and Barrel using TP3 and TP4................................................... 8
4 Control Loop Measurement Setup......................................................................................... 9
5 TPS40345EVM-353 Efficiency vs Load Current ....................................................................... 10
6 TPS40345EVM-353 Output Voltage vs Load Current................................................................. 11
7 TPS40345EVM-353 Output Voltage Ripple ............................................................................ 11
8 TPS40345EVM-353 Switching Waveforms............................................................................. 12
9 TPS40345EVM-353 Gain and Phase vs Frequency .................................................................. 12
10 TPS40345EVM-353 Output Ripple With FSS Enabled ............................................................... 13
11 TPS40345EVM-353 Component Placement (Top View) ............................................................. 14
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List of Figures
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12 TPS40345EVM-353 Silk Screen (Top View) ........................................................................... 14
13 TPS40345EVM-353 Top Copper (Top View)........................................................................... 15
14 TPS40345EVM-353 Bottom Copper (Top View)....................................................................... 15
15 TPS40345EVM-353 Internal 1 (X-Ray Top View) ..................................................................... 16
16 TPS40345EVM-353 Internal 2 (X-Ray Top View) ..................................................................... 16
1 TPS40345EVM-353 Electrical and Performance Specifications ...................................................... 3
2 Test Point Descriptions ..................................................................................................... 5
3 TPS40345EVM-353 Bill of Materials..................................................................................... 17
Trademarks
NexFET is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
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List of Tables
2
TPS40345EVM-353 Evaluation Module
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1 Description

The TPS40345EVM-353 is designed to use a regulated 12 V (8 V – 14 V) bus voltage to provide a regulated 1.2-V output at up to 20 A of load current. The TPS40345EVM-353 is designed to demonstrate the TPS40345 controller and TI NexFETs in a typical 12-V bus to low-voltage application while providing a number of non-invasive test points to evaluate the performance of the TPS40345 and TI NexFETs in a given application.

1.1 Applications

High-current, low-voltage FPGA or microcontroller core supplies
High-current point of load modules
Telecommunications equipment
Computer peripherals

1.2 Features

8-V to 14-V input voltage rating
1.2-V ± 2% output voltage rating
20-A steady state load current
600-kHz switching frequency
Simple access to IC features including power good, enable, soft start, and error amplifier
Convenient test points for simple, non-invasive measurements of converter performance
Description

2 TPS40345EVM-353 Electrical Performance Specifications

Table 1. TPS40345EVM-353 Electrical and Performance Specifications
PARAMETER NOTES AND CONDITIONS MIN TYP MAX UNIT
INPUTS CHARACTERISTICS
V
IN
I
IN
V
IN_UVLO
OUTPUTS CHARACTERISTICS
V
OUT1
V
OUT_ripple
I
OUT1
SYSTEMS CHARACTERISTICS
f
SW
ηpk Peak efficiency VIN= 12 V 88% η Full load efficiency VIN= 12 V, I
Input voltage 8 12 14 V Input current VIN= Nom, I No load input current VIN= Nom, I Input UVLO I
Output voltage 1 VIN= 12 V, I Line regulation VIN= 8 V to 14 V 0.5% Load regulation I Output voltage ripple VIN= 12 V, I Output current 1 VIN= 8 V to 14 V 0 20 A
Switching frequency 540 600 660 kHz
= 10 A 3.0 V
OUT
= 0 A to 20 A 0.5%
OUT
= Max 2.3 2.5 A
OUT
= 0A 40 50 mA
OUT
= 20 A 1.17 1.2 1.23 V
OUT
= 20 A 24 mVpp
OUT
= 20 A 86%
OUT
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TPS40345EVM-353 Schematic

3 TPS40345EVM-353 Schematic

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For reference only, See Table 3 for specific values
Figure 1. TPS40345EVM-353 Schematic
4
TPS40345EVM-353 Evaluation Module
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4 Connector and Test Point Descriptions

4.1 Enable Jumper (JP2)

The TPS40345EVM-353 is designed with a Disable Jumper (JP2) using a 0.1-inch spacing header and shunt. Installing a shunt in the JP2 position connects the EN/SS pin to GND, discharges the soft-start capacitor, and disables the TPS40304 controller. This forces the output into a high-impedance state (approximately 20kΩ to GND).

4.2 Frequency Spread Spectrum – FSS Jumper (JP1)

The TPS40345EVM-353 is designed with a frequency spread spectrum (FSS) enable jumper (JP1) using a 0.1" spacing header and shunt. Installing a shunt in the JP1 position connects the EN/SS pin to BP via a 267-kΩ resistor (R10) to enable frequency spread spectrum.
FSS modulates the switching frequency to ±10% of the nominal value at 30 kHz to reduce EMI at the switching frequency and its harmonics, however there may be a 30-kHz component to the output ripple (see Figure 10).
The TPS40345EVM-353 does not dynamically monitor the JP1 status for programming FSS. The TPS40345EVM-353 must be disabled via JP2 or powered down by reducing VIN to less than 3 V to remove or install JP1.

4.3 Test Point Descriptions

Connector and Test Point Descriptions
Table 2. Test Point Descriptions
TEST
POINT
TP1 VIN Measurement test point for input voltage 4.3.1 TP2 GND Ground test point for input voltage 4.3.1 TP3 VOUT Measurement test point for output voltage 4.3.1 TP4 GND Ground test point for output voltage 4.3.2 TP5 CHB Measurement test point for channel B of loop response 4.3.3 TP6 SGND Ground test point for channel B of loop response 4.3.3 TP7 CHA Measurement test point for channel A of loop response 4.3.3 TP8 SGND Ground test point for channel A of loop response 4.3.3
TP9 SGND Ground test point for error amplifier measurements 4.3.4 TP10 COMP Measurement test point for error amplifier output voltage 4.3.4 TP11 FB Measurement test point for error amplifier input voltage 4.3.4 TP12 HDRV Measurement test point for high-side gate driver voltage 4.3.5 TP13 SW Measurement test point for switching node voltage 4.3.5 TP14 LDRV Measurement test point for low-side gate driver voltage 4.3.5 TP15 PGND Ground test point for switch node and gate drive voltages 4.3.5 TP16 PGOOD Measurement test point for power good 4.3.6 TP17 EN/SS Measurement test point for enable / soft start 4.3.7 TP18 SGND Ground test point for power good and enable / soft start 4.3.6 and 4.3.7
LABEL USE SECTION
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Connector and Test Point Descriptions
4.3.1 Input Voltage Monitoring (TP1 and TP2)
The TPS40345EVM-353 provides two test points for measuring the input voltage applied to the module. This allows the user to measure the actual input module voltage without losses from input cables and connectors. All input voltage measurements should be made between TP1 and TP2. To use TP1 and TP2, connect a voltmeter positive input to TP1 and input terminal to TP2.
4.3.2 Output Voltage Monitoring (TP3 and TP4)
The TPS40345EVM-353 provides two test points for measuring the output voltage generated by the module. This allows the user to measure the actual module output voltage without losses from input cables and connectors. All input voltage measurements should be made between TP3 and TP4. To use TP3 and TP4, connect a voltmeter positive input to TP3 and negative input to TP4.
4.3.3 Loop Response Testing (TP5, TP6, TP7, TP8, and R3)
The TPS40345EVM-353 provides four test points (2 signal and 2 ground) for measuring the control loop frequency response. This allows the user to measure the actual module loop response without modifying the evaluation board. A transformer isolated signal up to 30 mV can be injected between TP5 and TP7. The injected signal amplitude can be measured by the ac coupled amplitude at CHA (TP7) and the resulting output voltage deviation can be measured at CHB (TP5). See Figure 4 for additional detail.
4.3.4 Error Amplifier Voltage Monitoring (TP9, TP10, and TP11)
The TPS40345EVM-353 provides three test points for measuring the error amplifier input and output voltages. This allows the user to directly measure the feedback and control voltages of the TPS40304 controller. The control voltage (TP10) can also be used to measure the control to output or power-stage frequency response or output to control or error amplifier frequency response. See Section 5.5 for additional details.
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4.3.5 Switching Waveform Monitoring (TP12, TP13, TP14, and TP15)
The TPS40345EVM-353 provides three test points and a local power ground for measuring the switching waveforms of the module power stage. This allows the user to monitor actual switching waveforms during operation. TP13 is a 0.040-inch square pad of exposed PCB copper to minimize EMI radiation from the high transient voltages on the switch node. Switching waveform measurements should be made using power ground (TP15) as the ground reference for more accurate measurements.
4.3.6 Power-Good Voltage Monitoring (TP16 and TP18)
The TPS40345EVM-353 provides a test point and local ground for measuring the power good output voltage. A 100-kΩ resistor pullup to BP (R9) is included to allow the power-good signal to be monitored without requiring an external pull-up. For true open-drain operation with no pullup, remove R9. With R9 removed, TP16 can be connected to TP17 of another TPS40345EVM-353 to provide sequential start-up of the two TPS40345EVM-353 converters.
4.3.7 Enable and Soft-Start Voltage Monitoring (TP17 and TP18)
The TPS40345EVM-353 provides a test point and local ground for measuring the enable and soft-start voltage. TP17 and TP18 or JP2 can be used to provide an external enable signal. Due to the nature of the soft-start function, the external signal must be open-collector or open-drain without pullup.
6
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5 Test Setup

5.1 Equipment

5.1.1 Voltage Source
VIN— The input voltage source (VIN) must be a 0-V to 15-V variable DC source capable of supplying 5 Adc.
5.1.2 Meters
A1: — Input current meter. 0 Adc – 5 Adc ammeter V1: — Input voltage meter. 0 V – 15 V voltmeter V2: — Output voltage meter. 0 V – 2 V voltmeter
5.1.3 Load
LOAD1: — Output load. Electronic load set for constant current or constant resistance capable of 0 Adc – 20 Adc at 1.2-Vdc.
5.1.4 Oscilloscope
For output voltage ripple: — Oscilloscope must be an analog or digital oscilloscope set for ac-coupled measurement with 20-MHz bandwidth limiting. Use 20 mV/division vertical resolution, 1-µs/division horizontal resolution.
For switching waveforms: — Oscilloscope shall be an analog or digital oscilloscope set for dc coupled measurement with 20-MHz bandwidth limiting. Use 2 V/division or 5V/division vertical resolution and 1­µs/division horizontal resolution.
Test Setup
5.1.5 Recommended Wire Gauge
VIN to J1: — The connection between the source voltage (VIN) and J1 of TPS40345EVM-353 can carry as much as 3.5 Adc of current. The minimum recommended wire size is AWG #16 with the total length of wire less than 2 feet (1 foot input, 1 foot return).
J2 to LOAD1: — The connection between the source voltage (VIN) and J1 of TPS40345EVM-353 can carry as much as 20 Adc of current. The minimum recommended wire size is AWG #12 with the total length of wire less than 2 feet (1 foot input, 1 foot return).
5.1.6 Other
FAN: — The TPS40345EVM-353 evaluation module includes components that can get hot to the touch when operating. Because this evaluation module is not enclosed to allow probing of circuit nodes, TI recommends a small fan capable of 200 lfm – 400 lfm to reduce component temperatures when operating.

5.2 Equipment Setup

Shown in Figure 2 is the basic test set up recommended to evaluate the TPS40345EVM-353. Note that although the return for J1 and JP2 are the same system ground, the connections should remain separate as shown in Figure 2.
5.2.1 Procedure
1. Working at an ESD workstation, make sure that any wrist straps, bootstraps, or mats are connected referencing the user to earth ground before power is applied to the EVM. Electrostatic smock and safety glasses should also be worn.
2. Prior to connecting the dc input source, VIN, it is advisable to limit the source current from VINto 4 A, maximum. Make sure VINis initially set to 0 V and connected as shown in Figure 2.
3. Connect VIN to J1 as shown in Figure 2.
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