TEXAS INSTRUMENTS TPS40303, TPS40304, TPS40305 Technical data

5

4

3

2

6

7

8

9

BOOT

HDRV

SW

LDRV/OC

FB

COMP

PGOOD

EN/SS

TPS4030x

1 10BPVDD

PAD

V

IN

SD

V

OUT

V

IN

UDG-09158

V

OUT

GND

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TPS40303, TPS40304, TPS40305

SLUS964 –NOVEMBER 2009

3-V TO 20-V INPUT SYNCHRONOUS BUCK CONTROLLER

Check for Samples :TPS40303 TPS40304 TPS40305

1

FEATURES

• Input Voltage Range from 3 V to 20 V

• 300 KHz (TPS40303), 600 KHz (TPS40304) and

1.2 MHz (TPS40305) Switching Frequencies

• High- and Low-Side FET R

DS(on)

Current

Sensing

• Programmable Thermally Compensated OCP
Levels

• Programmable Soft-Start

• 600 mV, 1% Reference Voltage

• Voltage Feed-Forward Compensation

• Supports Pre-Biased Output

• Frequency Spread Spectrum

• Thermal Shutdown Protection at 145°C

CONTENTS

Device Ratings 2
Electrical Characteristics 3
Device Information 8
Application Information 10
Design Examples 14
Additional References 24

X

APPLICATIONS

• POL Modules

• Printer

• Digital TV

• Telecom

• 10-Pin 3 mm × 3 mm SON Package with
Ground Connection to Thermal Pad

DESCRIPTION

The TPS4030x is a family of cost-optimized synchronous buck controllers that operate from 3-V to 20-V input.
The controller implements a voltage-mode control architecture with input-voltage feed-forward compensation that
responds instantly to input voltage change. The switching frequency is fixed at 300 KHz, 600 KHz or 1.2 MHz.

Frequency Spread Spectrum feature adds dither to the switching frequency, significantly reducing the peak EMI
noise and making it much easier to comply with EMI standards.

The TPS4030x offers design with a variety of user programmable functions, including soft-start, Over- Current
Protection (OCP) levels, and loop compensation.

OCP level may be programmed by a single external resistor connected from LDRV pin to circuit ground. During
initial power on, the TPS4030x enters a calibration cycle, measures the voltage at the LDRV pin, and sets an
internal OCP voltage level. During operation, the programmed OCP voltage level is compared to the voltage drop
across the low side FET when it is on to determine whether there is an overcurrent condition. The TPS4030x
then enters a shutdown and restart cycle until the fault is removed.

SIMPLIFIED APPLICATION DIAGRAM

1

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2009, Texas Instruments Incorporated

TPS40303, TPS40304, TPS40305

SLUS964 –NOVEMBER 2009

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ORDERING INFORMATION

OPERATING FREQUENCY PACKAGE TAPE AND REEL QUANTITY PART NUMBER

1.2 MHz

600 kHz Plastic 10-Pin SON (DRC)

300 kHz

250 TPS40305DRCT

3000 TPS40305DRCR

250 TPS40304DRCT

3000 TPS40304DRCR

250 TPS40303DRCT

3000 TPS40303DRCR

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ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

VDD –0.3 to 22 V
SW –3 to 27 V
SW (< 100 ns pulse width, 10 µJ) –5 V
BOOT –0.3 to 30 V
HDRV –5 to 30 V
BOOT-SW, HDRV-SW (differential from BOOT or HDRV to SW) –0.3 to 7 V
COMP, PGOOD, FB, BP, LDRV, EN/SS –0.3 to 7 V

T

Operating junction temperature range –40 to 145 °C

J

T

Storage temperature –55 to 150 °C

stg

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other condition beyond those included under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods of time may affect device reliability.

(1)

VALUE UNIT

DISSIPATION RATINGS

R

HIGH-K BOARD

PACKAGE AIRFLOW (LFM)

0 (Natural Convection) 47.9 2.08 0.835

10-Pin SON (DRC) 200 40.5 2.46 0.987

400 38.2 2.61 1.04

(1) Ratings based on JEDEC High Thermal Conductivity (High K) Board. For more information on the test method, see TI technical brief

(SZZA017).

θJA

(°C/W) TA= 25°C TA= 85°C

(1)

POWER RATING (W) POWER RATING (W)

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT

VDD Input voltage 3 20 V
T

Operating junction temperature –40 125 °C

J

ELECTROSTATIC DISCHARGE (ESD) PROTECTION

MIN TYP MAX UNIT

Human body model (HBM) 2000 V
Charge device model (CDM) 1500 V

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ELECTRICAL CHARACTERISTICS

TJ= –40°C to 125°C, V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VOLTAGE REFERENCE

V

FB

INPUT SUPPLY

V

VDD

IDD

SD

IDD

Q

ENABLE/SOFT-START

V

IH

V

IL

I

SS

V

SS

BP REGULATOR

V

BP

V

DO

OSCILLATOR

f

SW

V

RAMP

f

SWFSS

f

MOD

PWM

(1)

D

MAX

t

ON(min)

t

DEAD

ERROR AMPLIFIER

(1)

G

BWP

(1)

A

OL

I

IB

I

EAOP

I

EAOM

(1) Ensured by design. Not production tested.

FB input voltage mV

Input supply voltage range 3 20 V
Shutdown supply current V
Quiescent, non-switching Let EN/SS float, VFB= 1 V 2.5 3.5 mA

High-level input voltage, EN/SS 0.55 0.70 1.00 V
Low-level input voltage, EN/SS 0.27 0.30 0.33 V
Soft-start source current 8 10 12 µA
Soft-start voltage level 0.4 0.8 1.3 V

Output voltage IBP= 10 mA 6.2 6.5 6.8 V
Regulator dropout voltage, V

PWM frequency TPS40304 3 V < V

(1)

Ramp amplitude V
Frequency spread spectrum frequency

deviation
Modulation frequency 25 KHz

Maximum duty cycle TPS40304 VFB= 0 V, 3 V < V

(1)

Minimum controllable pulse width 100 ns

Output driver dead time ns

Gain bandwidth product 10 24 MHz
Open loop gain 60 dB
Input bias current (current out of FB pin) VFB= 0.6 V 75 nA
Output source current VFB= 0 V 2
Output sink current VFB= 1 V 2

= 12 V, all parameters at zero power dissipation (unless otherwise noted)

VDD

VDD

TPS40303 270 300 330 kHz

TPS40305 1.02 1.20 1.38 MHz

TPS40303 90%

TPS40305 85%

– V

TPS40303, TPS40304, TPS40305

SLUS964 –NOVEMBER 2009

TJ= 25°C, 3 V < V
–40°C < TJ< 125°C, 3 V < V

V

< 0.2 V 70 100 µA

EN/SS

BPIBP

= 25 mA, V

< 20 V 540 600 660 kHz

VDD

HDRV off to LDRV on 5 25 35
LDRV off to HDRV on 5 25 30

< 20 V 597 600 603

VDD

< 20 594 600 606

VDD

= 3 V 70 110 mV

VDD

/6.6 V

VDD

VDD

12% f

< 20 V 90%

VDD

/6 V

/5.4 V

VDD

SW

mA

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TPS40303, TPS40304, TPS40305

SLUS964 –NOVEMBER 2009

ELECTRICAL CHARACTERISTICS (continued)

TJ= –40°C to 125°C, V

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

PGOOD

V

OV

V

UV

V

PGD-HYST

R

PGD

I

PGDLK

OUTPUT DRIVERS

R

HDHI

R

HDLO

R

LDHI

R

LDLO

(2)

t

HRISE

(2)

t

HFALL

(2)

t

LRISE

(2)

t

LFALL

OVERCURRENT PROTECTION

t

PSSC(min)

t

BLNKH

V

OCH

I

OCSET

V

LD-CLAMP

V

OCLOS

V

OCLPRO

(2)

V

THTC

t

OFF

BOOT DIODE

V

DFWD

THERMAL SHUTDOWN

(2)

T

JSD

(2)

T

JSDH

(2) Ensured by design. Not production tested.

Feedback upper voltage limit for
PGOOD

Feedback lower voltage limit for mV
PGOOD

PGOOD hysteresis voltage at FB 25 40
PGOOD pull down resistance VFB= 0 V, IFB= 5 mA 30 70 Ω

PGOOD leakage current 10 20 µA

High-side driver pull-up resistance V
High-side driver pull-down resistance V
Low-side driver pull-up resistance I
Low-side driver pull-down resistance I
High-side driver rise time C
High-side driver fall time 12 ns
Low-side driver rise time 15 ns
Low-side driver fall time 10 ns

(2)

Minimum pulse time during short circuit 250 ns

(2)

Switch leading-edge blanking pulse time 150 ns
OC threshold for high side FET TJ= 25°C 360 450 580 mV
OCSET current source TJ= 25°C 9.5 10.0 10.5 µA
Maximum clamp voltage at LDRV 260 340 400 mV
OC comparator offset voltage for low

side FET
Programmable OC range for low side

(2)

FET
OC threshold temperature coefficient

(both high side and low side)
OC retry cycles on EN/SS pin 4 Cycle

Bootstrap diode forward voltage I

Junction shutdown temperature 145 °C
Hysteresis 20 °C

= 12 V, all parameters at zero power dissipation (unless otherwise noted)

VDD

550 mV < VFB< 655 mV,
V

PGOOD

BOOT
BOOT

= -100 mA 0.8 1.5 2.5 Ω

LDRV

= 100 mA 0.35 0.60 1.20 Ω

LDRV

LOAD

TJ= 25°C –8 8 mV

TJ= 25°C 12 300 mV

= 5 mA 0.8 V

BOOT

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655 675 700

500 525 550

= 5 V

– VSW= 5 V, I
– VSW= 5 V, I

= –100 mA 0.8 1.5 2.5 Ω

HDRV

= 100 mA 0.5 1.0 2.2 Ω

HDRV

= 5 nF 15 ns

3000 ppm

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305

306

307

308

309

310

311

312

313

314

–40 20–25 –10 5 65 12580 95 11035 50

TJ– Junction Temperature – °C

f

SW

– Switching Frequency – kHz

TPS40303

V

VDD

= 3V

V

VDD

= 12 V

V

VDD

= 20 V

580

585

590

595

600

605

610

615

620

625

V

VDD

= 3V

V

VDD

= 20 V

–40 20–25 –10 5 65 12580 95 11035 50

TJ– Junction Temperature – °C

TPS40304

f

SW

– Switching Frequency – kHz

V

VDD

= 12 V

–40 20–25 –10 5 65 12580 95 11035 50

TJ– Junction Temperature – °C

I

DDQ

– Quiescent Current – mA

2.12

2.14

2.16

2.18

2.20

2.22

2.24

V

VDD

= 12 V

1

1.05

1.1

1.15

1.2

1.25

1.3

1.35

1.4

V

VDD

= 3V

V

VDD

= 20 V

V

VDD

= 12 V

TJ– Junction Temperature – °C

f

SW

– Switching Frequency – MHz

–40 20–25 –10 5 65 12580 95 11035 50

TPS40305

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TPS40303, TPS40304, TPS40305

SLUS964 –NOVEMBER 2009

TYPICAL CHARACTERISTICS

SWITCHING FREQUENCY SWITCHING FREQUENCY

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

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Figure 1. Figure 2.

SWITCHING FREQUENCY QUIESCENT CURRENT

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 3. Figure 4.

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TJ– Junction Temperature – °C

I

DD(SD)

– Shutdown Current – mA

–40 20–25 –10 5 65 12580 95 11035 50

58

60

62

64

66

68

70

72

V

VDD

= 12 V

–40 20–25 –10 5 65 12580 95 11035 50

TJ– Junction Temperature – °C

I

OCSET

– OCSET Current Source– mA

6

7

8

9

10

11

12

13

14

–40 20

599.4

599.6

599.8

600

600.2

600.4

600.6

600.8

–25 –10 5 65 12580 95 11035 50

V

FB

– Feedback Reference Voltage – mV

TJ– Junction Temperature – °C

–40 20–25 –10 5 65 12580 95 11035 50

TJ– Junction Temperature – °C

V

IH

– Enable High-Level Threshold Voltage – mV

620

640

660

680

700

720

740

TPS40303, TPS40304, TPS40305

SLUS964 –NOVEMBER 2009

TYPICAL CHARACTERISTICS (continued)

SHUTDOWN CURRENT OCSET CURRENT SOURCE

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

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Figure 5. Figure 6.

FEEDBACK REFERENCE VOLTAGE ENABLE HIGH-LEVEL THRESHOLD VOLTAGE

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 7. Figure 8.

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TJ– Junction Temperature – °C

V

OCH

– High-Side Overcurrent Threshold – mV

–40 20–25 –10 5 65 12580 95 11035 50

350

400

450

500

550

600

–40 20–25 –10 5 65 12580 95 11035 50

TJ– Junction Temperature – °C

300.0

300.5

301.0

301.5

302.0

302.5

303.0

V

IL

– Enable Low-Level Threshold Voltage – mV

–40 20–25 –10 5 65 12580 95 11035 50

TJ– Junction Temperature – °C

V

OV

/V

UV

– Power Good Threshold Voltage – mV

400

450

500

550

600

650

700

750

800

Undervoltage

Overvoltage

750

775

800

825

850

875

900

925

950

975

1000

–40 20–25 –10 5 65 12580 95 11035 50

TJ– Junction Temperature – °C

V

SS

– Soft-Start Voltage – mV

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TPS40303, TPS40304, TPS40305

SLUS964 –NOVEMBER 2009

TYPICAL CHARACTERISTICS (continued)

ENABLE LOW-LEVEL THRESHOLD VOLTAGE HIGH-SIDE OVERCURRENT THRESHOLD

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

Copyright © 2009, Texas Instruments Incorporated Submit Documentation Feedback 7

Figure 9. Figure 10.

POWER GOOD THRESHOLD VOLTAGE SOFT-START VOLTAGE

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 11. Figure 12.

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5 4 3 2 1

6 7 8 9 10

FB COMP PGOOD EN/SS VDD

BOOT HDRV SW

LDRV/

OC

BP

Thermal Pad

TPS40303, TPS40304, TPS40305

SLUS964 –NOVEMBER 2009

DEVICE INFORMATION

TERMINAL CONFIGURATION

The package is an 10-Pin SON (DRC) package. Note: The thermal pad is an electrical ground connection.

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TERMINAL

NAME NO.

BOOT 6 I between this pin and SW. For low input voltage operation, an external schottky diode from BP to BOOT is

BP 10 O
COMP 4 O Output of the error amplifier and connection node for loop feedback components.

EN/SS 2 I

FB 5 I
PGOOD 3 O Open drain power good output.

HDRV 7 O Bootstrapped gate drive output for the high side N-channel MOSFET.

LDRV/OC 9 O is also used to determine the voltage level for OCP. An internal current source of 10 µA flows through the

VDD 1 I

SW 8 O

GND

Thermal connection serves a twofold purpose. The first is to provide an electrical ground connection for the device.

Pad The second is to provide a low thermal impedance path from the device die to the PCB. This pad should be

PIN FUNCTIONS

I/O DESCRIPTION

Gate drive voltage for the high side N-channel MOSFET. A 100 nF capacitor (typical) must be connected
recommended to maximize the gate drive voltage for the high-side.

Output bypass for the internal regulator. Connect a low ESR bypass ceramic capacitor of 1 µF or greater from
this pin to GND.

Logic level input which starts or stops the controller via an external user command. Letting this pin float turns
the controller on. Pulling this pin low disables the controller. This is also the soft-start programming pin. A
capacitor connected from this pin to GND programs the soft-start time. The capacitor is charged with an
internal current source of 10 µA. The resulting voltage ramp of this pin is also used as a second non-inverting
input to the error amplifier after a 0.8 V (typical) level shift downwards. Output regulation is controlled by the
internal level shifted voltage ramp until that voltage reaches the internal reference voltage of 600 mV – the
voltage ramp of this pin reaches 1.4 V (typical). Optionally, a 267 kΩ resistor from this pin to BP enables
frequency spread spectrum feature.

Inverting input to the error amplifier. In normal operation, the voltage on this pin is equal to the internal
reference voltage.

Gate drive output for the low side synchronous rectifier N-channel MOSFET. A resistor from this pin to GND
resistor during initial calibration and that sets up the voltage trip point used for OCP.

Power input to the controller. Bypass VDD to GND with a low ESR ceramic capacitor of at least 1.0-µF close
to the device.

Sense line for the adaptive anti-cross conduction circuitry. Serves as common connection for the flying high
side FET driver.

Ground connection to the controller. This is also the thermal pad used to conduct heat from the device. This

tied externally to a ground plane.

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BOOT

SW

LDRV/OC

EN/SS

COMP

FB

GND

VDD

BP

PGOOD

2

1

10

4

5

3

6

7

8

9

PAD

HDRV

+

+

FB

0.6 V

REF

+ 12.5%

0.6 V

REF

–12.5%

+

Fault

Controller

SS

Soft Start

BP

Anti-Cross

Conduction

and

Pre-Bias

Circuit

PWM
Logic

BP

Clock

6-V

Regulator

References

0.6 V

REF

SD

BP

Spread
Spectrum
Oscillator

+

Calibration

Circuit

+

UDG-09160

0.6 V

REF

SS

10 mA

750 kW

Fault Controller

Thermal

Shutdown

OC

Threshold

Setting

10 mA

OC

SS

SD

PWM

Clock

OC

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TPS4030x BLOCK DIAGRAM

TPS40303, TPS40304, TPS40305

SLUS964 –NOVEMBER 2009

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0

0.4

0.7 V

0.8

1.3 V

1.2

1.6

2.0

V

EN/SS

t – Time – ms

Calibration

Time

1.9 ms

V

IN

– Input Voltage – V

V

SS_INT

UDG-09159

TPS40303, TPS40304, TPS40305

SLUS964 –NOVEMBER 2009

APPLICATION INFORMATION

Introduction

The TPS4030x is a family of cost-optimized synchronous buck controllers providing high-end features to
construct high-performance DC/DC converters. Pre-bias capability eliminates concerns about damaging sensitive
loads during startup. Programmable over-current protection levels and hiccup over-current fault recovery
maximize design flexibility and minimize power dissipation in the event of a prolonged output short. Frequency
Spread Spectrum (FSS) feature reduces peak EMI noise by spreading the initial energy of each harmonic along
a frequency band, thus giving a wider spectrum with lower amplitudes.

Voltage Reference

The 600 mV band gap cell is internally connected to the non-inverting input of the error amplifier. The reference
voltage is trimmed with the error amplifier in a unity gain configuration to remove amplifier offset from the final
regulation voltage. The 1% tolerance on the reference voltage allows the user to design a very accurate power
supply.

Enable Functionality, Startup Sequence and Timing

After input power is applied, an internal current source of 40 µA starts to charge up the soft-start capacitor
connected from EN/SS to GND. When the voltage across that capacitor increases to 0.7 V, it enables the internal
BP regulator followed by a calibration. The total calibration time is about 1.9 ms. See Figure 13. During the
calibration, the device performs in the following way. It disables the LDRV drive and injects an internal 10 µA
current source to the resistor connected from LDRV to GND. The voltage developed across that resistor is then
sampled and latched internally as the OCP trip level until one cycles the input or toggles the EN/SS.

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The voltage at EN/SS is internally clamped to 1.3 V before and/or during calibration to minimize the discharging
time once calibration is complete. The discharging current is from an internal current source of 140 µA and it
pulls the voltage down to 0.4 V. It then initiates the soft-start by charging up the capacitor using an internal
current source of 10 µA. The resulting voltage ramp on this pin is used as a second non-inverting input to the
error amplifier after an 800 mV (typical) downward level-shift; therefore, actual soft-start will not take place until
the voltage at this pin reaches 800 mV.

Figure 13. Startup Sequence and Timing

If EN/SS is left floating, the controller starts automatically. EN/SS must be pulled down to less than 270 mV to
guarantee that the chip is in shutdown mode.

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