TEXAS INSTRUMENTS TPS40060, TPS40061 Technical data

8

V

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SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

WIDE-INPUT SYNCHRONOUS BUCK CONTROLLER

FEATURES DESCRIPTION

• Operating Input Voltage 10 V to 55 V

• Input Voltage Feed-Forward Compensation

• < 1% Internal 0.7-V Reference

• Programmable Fixed-Frequency, Up to 1-MHz

Voltage Mode Controller

• Internal Gate Drive Outputs for High-Side
P-Channel and Synchronous N-Channel
MOSFETs

• 16-Pin PowerPAD™ Package (θJC=2°C/W)

• Thermal Shutdown

• Externally Synchronizable

• Programmable High-Side Sense Short Circuit

Protection

• Programmable Closed-Loop Soft-Start

• TPS40060 Source Only/TPS40061 Source/Sink

The TPS40060 and TPS40061 are high-voltage, wide
input (10 V to 55 V) synchronous, step-down con­verters.

This family of devices offers design flexibility with a
variety of user programmable functions, including;
soft-start, UVLO, operating frequency, voltage
feed-forward, high-side current limit, and loop com­pensation. These devices are also synchronizable to
an external supply.

The TPS40060 and TPS40061 incorporate MOSFET
gate drivers for external P-channel high-side and
N-channel synchronous rectifier (SR) MOSFETs.
Gate drive logic incorporates anti-cross conduction
circuitry to prevent simultaneous high-side and
synchronous rectifier conduction.

TPS40060
TPS40061

APPLICATIONS

• Networking Equipment

• Telecom Equipment

• Base Stations

• Servers

SIMPLIFIED APPLICATION DIAGRAM

TPS40060PWP

1

KFF

2

IN

RT

3

BP5

4

SYNC

5

SGND

SS/SD

VFB

7

COMP

8

HDRV

BPN10

LDRV

PGND

ILIM

VIN

SW

BP10

16

15

14

13

12

116

10

+

V

OUT

9

-

UDG-02157

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Copyright © 2002–2004, Texas Instruments Incorporated

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TPS40060
TPS40061

SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

T

A

–40°Cto85°C

(1) The PWP package is alsoavailable taped and reeled. Add an R suffix to the device type (i.e.,TPS40060PWPR). See the application

section of the data sheet for PowerPADdrawing and layout information.

(2) See ApplicationInformation section.

LOAD CURRENT PACKAGE

SOURCE

SOURCE/SIN

(2)

(2)

Plastic HTSSOP (PWP) TPS40060PWP

Plastic HTSSOP (PWP) TPS40061PWP

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

VIN 60 V

VFB, SS/SD, SYNC –0.3 V to 6 V

V

V

I

I

T

T

(1) Stresses beyond thoselisted under "absolute maximum ratings" may cause permanent damage to thedevice. These are stress ratings

Input voltage range

IN

Output voltage range COMP, RT, KFF, SS –0.3 V to 6 V

OUT

Input current KFF 5mA

IN

Output current RT 200 µA

OUT

Operating junction temperature range –40°C to 125°C

J

Storage temperature –55°C to 150°C

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C

only, and functional operation of the deviceat these or any other conditions beyond those indicated under "recommendedoperating
conditions" is not implied. Exposure to absolute-maximum-ratedconditions for extended periods may affect devicereliability.

SW

SW. transient < 50 ns –2.5 V

(1)

(1)

PART NUMBER

TPS40060
TPS40061

–0.3 V to 60 V or VIN+5 V

(whichever is less)

RECOMMENDED OPERATING CONDITIONS

V

T

2

Input voltage 10 55 V

IN

Operating free-air temperature –40 85 °C

A

PAD

(1)(2)

16
15
14
13
12
11
10

ILIM
VIN
HDRV
BPN10
SW
BP10
LDRV

9

PGND

PWP PACKAGE

(TOP VIEW)

KFF

RT

BP5

SYNC

SGND

SS/SD

VFB

COMP

(1) For more information on the PWP package, refer to TI Technical Brief (SLMA002).

(2) PowerPAD™ heat slug must be connected to SGND (Pin 5), or electrically isolated from all other pins.

1
2
3
4
5
6
7
8

THERMAL

MIN NOM MAX UNIT

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ELECTRICAL CHARACTERISTICS

TA= –40°Cto85°C, VIN=24Vdc,RT= 165 kΩ,I
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INPUT SUPPLY

V

OPERATING CURRENT

I

5-V REFERENCE

V

OSCILLATOR/RAMP GENERATOR

f

V

V

V

I

V

V

I

SS/SD (SOFT START)

I

V

t

t

SS/SD (SHUTDOWN)

V

V

10-V REFERENCE

V

ERROR AMPLIFIER

V

G

A

I

I

I

V

V

(1) KFF current(I
(2) Ensured by design. Notproduction tested.
(3) Ensured by design. Notproduction tested.

Input voltage range, VIN 10 55 V

IN

Quiescent current Output drivers not switching 1.5 2.5 mA

DD

Input voltage 4.5 5.0 5.5 V

BP5

Frequency 270 300 330 kHz

OSC

PWM ramp voltage

RAMP

High-level input voltage, SYNC 2V

IH

Low-level input voltage, SYNC 0.8

IL

Input current, SYNC 510µA

SYNC

(2)

(1)

Pulse width, SYNC Pulse amplitude = 5 V 50 ns

RT voltage 2.32 2.50 2.68 V

RT

Maximum duty cycle VFB= 0 V, 100 kHz ≤ fSW≤ 1 MHz 85% 98%

Minumum duty cycle VFB≥ 0.75 V 0%

Feed-forward voltage 3.35 3.50 3.65 V

KFF

Feed-forward current operating range

KFF

Soft-start source current 1.8 2.3 2.9 µA

SS

Soft-start clamp voltage 3.1 3.7 4.0 V

SS

Discharge time CSS= 220 pF 1.8 2.2 2.8

DSCH

Soft-start time CSS= 220 pF, 0 V ≤ VSS≤ 1.6 V 120 155 190

SS

Shutdown threshold voltage 90 120 145 mV

SD

Device action threshold voltage 160 210 260 mV

EN

Input voltage 9.0 9.7 10.7 V

BP10

Feedback regulation voltage 0°C ≤ TA≤ 85°C 0.690 0.700 0.707 V

FB

Gain bandwidth 3 5 MHz

BW

Open loop gain 60 80 dB

VOL

High-level output source current V

OH

Low-level output sink current V

OL

Input bias current VFB= 0.7 V 100 300 nA

BIAS

High-level output voltage IOH= 0.5 mA, VFB= 0 V 3.25 3.45 3.60

OH

Low-level output voltage IOL= 0.5 mA, VFB= 1 V 0.050 0.215 0.350

OL

) increases with SYNC frequency(f

KFF

(3)

TPS40060
TPS40061

SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

= 113 µA, fSW= 300 kHz, all parameters at zero power dissipation (unless

KFF

2

20 1100 µA

TA=25°C 0.698 0.700 0.704

0.690 0.700 0.715

= 2.0 V, VFB=0V 1.5 4.0

COMP

= 2.0 V, VFB=1V 2.5 4.0

COMP

) and decreases with maximum dutycycle (D

SYNC

MAX

).

µs

mA

V

3

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TPS40060
TPS40061

SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

ELECTRICAL CHARACTERISTICS (continued)

TA= –40°Cto85°C, VIN=24Vdc,RT= 165 kΩ,I
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CURRENT LIMIT

I

t

t

t

V

OUTPUT DRIVER

t

t

t

t

V

V

V

V

BPN10 REGULATOR

V

0

RECTIFIER ZERO CURRENT COMPARATOR (TPS40060 ONLY)

V

SW NODE

I

THERMAL SHUTDOWN

T

UNDERVOLTAGE LOCKOUT

V

V

Current limit sink current 8.3 10.0 11.5 µA

SINK

Propagation delay to output

DELAY

Switch leading-edge blanking pulse time

ON

Off time during a fault 7 cycles

OFF

Overcurrent comparator offset voltage -200 -60 50 mV

OS

High-side driver fall time

HFALL

High-side driver rise time

HRISE

Low-side driver fall time

LFALL

Low-side driver rise time

LRISE

High-level ouput voltage, HDRV I

OH

Low-level ouput voltage, HDRV I

OL

High-level ouput voltage, LDRV I

OH

Low-level ouput voltage, LDRV I

OL

(4)

(4)

(4)

(4)

(4)

Minimum controllable pulse width 100 150 ns

BPN1

Output voltage Outputs off –7.5 –8.5 –9.5 V

Switch voltage LDRV output OFF –6 0 6 mV

SW

Leakage current

LEAK

Shutdown temperature

SD

Hysteresis

Undervoltage lockout threshold voltage, BP10 R

UVLO

(4)

(4)

(4)

Undervoltage lockout hysteresis 0.4 V

KFF programmable threshold voltage R

KFF

= 113 µA, fSW= 300 kHz, all parameters at zero power dissipation (unless

KFF

V

= 23.7 V, VSW=(V

ILIM

V

= 23.7 V, VSW=(V

ILIM

C

HDRV

C

HDRV

C

LDRV

C

LDRV

=0.1A,(VIN–V

HDRV

=0.1A,(V

HDRV

= 0.1 A, (V

LDRV

= 0.1 A 0.5

LDRV

=10kΩ 6.25 6.5 7.5

KFF

= 82.5 kΩ 91011

KFF

– 0.5 V) 330 500

ILIM

– 2 V) 275 375 ns

ILIM

100

= 2200 pF, (VIN–V

= 2200 pF, (VIN–V

)4896

BPN10

)3672

BPN10

= 2200 pF, BP10 24 48

= 2200 pF, BP10 48 96

)1.01.4

HDRV

HDRV–VBPN10

BP10–VLDRV

)0.75

)1.01.5

165

25

ns

V

1µA

°C

(4) Ensured by design. Notproduction tested.

4

TPS40060

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SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

Terminal Functions

TERMINAL

NAME NO.

BP5 3 O

BP10 11 O

BPN10 13 O

COMP 8 I VFB pin to compensate the overall loop. The comp pin is internally clamped above the peak of the ramp to

HDRV 14 O

ILIM 16 I voltage drop across an external resistor connected from this pin to VIN. The voltage on this pin is compared to the

KFF 1 I

LDRV 10 I

PGND 9

RT 2 I

SGND 5 Signal ground reference for the device.

SS/SD 6 I 0.85 V. The output continues to rise and reaches regulation when V

SW 12 I

SYNC 4 I

VFB 7 I

VIN 15 I Supply voltage for the device.

I/O DESCRIPTION

5-V reference. This pin should be bypassed to ground with a 0.1-µF ceramic capacitor. This pin may be used with
an external DC load of 1 mA or less.

10-V reference used for gate drive of the N-channel synchronous rectifier. This pin should be bypassed by a 1-µF
ceramic capacitor. This pin may be used with an external DC load of 1 mA or less.

Negative 8-V reference with respect to VIN. This voltage is used to provide gate drive for the high side P-channel
MOSFET. This pin should be bypassed to VIN with a 0.1-µF capacitor

Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to the

improve large signal transient response.

Floating gate drive for the high-side P-channel MOSFET. This pin switches from VIN (MOSFET off) to BPN10
(MOSFET on).

Current limit pin, used to set the overcurrent threshold. An internal current sink from this pin to ground sets a

voltage drop (VIN -SW) across the high side MOSFET during conduction.

A resistor is connected from this pin to VIN to program the amount of voltage feed-forward. The current fed into
this pin is internally divided and used to control the slope of the PWM ramp.

Gate drive for the N-channel synchronous rectifier. This pin switches from BP10 (MOSFET on) to ground
(MOSFET off).

Power ground reference for the device. There should be a low-impedance connection from this point to the source
of the power MOSFET.

A resistor is connected from this pin to ground to set the internal oscillator ramp charging current and switching
frequency.

Soft-start programming pin. A capacitor connected from this pin to ground programs the soft-start time. The
capacitor is charged with an internal current source of 2.3 µA. The resulting voltage ramp on the SS pin is used as
a second non-inverting input to the error amplifier. The output voltage begins to rise when V

considered shut down when V
enabled when V
switching and the output voltage (V

This pin is connected to the switched node of the converter and used for overcurrent sensing. This pin is used for
zero current sensing in the TPS40060.

Synchronization input for the device. This pin can be used to synchronize the oscillator to an external master
frequency.

Inverting input to the error amplifier. In normal operation the voltage on this pin is equal to the internal reference
voltage, 0.7 V.

is 210 mV or greater. When V

SS/SD

is 125 mV or less. All internal circuitry is inactive. The internal circuitry is

SS/SD

) decays while the internal circuitry remains active.

OUT

is less than approximately 0.85 V, the outputs cease

SS/SD

is approximately 1.55 V. The controller is

SS/SD

SS/SD

TPS40061

is approximately

5

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TPS40060
TPS40061

SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

SIMPLIFIED BLOCK DIAGRAM

VIN

ILIM

16

BP10

BP10

1115

RT

SYNC

KFF

BP5

COMP

VFB

SS/SD

2

4

Ramp Generator

1

BP5

3

8

7

7

6

7

Restart

Clock

Oscillator

7

07VREF

+

+

+

0.85 V

5

SGND

CLK

07VREF

7

10−V Regulator

Reference

Voltages

Fault

7

CL

7

+

7

CLK

+

07VREF

1V5REF

3V5REF

SQ

1V5REF

BP5

QR

CLK

7

7

7

7

3−bit up/down
Fault Counter

7

7

7

Restart

SW

7

Zero Current Detector

(TPS40060 Only)

7

7

Fault

7 HDRV

CL

BP10

7

SQ

QR

VIN

7

P-Channel

Driver

7

BPN10

N-Channel

Driver

7

HDRV

7

UDG−02160

13

14

12

10

9

BPN10

HDRV

SW

LDRV

PGND

6

TPS40060

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SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

APPLICATION INFORMATION

The TPS40060/61 family of parts allows the user to optimize the PWM controller to the specific application.

The TPS40061 is the controller of choice for synchronous buck designs which will include most applications. It
has two quadrant operation and will source or sink output current. This provides the best transient response.

The TPS40060 operates in one quadrant and sources output current only, allowing for paralleling of converters
and ensures that one converter does not sink current from another converter. This controller also emulates a
standard buck converter at light loads where the inductor current goes discontinuous. At continuous output
inductor currents the controller operates as a synchronous buck converter to optimize efficiency.

SW NODE RESISTOR

The SW node of the converter will be negative during the dead time when both the upper and lower MOSFETs
are off. The magnitude of this negative voltage is dependent on the lower MOSFET body diode and the output
current which flows during this dead time. This negative voltage could affect the operation of the controller,
especially at low input voltages.

Therefore, a 10-Ω resistor must be placed between the lower MOSFET drain and pin 12 (SW) of the controller as
shown in Figure 13 as RSW.

SETTING THE SWITCHING FREQUENCY (PROGRAMMING THE CLOCK OSCILLATOR)

The TPS40060 and TPS40061 have independent clock oscillator and ramp generator circuits. The clock
oscillator serves as the master clock to the ramp generator circuit. The switching frequency, fSWin kHz, of the
clock oscillator is set by a single resistor (RT) to ground. The clock frequency is related to RT,inkΩ by
Equation 1 and the relationship is charted in Figure 2.

TPS40061

RT+

ǒ

fSW 17.82 10

1

* 23ǓkW

*6

(1)

PROGRAMMING THE RAMP GENERATOR CIRCUIT

The ramp generator circuit provides the actual ramp used by the PWM comparator. The ramp generator provides
voltage feed-forward control by varying the P WM ramp slope with line voltage, while maintaining a constant ramp
magnitude. Varying the PWM ramp directly with line voltage provides excellent response to line variations since
the PWM does not have to wait for loop delays before changing the duty cycle. (See Figure 1).

VIN

VIN

SW

V

PEAK

COMP

RAMP

t

ON1

d +

1

t

ON

T

t

t

ON2

ON1

> t

and d1> d

ON2

T

2

2

T

Figure 1. Voltage Feed-Forward Effect on PWM Duty Cycle

SW

RAMP

COMP

V

VALLEY

UDG-02131

7

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100

0

200

300

400

500

600

400 600 800 1000

700

200

800

FEED-FORWARD IMPEDANCE

vs

SWITCHING FREQUENCY

R

KFF

- Feed-Forward Impedance - kΩ

fSW - Switching Frequency - kHz

VIN= 25 V

VIN= 15 V

VIN= 9 V

TPS40060
TPS40061

SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

APPLICATION INFORMATION (continued)

The PWM ramp must be faster than the master clock frequency or the PWM is prevented from starting. The
PWM ramp time is programmed via a single resistor (R
minimum input voltage, V

R

KFF

+ǒV

IN (min)

* 3.5Ǔ ǒ65.27 RT) 1502Ǔ(W)

through the following:

IN(min)

where:

• VINis the desired start-up (UVLO) input voltage

• R

is the timing resistor in kΩ

T

See the section on UVLO operation for further description.

The curve showing the feedforward impedance required for a given switching frequency, fSW, at various input
voltages is shown in Figure 3.

For low input voltage and high duty cycle applications, the voltage feed-forward may limit the duty cycle
prematurely. This does not occur for most applications. The voltage control loop controls the duty cycle and
regulates the output voltages. For more information on large duty cycle operation, refer to Application Note
(SLUA310).

) pulled up to VIN.R

KFF

is related to RT, and the

KFF

(2)

TIMING RESISTANCE

600

500

400

300

200

- Timing Resistance - kΩ

T

R

100

0

0

SWITCHING FREQUENCY

200 400 600 800 1000

fSW - Switching Frequency - kHz

Figure 2. Figure 3.

vs

UVLO OPERATION

The TPS40060 and TPS40061 use both fixed and variable (user programmable) UVLO protection. The fixed
UVLO monitors the BP10 and BP5 bypass voltages. The UVLO circuit holds the soft-start low until the BP5 and
BP10 voltage rails have exceeded their thresholds and the input voltage has exceed the user programmable
undervoltage threshold.

The TPS40060 and TPS40061 use the feed-forward pin, KFF, as a user programmable low-line UVLO detection.
This variable low-line UVLO threshold compares the PWM ramp duration to the oscillator clock period. An
undervoltage condition existis if the device receives a clock pulse before the ramp has reached 90% of its full
amplitude. The ramp duration is a function of the ramp slope, which is directly related to the current into the KFF
pin. The KFF current is a function of the input voltage and the resistance from KFF to the input voltage. The KFF
resistor can be referenced to the oscillator frequency as descibed in Equation 3:

8

TPS40060

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SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

APPLICATION INFORMATION (continued)

R

+ǒV

KFF

IN (min)

where:

• VINis the desired start-up (UVLO) input voltage

• R

T

The variable UVLO function utilizes a 3-bit full adder to prevent spurious shut-downs or turn-ons due to spikes or
fast line transients. When the adder reaches a total of seven counts in which the ramp duration is shorter the
clock cycle a powergood signal is asserted, a soft-start initiated, and the upper and lower MOSFETs are turned
off.

Once the soft-start is initiated, the UVLO cicruit must see a total count of seven cycles in which the ramp
duration is longer than the clock cycle before an undervoltage condition is declared (See Figure 4).

UVLO Threshold

VIN

* 3.5Ǔ ǒ65.27 RT) 1502Ǔ(W)

is the timing resistor in kΩ

TPS40061

(3)

Clock

PWM RAMP

PowerGood

1 2 3 4 5 6 7 1 2 3 4 5 6 71 2

Figure 4. Undervoltage Lockout Operation

3.0

2.5

2.0

1.5

- Output Voltage - V

1.0

UVLO

V

UNDERVOLTAGE LOCKOUT

vs

HYSTERESIS

UDG-02132

0.5

0

10 15

20 25 30 35 40 45 50 45

V

- Undervoltage Lockout Threshold - V

UVLO

Figure 5.

9

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TPS40060
TPS40061

SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

APPLICATION INFORMATION (continued)

The impedance of the input voltage can cause the input voltage, at the TPS4006x, to sag when the converter
starts to operate and draw current from the input source. Therefore, there is voltage hysteresis that prevents
nuisance shutdowns at the UVLO point.

With RT chosen to select the operating frequency and RKFF chosen to select the start-up voltage, the amount of
hysteresis voltage is shown in Figure 5.

PROGRAMMING SOFT START

TPS4006x uses a closed-loop approach to ensure a controlled ramp on the output during start-up. Soft-start is
programmed by charging an external capacitor (CSS) via an internally generated current source. The voltage on
CSSminus 0.85 V, is fed into a separate non-inverting input to the error amplifier (in addition to FB and 0.7-V
V

). The loop is closed on the lower of the (CSS– 0.85 V) voltage or the internal reference voltage ( 0.7-V

REF

V

). Once the (CSS– 0.85 V) voltage rises above the internal reference voltage, regulation is based on the

REF

internal reference. To ensure a controlled ramp-up of the output voltage the soft-start time should be greater than
the L-COtime constant as described in Equation 4.

t

w 2p L C

START

There is a direct correlation between t
higher the input current required during start-up. This relationship is describe in more detail in the section titled,
Programming the Current Limit which follows. The soft-start capacitance, CSS, is described in Equation 5.

For applications in which the VINsupply ramps up slowly, (typically between 50 ms and 100 ms) it may be
necessary to increase the soft-start time to between approximately 2 ms and 5 ms to prevent nuisance UVLO
tripping. The soft-start time should be longer than the time that the VINsupply transitions between 6 V and 7 V.

CSS+

2.3 mA

0.7 V

Ǹ

t

START

(seconds)

O

(Farads)

and the input current required during start-up. The faster t

START

START

(4)

,the

(5)

10

TPS40060

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SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

APPLICATION INFORMATION (continued)

PROGRAMMING CURRENT LIMIT

This device uses a two-tier approach for overcurrent protection. The first tier is a pulse-by-pulse protection
scheme. Current limit is implemented on the high-side MOSFET by sensing the voltage drop across the
MOSFET when the gate is driven low. The MOSFET voltage is compared to the voltage dropped across a
resistor connected from VIN pin to the ILIM pin when driven by a constant current sink. If the voltage drop across
the MOSFET exceeds the voltage drop across the ILIM resistor, the switching pulse is immediately terminated.
The MOSFET remains off until the next switching cycle is initiated.

The second tier consists of a fault counter. The fault counter is incremented on an overcurrent pulse and
decremented on a clock cycle without an overcurrent pulse. When the counter reaches seven (7) a restart is
issued and seven soft-start cycles are initiated. Both the upper and lower MOSFETs are turned off during this
period. The counter is decremented on each soft-start cycle. When the counter is decremented to zero, the PWM
is re-enabled. If the fault has been removed the output starts up normally. If the output is still present the counter
counts seven overcurrent pulses and re-enters the second-tier fault mode. See Figure 6 for typical overcurrent
protection waveforms.

The minimum current limit setpoint (I

I

LIM

+

ǒ

CO V

ƪ

Ǔ

O

) IL(A)

t

ƫ

SS

The current limit programming resistor (R
values used fro VOSand I
minimum value of I

R

ILIM

IOC R

+

and the maximum value of VOSmust be used.

SINK

DS(on)[max]

I

SINK

in the equation. In order to ensure the output current at the overcurrent level, the

SINK

where:

• I

• I

• V

is the current into the ILIM pin and is nominally 8.3 µA, minimum

SINK

is the overcurrent setpoint which is the DC output current plus one-half of the peak inductor current

OC

is the overcurrent comparator offset and is 50 mV maximum

OS

)

LIM

V

I

SINK

OS

) depends on t

) is calculated using Equation 7. Care must be taken in choosing the

ILIM

(W)

START,CO,VO

, and the load current at turn-on (IL).

TPS40061

(6)

(7)

BP5, BPN10 AND BPN10 INTERNAL VOLTAGE REGULATOR

Start-up characteristics of the BP5, BP10 and BPN10 regulators are shown in Figure 6. Slight variations in the
BP5 occurs dependent upon the switching frequency. Variation in the BPN10 and BP10 regulation characteristics
is also based on the load presented by switching the external MOSFETs.

11

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TPS40060
TPS40061

SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

APPLICATION INFORMATION (continued)

INTERNAL REGULATOR OUTPUT VOLTAGE

vs

INPUT VOLTAGE

12

10

8

BP5

6

- Output Voltage - V
4

BPx

V

2

0

2 4 6 8 10 12

VIN - Input Voltage - V

BP10

BPN10

Figure 6.

HDRV

CLOCK

t

BLANKING

V

ILIM

V

VIN-VSW

SS

(HDRV CYCLE TERMINATED BY CURRENT LIMIT TRIP)

7 CURRENT LIMIT TRIPS

7 SOFT-START CYCLES

UDG-02136

Figure 7. Typical Current Limit Protection Waveforms

CALCULATING THE BPN10 AN BP10V BYPASS CAPACITOR

The BPN10 capacitance provides a local, low impedance source for the high-side driver. The BPN10 capacitor
should be a good quality, high-frequency capacitor. The size of the bypass capacitor depends on the total gate
charge of the MOSFET and the amount of droop allowed on the bypass capacitor. The BPN10 capacitance is
described in Equation 8.

12

TPS40060

www.ti.com

SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

APPLICATION INFORMATION (continued)

Q

C

BPN10

+

DV

g

(F)

The 10-V reference pin, BP10V needs to provide energy for the synchronous MOSFET gate drive via the BP10V
capacitor. Neglecting any efficiency penalty, the BP10V capacitance is described in Equation 9.

Q

C

BP10V

+

gSR

DV

(F)

SYNCHRONIZING TO AN EXTERNAL SUPPLY

The TPS4006x can be synchronized to an external clock through the SYNC pin. The SW node rises on the
falling edge of the SYNC signal. The synchronization frequency should be in the range of 20% to 30% higher
than its programmed free-run frequency. The clock frequency at the SYNC pin replaces the master clock
generated by the oscillator circuit. Pulling the SYNC pin low programs the TPS4006x to freely run at the
frequency programmed by RT.

Internally, the SYNC pin has a pull-down current between 5 µA and 10 µA. In order to synchronize the device t o
an external clock signal, the SYNC pin has to be overdriven from the external clock circuit. Normal logic gates or
an external MOSFET with a pull-up resistor of 10 kΩ is adequate.

Internally there is a delay of between approximately 50 ns and 100 ns from the time the SYNC pin is pulled low
and the HDRV signal goes high to turn on the upper MOSFET. Additionally, there is some delay as the MOSFET
gate charges to turn on the upper MOSFET, typically between 20 ns and 50 ns.

The higher synchronization must be factored in when programming the PWM ramp generator circuit. If the PWM
ramp is interrupted by the SYNC pulse, a UVLO condition is declared and the PWM becomes disabled. Typically
this is of concern under low-line conditions only. In any case, R
frequency. In order to specify the correct value for R

at the synchronizing frequency, calculate a 'dummy'

KFF

value for RT that would cause the oscillator to run at the synchronizing frequency. Do not use this value of RT in
the design.

needs to be adjusted for the higher switching

KFF

TPS40061

(8)

(9)

R

T(dummy)

+

Use the value of R

R

+ǒV

KFF

IN(min)

ǒ

f

SYNC

T(dummy)

* 3.5 VǓ ǒ65.27 R

1

17.82 10

* 23ǓkW

*6

to calculate the value for R

T(dummy)

.

KFF

) 1502ǓkW

(10)

(11)

where:

• RTis in kΩ

This value of R

ensures that UVLO is not engaged when operating at the synchronization frequency.

KFF

SELECTING THE INDUCTOR VALUE

The inductor value determines the magnitude of ripple current in the output capacitors as well as the load current
at which the converter enters discontinuous mode. Too large an inductance results in lower ripple current but is
physically larger for the same load current. Too small an inductance results in larger ripple currents and a greater
number of (or more expensive output capacitors for) the same output ripple voltage requirement. A good
compromise is to select the inductance value such that the converter doesn't enter discontinuous mode until the
load approximated somewhere between 10% and 30% of the rated output. The inductance value is described in
Equation 12.

ǒ

VIN* V

L +

VIN DI f

where:

• VOis the output voltage

•∆I is the peak-to-peak inductor current

O

Ǔ

V

SW

O

(H)

(12)

13

www.ti.com

Ǔ

TPS40060
TPS40061

SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

APPLICATION INFORMATION (continued)

CALCULATING THE OUTPUT CAPACITANCE

The output capacitance depends on the output ripple voltage requirement, output ripple current, as well as any
output voltage deviation requirement during a load transient.

The output ripple voltage is a function of both the output capacitance and capacitor ESR. The worst case output
ripple is described in Equation 13.

DV + DI

The output ripple voltage is typically between 90% and 95% due to the ESR component.

The output capacitance requirement typically increases in the presence of a load transient requirement. During a
step load, the output capacitance must provide energy to the load (light to heavy load step) or absorb excess
inductor energy (heavy-to-light load step) while maintaining the output voltage within acceptable limits. The
amount of capacitance depends on the magnitude of the load step, the speed of the loop and the size of the
inductor.

Stepping the load from a heavy load to a light load results in an output overshoot. Excess energy stored in the
inductor must be absorbed by the output capacitance. The energy stored in the inductor is described in
Equation 14 and Equation 15.

EL+

where:

I2+

where:

Energy in the capacitor is given by the following equation:

EC+

where:

V2+ǒV

where:

By substituting Equation 14 into Equation 13, substituting Equation 16 into Equation 15, setting Equation 13
equal to Equation 15 and solving for COyields the following equation.

CO+

ESR ) ǒ

ƪ

1

L I2(J)

2

2

ǒ

Ǔ

ƪ

I

*ǒI

OH

• IOHis the output current under heavy load conditions

• I

is the output current under light load conditions

OL

1

C V2(J)

2

2

Ǔ

*ǒV

f

• Vfis the final peak capacitor voltage

• V

is the initial capacitor voltage

i

ǒ

ƪ

I

L

ǒ

ƪ

V

OH

Ǔ

f

Ǔ2ǒ

i

Ǔ

2

*ǒV

OL

2

2

Ǔ

*ǒI

1

8 CO f

ǒ

ƫ

(

Amperes

2

Ǔ

Volts

2

Ǔ

ƫ

OL

2

Ǔ

ƫ

i

SW

(F)

ǒ

V

P*P

Ǔ

(13)

(14)

(15)

(16)

(17)

(18)

Ǔ

ƫ

2

)

Loop Compensation

Voltage-mode buck-type converters are typically compensated using Type III networks. Since the TPS40060 and
TPS40061 use voltage feedforward control, the gain of the PWM modulator with voltage feedforward circuit must
be included. The modulator gain is described in Figure 7, with VINbeing the minimum input voltage required to
cause the ramp excursion to cover the entire switching period.

14

www.ti.com

APPLICATION INFORMATION (continued)

TPS40060
TPS40061

SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

A

MOD

+

V

IN

or A

V

S

MOD(db)

+ 20 log

V

IN

ǒ

Ǔ

V

S

(19)

Duty dycle, D, varies from 0 to 1 as the control voltage, VC, varies from the minimum ramp voltage to the
maximum ramp voltage, VS. Also, for a synchronous buck converter, D = VO/VIN. To get the control voltage to
output voltage modulator gain in terms of the input voltage and ramp voltage,

D +

V

V

V

O

C

+

V

IN

S

or

V

V

O

IN

+

V

V

C

S

(20)

Calculate the Poles and Zeros

For a buck converter using voltage mode control there is a double pole due to the output L-CO. The double pole
is located at the frequency calculated in Equation 21.

fLC+

2p L C

1

Ǹ

(Hz)

O

(21)

There is also a zero created by the output capacitance, CO, and its associated ESR. The ESR zero is located at
the frequency calculated in Equation 22.

fZ+

2p ESR C

Calculate the value of R

R

+

BIAS

1

0.7 R1

V

* 0.7

OUT

(Hz)

O

to set the output voltage, V

BIAS

W

OUT

(22)

.

(23)

The maximum crossover frequency (0 dB loop gain) is calculated in Equation 24.

f

SW

fC+

4

(Hertz)

(24)

Typically, fCis selected to be close to the midpoint between the L-COdouble pole and the ESR zero. At this
frequency, the control to output gain has a –2 slope (-40 dB/decade), while the Type III topology has a +1 slope
(20 dB/decade), resulting in an overall closed loop –1 slope (–20 dB/decade). Figure 9 shows the modulator
gain, L-C filter, output capacitor ESR zero, and the resulting response to be compensated.

A Type III topology, shown in Figure 10, has two zero-pole pairs in addition to a pole at the origin. The gain and
phase boost of a Type III topology is shown in Figure 11. The two zeros are used to compensate the L-C
double pole and provide phase boost. The double pole is used to compensate for the ESR zero and provide
controlled gain roll-off. In many cases the second pole can be eliminated and the amplifier's gain roll-off used to
roll-off the overall gain at higher frequencies.

O

15

www.ti.com

MODULATOR GAIN

vs

SWITCHING FREQUENCY

Modulator Gain - dB

fSW - Switching Frequency - Hz

100 1 k 10 k 100 k

ESR Zero, + 1

LC Filter, - 2

A

MOD

= VIN / V

S

Resultant, - 1

GAIN

180°

−90°

−270°

PHASE

+ 1

− 1

− 1

0 dB

P

TPS40060
TPS40061

SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

APPLICATION INFORMATION (continued)

PWM MODULATOR RELATIONSHIPS

V

S

V

C

D = VC / V

C3

V

OUT

S

R3

R1

R

BIAS

Figure 10. Type III Compensation of Configuration Figure 11. Type III Compensation Gain and Phase

Figure 8. Figure 9.

C2

(optional)

C1

VFB

7

VREF

R2

8

+

COM

UDG−02189

The poles and zeros for a type III network are described in Equation 25.

fZ1+

2p R2 C1

The value of R1 is somewhat arbitraty, but influences other component values. A value between 50kΩ and

1

(Hz) fZ2+

fP1+

2p R2 C2

100kΩ usually yields reasonable values.

The unity gain frequency is described in Equation 26.

+

f

C

2p R1 C2 G

where G is the reciprocal of the modulator gain at fC.

16

1

(Hertz)

1

1

2p R1 C3

(Hz) fP2+

(Hz)

2p R3 C3

(25)

1

(Hz)

(26)

TPS40060

www.ti.com

SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

APPLICATION INFORMATION (continued)

The modulator gain as a function of frequency at fC, is described in Equation 27.

2

f

AMOD(f) + AMOD

LC

ǒ

Ǔ

f

and G +

C

1

AMOD(f)

Care must be taken not to load down the output of the error amplifier with the feedback resistor, R2, that is too
small. The error amplifier has a finite output source and sink current which must be considered when sizing R2.
Too small a value does not allow the output to swing over its full range.

V

R2

(MIN)

+

C(max)

I

SOURCE (min)

(W) +

3.45 V

2.0 mA

+ 1.725 kW

dv/dt INDUCED TURN-ON

MOSFETs are susceptible to dv/dt turn-on particularly in high-voltage (VDS) applications. The turn-on is caused
by the capacitor divider that is formed by CGDand CGS. High dv/dt conditions and drain-to-source voltage, on the
MOSFET causes current flow through CGDand causes the gate-to-source voltage to rise. If the gate-to-source
voltage rises above the MOSFET threshold voltage, the MOSFET turns on, resulting in large shoot-through
currents. Therefore the SR MOSFET should be chosen so that the CGDcapacitance is smaller than the C
capacitance. A 2-Ω to 5-Ω resistor in the upper MOSFET gate lead shapes the turn-on and dv/dt of the SW node
and helps reduce the induced turn-on.

TPS40061

(27)

(28)

GS

HIGH-SIDE MOSFET POWER DISSIPATION

The power dissipated in the external high-side MOSFET is comprised of conduction and switching losses. The
conduction losses are a function of the I
high-side MOSFET conduction losses are defined by Equation 29.

2

P

COND

+ǒI

RMS

Ǔ

R

ǒ1 ) TCR ƪTJ* 25OC

DS(on)

where:

• TCRis the temperature coefficient of the MOSFET R

The TCRvaries depending on MOSFET technology and manufacturer but is typically ranges between 0.0035
ppm/°C and 0.010 ppm/°C.

The I

current for the high side MOSFET is described in Equation 30.

RMS

I

RMS

+ IO d

Ǹ

ǒ

Amperes

RMS

Ǔ

The switching losses for the high-side MOSFET are descibed in Equation 31.

P

SW(fsw)

+ǒVIN I

OUT

t

Ǔ

fSW(Watts)

SW

where:

• IOis the DC output current

• t

is the switching rise time, typically < 20 ns

SW

• f

is the switching frequency

SW

Typical switching waveforms are shown in Figure 12.

current through the MOSFET and the R

RMS

ƫ

Ǔ

(W)

DS(on)

of the MOSFET. The

DS(on)

(29)

(30)

(31)

17

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TPS40060
TPS40061

SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

APPLICATION INFORMATION (continued)

I

O

d 1-d

BODY DIODE

CONDUCTION

SW

0

BODY DIODE

CONDUCTION

I

D2

∆I

}

I

D1

ANTI-CROSS

CONDUCTION

SYNCHRONOUS

RECTIFIER ON

HIGH SIDE ON

UDG-02179

Figure 12. Inductor Current and SW Node Waveforms

The maximum allowable power dissipation in the MOSFET is determined by the following equation.

PT+

ǒ

TJ* T

Ǔ

A

q

JA

(W)

(32)

where:

PT+ P

COND

) P

SW(fsw)

(W)

(33)

and ΘJAis the package thermal impedance.

SYNCHRONOUS RECTIFIER MOSFET POWER DISSIPATION

The power dissipated in the synchronous rectifier MOSFET is comprised of three components: R
losses, body diode conduction losses, and reverse recovery losses. R

) conduction losses can be found

DS(on

using Equation 29 and the RMS current through the synchronous rectifier MOSFET is described in Equation 34.

I

+ IO 1 * d

RMS

Ǹ

ǒ

Ǔ

A

RMS

The body-diode conduction losses are due to forward conduction of the body diode during the anti-cross
conduction delay time. The body diode conduction losses are described by Equation 35.

PDC+ 2 IO VF t

DELAY

f

SW

(W)

where:

• VFis the body diode forward voltage

• t

is the delay time just before the SW node rises

DELAY

The 2-multiplier is used because the body-diode conducts twice during each cycle (once on the rising edge and
once on the falling edge)

The reverse recovery losses are due to the time it takes for the body diode to recovery from a forward bias to a
reverse blocking state. The reverse recovery losses are described in Equation 36.

PRR+ 0.5 QRR VIN f

SW

(W)

where:

• QRRis the reverse recovery charge of the body diode

The total synchronous rectifier MOSFET power dissipation is described in Equation 37.

DS(on)

conduction

(34)

(35)

(36)

18

TPS40060

www.ti.com

APPLICATION INFORMATION (continued)

PSR+ PDC) PRR) P

TPS40060/TPS40061 POWER DISSIPATION

The power dissipation in the TPS40060 and TPS40061 is largely dependent on the MOSFET driver currents and
the input voltage. The driver current is proportional to the total gate charge, Qg, of the external MOSFETs. Driver
power (neglecting external gate resistance, refer to [2] can be calculated from Equation 38.

PD+ Qg VDR f

And the total power dissipation in the device, assuming MOSFETs with similar gate charges for both the
high-side and synchronous rectifier is described in Equation 39.

2 P

ǒ

PT+

or

PT+ƪǒ2 Qg f

where:

• IQis the quiescent operating current (neglecting drivers)

The maximum power capability of the device's PowerPad package is dependent on the layout as well as air flow.
The thermal impedance from junction to air, assuming 2 oz. copper trace and thermal pad with solder and no air
flow.

ΘJA= 36.51°C/W

The maximum allowable package power dissipation is related to ambient temperature by Equation 36.
Substituting Equation 32 into Equation 40 and solving for fSWyields the maximum operating frequency for the
TPS40060 and TPS40061. The result is:

D

) I

V

DR

COND

SW

Ǔ

VIN(W)

Q

Ǔ

) I

SW

(W)

(W)

ƫ

VIN(W)

Q

SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

TPS40061

(37)

(38)

(39)

(40)

fSW+

ǒ

ǒ

ƪ

ǒ

qJA V

TJ*T

ǒ

2 Q

A

DD

Ǔ

Ǔ

g

ƫ* I

Ǔ

Ǔ

Q

(Hz)

(41)

19

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TPS40060
TPS40061

SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

LAYOUT CONSIDERATIONS

THE PowerPAD™ PACKAGE

The PowerPAD package provides low thermal impedance for heat removal from the device. The PowerPAD
derives its name and low thermal impedance from the large bonding pad on the bottom of the device. For
maximum thermal performance, the circuit board must have an area of solder-tinned-copper underneath the
package. The dimensions of this area depends on the size of the PowerPAD package. For a 16-pin TSSOP
(PWP) package the dimensions of the circuit board pad are 5 mm x 3.4 mm. The dimensions of the package pad
are shown in Figure 13.

Thermal vias connect this area to internal or external copper planes and should have a drill diameter sufficiently
small so that the via hole is effectively plugged when the barrel of the via is plated with copper. This plug is
needed to prevent wicking the solder away from the interface between the package body and the solder-tinned
area under the device during solder reflow. Drill diameters of 0.33 mm (13 mils) works well when 1-oz copper is
plated at the surface of the board while simultaneously plating the barrel of the via. If the thermal vias are not
plugged when the copper plating is performed, then a solder mask material should be used to cap the vias with a
diameter equal to the via diameter of 0.1 mm minimum. This capping prevents the solder from being wicked
through the thermal vias and potentially creating a solder void under the package. Refer to PowerPAD Thermally

Enhanced Package

[2]

for more information on the PowerPAD package.

X: Minimum PowerPAD = 1,86 mm
Y: Minimum PowerPAD = 1,75 mm

Thermal Pad

X

Y

4,50 mm

4,30 mm

101

6,60 mm
6,20 mm

Figure 13. PowerPAD Dimensions

MOSFET PACKAGING

MOSFET package selection depends on MOSFET power dissipation and the projected operating conditions. In
general, for a surface-mount applications, the DPAK style package provides the lowest thermal impedance (θJA)
and, therefore, the highest power dissipation capability. However, the effectiveness of the DPAK depends on
proper layout and thermal management. The θJAspecified in the MOSFET data sheet refers to a given copper
area and thickness. In most cases, a thermal impedance of 40°C/W requires one square inch of 2-ounce copper
on a G-10/FR-4 board. Lower thermal impedances can be achieved at the expense of board area. Please refer
to the selected MOSFET's data sheet for more information regarding proper mounting.

GROUNDING AND CIRCUIT LAYOUT CONSIDERATIONS

The device provides separate signal ground (SGND) and power ground (PGND) pins. It is important that circuit
grounds are properly separated. Each ground should consist of a plane to minimize its impedance if possible.
The high power noisy circuits such as the output, synchronous rectifier, MOSFET driver decoupling capacitor
(BP10), and the input capacitor should be connected to PGND plane at the input capacitor.

Sensitive nodes such as the FB resistor divider, RT, and ILIM should be connected to the SGND plane. The
SGND plane should only make a single point connection to the PGND plane.

Component placement should ensure that bypass capacitors (BP10, BP5, and BPN10) are located as close as
possible to their respective power and ground pins. Also, sensitive circuits such as FB, RT and ILIM should not
be located near high dv/dt nodes such as HDRV, LDRV, BPN10, and the switch node (SW).

20

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TPS40060
TPS40061

SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

DESIGN EXAMPLE

• Input voltage: 18 VDCto 55 V

• Output voltage: 3.3 V ±2%

• Output current: 5 A (maximum, steady-state), 7 A (surge, 10-ms duration, 10% duty cycle maximum)

• Output ripple: 33 mV

• Output load response: 0.3 V => 10% to 90% step load change

• Operating temperature: –40°Cto85°C

• fSW= 130 kHz

P-P

DC

at 5 A

1. Calculate maximum and minimum duty cycles

d

MIN

+

V

O(min)

V

IN(max)

+ 0.0588 d

MAX

+

V

O(max)

V

IN(min)

++ 0.187

(42)

2. Select switching frequency

The switching frequency is based on the minimum duty cycle ratio and the propagation delay of the current limit
comparator. In order to maintain current limit capability, the on time of the upper MOSFET, tON, must be greater
than 330 ns (see Electrical Characteristics table). Therefore

V

O(min)

V

IN(max)

1

+ fSW+

T

SW

Using 400 ns to provide margin,

fSW+

Since the oscillator can vary by 10%, decrease fSW, by 10%

fSW=0.9× 147 kHz = 130 kHz

and therefore choose a frequency of 130 kHz.

t

+

T

0.0588
400 ns

ON

or

SW

V

O(min)

ȡ

ǒ

V

IN(max)

ȧ

ȧ
ȧ

T

ȧ
Ȣ

+ 147 kHz

ON

(43)

ȣ

Ǔ

ȧ

ȧ
ȧ
ȧ

Ȥ

(44)

(45)

3. Select∆ I

In this case ∆I is chosen so that the converter enters discontinuous mode at 20% of nominal load.

DI + IO 2 0.2 + 5 2 0.2 + 2.0 A

(46)

4. Calculate the power losses

Power losses in the high-side MOSFET (Si9407AGY) at 55-VINwhere switching losses dominate can be
calculated from Equation 46 through Equation 49.

I

+ IO dǸ+ 5 0.0588Ǹ+ 1.2 A

RMS

substituting Equation 30 into Equation 29 yields

P

and from Equation 31, the switching losses can be determined.

+ 1.22 0.12 (1 ) 0.007 (150 * 25))+ 0.324 W

COND

(47)

(48)

21

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TPS40060
TPS40061

SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

DESIGN EXAMPLE (continued)

P

SW(fsw)

+ǒVIN IO t

Ǔ

fSW+ 55 V 5A 20 ns 130 kHz + 0.715 W

SW

(49)

The MOSFET junction temperature can be found by substituting Equation 33 into Equation 32

TJ+ǒP

COND

) P

Ǔ

qJA) TA+(0.324 ) 0.715) 40 ) 85 + 127OC

SW

(50)

5. Calculate synchronous rectifier losses

The synchronous rectifier MOSFET has two (2) loss components, conduction, and diode reverse recovery
losses. The conduction losses are due to I
time associated with the anti-cross conduction delay.

The I

current through the synchronous rectifier from Equation 51

RMS

I

+ IO 1 * dǸ+ 5 1 * 0.0588Ǹ+ 4.85 A

RMS

The synchronous MOSFET conduction loss from Equation 29 is:

P

COND

+ I

RMS

2

R

+ 4.852 0.011 (1 ) 0.007(150 * 25))+ 0.10 W

DS(on)

The body diode conduction loss from Equation 35 is:

PDC+ 2 IO VFD t

fSW+ 2 5.0 A 0.8 V 100 ns 130 kHz + 0.104 W

DELAY

The body diode reverse recovery loss from Equation 36 is:

PRR+ 0.5 QRR VIN fSW+ 0.5 30 nC 55 V 130 kHz + 0.107 W

The total power dissipated in the synchronous rectifier MOSFET from Equation 37 is:

PSR+ PRR) P

) PDC+ 0.107 ) 0.1 ) 0.104 + 0.311 W

COND

The junction temperature of the synchronous rectifier at 85°Cis:

TJ+ PSR qJA) TA+(0.311) 40 ) 85 + 97oC

In typical applications, paralleling the synchronous rectifier MOSFET with a Schottky rectifier increases the
overall converter efficiency by approximately 2% due to the lower power dissipation during the body diode
conduction and reverse recovery periods.

losses as well as body diode conduction losses during the dead

RMS

RMS

(51)

(52)

(53)

(54)

(55)

(56)

6. Calculate the Inductor Value

The inductor value is calculated from Equation 11

(

L +

48 * 3.3) 3.3

48 2.0 130 kHz

+ 11.8 mH

(57)

A standard inductor value of 10-µH is chosen. A Coev DXM1306-10RO or Panasonic ETQPF102HFA could be
used.

7. Setting the switching frequency

The clock frequency is set with a resistor (RT) from the RT pin to ground. The value of RTcan be derived from
following Equation 58, with fSWin kHz.

RT+

ǒ

fSW 17.82 E * 06

1

* 23ǓkW + 408 kW, use 412 kW

(58)

8. Programming the Ramp Generator Circuit

The PWM ramp is programmed through a resistor (R
controls the input UVLO voltage. For an undervoltage level of 14.4V (20% below the 18 V
calculated in Equation 59.

22

) from the KFF pin to VIN. The ramp generator also

KFF

IN(min)

,R

KFF

is

z

z

TPS40060

www.ti.com

SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

DESIGN EXAMPLE (continued)

R

+ǒV

KFF

IN(min)

* 3.5

Ǔ

65.27 RT) 1502ǓW + 133.7 kW, use 133 kW

ǒ

9. Calculating the Output Capacitance (CO)

In this example. the output capacitance is determined by the load response requirement of ∆V=0.3Vfora1A
to 5 A step load. COcan be calculated using Equation 18.

2

2

Ǔ

Ǔ

+ 127 mF

10 mH ǒ52* 1

CO+

ǒ

3.32* 3.0

Using Equation 13 calculate the ESR required to meet the output ripple requirements.

TPS40061

(59)

(60)

33 mV + 2.0ǒESR )

1

8 127 mF 130 kHz

Ǔ

(61)

ESR = 12.7 mΩ

In order to get the required ESR, the capacitance needs to be greater than the 127-µF calculated. For example,
a single Panasonic SP capacitor, 180-µF with ESR of 12 mΩ can be used. Re-calculating the ESR required with
the new value of 180-µF is shown in Equation 62.

33 mV + 2.0ǒESR )

1

8 180 mF 130 kHz

Ǔ

(62)

ESR = 13.8 mΩ

10. Calculate the Soft-Start Capacitor (CSS)

This design requires a soft-start time (t

CSS+

2.3 mA

0.7 V

1ms+ 3.28 nF + 3300 pF

11. Calculate the Current Limit Resistor (R

The current limit set point depends on t

180 mF 3.3

LIM

u

1m

) 7.0 + 7.6 A

for 10.0 A minimum, then from Equation 7

V

ILIM

10 0.14

+

I

SINK

)

I

SINK

OS

W +

Set I

I

LIM

R

) of 1 ms. CSSis calculated in Equation 63.

START

)

ILIM

START,VO,CO

10 0.14

8.3 mA

)

and I

(

50 mV

8.3 mA

at start up as shown in Equation 7.

LOAD

)

W + 175 kW + 174 kW

(63)

(64)

(65)

12. Calculate Loop Compensation Values

Calculate the DC modulator gain (A

10

+

+ 5

2

+ 20 log(5.0)+ 14 dB

A

MOD(dB)

A

MOD

Calculate the output poles and zeros from Equation 21 and Equation 22 of the L-C filter.

fLC+

2p 10 mH 180 mF

1

Ǹ

and

fZ+

2p 0.012 180 mF

1

Select the close-loop 0 dB crossover frequency, f

) from Equation 19.

MOD

+ 3.7 kH

+ 74 kH

. For this example fC=10kHz.

C

(66)

(67)

(68)

(69)

23

www.ti.com

F

f

f

TPS40060
TPS40061

SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

DESIGN EXAMPLE (continued)

Select the double zero location for the Type III compensation network at the output filter double pole at 3.7 kHz.

Select the double pole location for the Type III compensation network at the output capacitor ESR zero at 73.7
kHz.

The amplifier gain at the crossover frequency of 10 kHz is determined by the reciprocal of the modulator gain
AMOD at the crossover frequency from Equation 27.

2

f

LC

ǒ

A

And also from Equation 27.

G +

Choose R1 = 100 kΩ

The poles and zeros for a Type III network are described in Equation 25 and Equation 26.

fZ2+

P2

fC+

P1

fZ1+

Calculate the value of R

R

+ A

MOD(f)

A

+

2p R1 C2 G

+

BIAS

MOD

1

+

MOD(f)

1

2p R1 C3

1

2p R3 C3

1

1

2p R2 C2

1

2p R2 C1

0.7 V R1

+

VO* 0.7 V

0.68

Ǔ

+ 5

f

C

1

+ 1.46

N C3 +

N R3 +

N C2 +

N R2 +

N C1 +

from Equation 23 with R1 = 100 kΩ.

BIAS

0.7 V 100kW

+

3.3 V * 0.7 V

3.7 kHz

ǒ

10 kHz

2p 100 kW 3.7 kHz

2p 470 pF 73.3 kHz

2p 100 kW 3.29 1.46 kHz

2p 100 pF 73.3 kHz

2p 21.5 kW 3.7 kHz

2

Ǔ

+ 0.68

1

1

1

1

+ 26.9 kW, choose 26.7 kW

+ 430 pF, choose 470 p

+ 4.62 kW, choose 4.64 kW

1

+ 21.7 kW, choose 21.5 kW

+ 2000 pF, choose 1800 pF

+ 109 pF, choose 100 pF

(70)

(71)

(72)

(73)

(74)

(75)

(76)

(77)

CALCULATING THE BPN10 AND BP10V BYPASS CAPACITANCE

The size of the bypass capacitor depends on the total gate charge of the MOSFET being used and the amount
of droop allowed on the bypass capacitor. The BPN10 capacitance, allowing for a 0.5-V droop on the BPN10 pin
from Equation 8 is shown in Equation 78.

Q

g

C

and the BP10V capacitance from Equation 9 is shown in Equation 79.

C

For this application, a 0.1-µF capacitor was used for the BPN10V and a 1.0-µF was used for the BP10V bypass
ccapacitor. Figure 14 shows component selection for the 18-V through 55-V to 3.3-V at 5-A dc-to-dc converter
specified in the design example.

BPN10

BP10V

+

+

DV

Q

gSR

DV

+

30 nC

0.5

57 nC

+

+ 60 nF

0.5

+ 114 nF

(78)

(79)

GATE DRIVE CONFIGURATION

Due to the possibility of dv/dt induced turn-on from the fast MOSFET switching times, high VDSvoltage and low
gate threshold voltage of the Si4470, the design includes a 2-Ω in the gate lead of the upper MOSFET. The
resistor can be used to shape the low-to-high transition of the SWitch node and reduce the tendancy of
dv/dt-induced turn on.

24

www.ti.com

DESIGN EXAMPLE (continued)

TPS40060
TPS40061

SLUS543D–DECEMBER 2002–REVISED SEPTEMBER 2004

+

VIN

−

C1 1800 pF

21.5 kΩ

R

133 kΩ

R2

KFF

412 kΩ

R

T

0.1 µF

3300 pF

C

SS

C2

100 pF

TPS40060PWP

1

KFF

2

RT

3

BP5

SYNC

4

5

SGND

6

SS/SD

7

VFB

8

COMP

PGND

ILIM

VIN

BPN10

SW

BP10

LDRV

PGND 9

16

15

14HDRV

13

12

11

10

R

174 kΩ

2 Ω

0.1 µF

R
10 Ω

1.0 µF

ILIM

Si9470

SW

10 µH

Si4470

Figure 14. Design Example, 48 V to 3.3 V at 5 A dc-to-dc Converter

30BQ060

R3

4.64 kΩ

C3

470 pF

R1
100kΩ

R

BIAS

26.7 kΩ

C

O

180 µF

VOUT

UDG−02161

+

−

REFERENCES

1. Balogh, Laszlo, Design and Application Guide for High Speed MOSFET Gate Drive Circuits, Texas
Instruments/Unitrode Corporation, Power Supply Design Seminar, SEM-1400 Topic 2.

2. PowerPAD Thermally Enhanced Package Texas I nstruments, Semiconductor Group, Technical Brief: TI
Literature No. SLMA002

25

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