TEXAS INSTRUMENTS TPS40056 Technical data

8

  

 



SLVS612 − APRIL 2006

FEATURES

Operating Input Voltage 10 V to 40 V

D
D Output Voltage Tracks External Reference
D Programmable Fixed-Frequency Up to

100 kHz to 1 MHz Voltage Mode Controller

D Internal Gate Drive Outputs for High-Side

and Synchronous N-Channel MOSFETs

D Externally Synchronizable
D Programmable Short-Circuit Protection
D Thermal Shutdown
D 16-Pin PowerPADt Package (θ

= 2°C/W)

JC

D Programmable Closed-Loop Soft-Start

APPLICATIONS

DDR Tracking Regulators

D
D Power Modules
D Networking Equipment
D Industrial Servers

SIMPLIFIED APPLICATION DIAGRAM

CONTENTS

Device Ratings 2
Electrical Characteristics 3
Terminal Information 5
Application Information 7
Design Example 22
Additional References 29

DESCRIPTION

The TPS40056 is part of a family of high-voltage,
wide input, synchronous, step-down converters.
The TPS40056 offers design flexibility with a
variety of user programmable functions, including
soft-start, operating frequency, high-side current
limit, and loop compensation. The TPS40056 is
also synchronizable to an external supply. It
incorporates MOSFET gate drivers for external
N-channel high-side and synchronous rectifier
(SR) MOSFETs. Gate drive logic incorporates
anti-cross conduction circuitry to prevent
simultaneous high-side and synchronous rectifier
conduction. The externally programmable short
circuit protection provides pulse-by-pulse current
limit, as well as hiccup mode operation utilizing an
internal fault counter for longer duration
overloads.

+

V

IN

−

V

TRKIN

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TPS40056PWP

SYNC

1
2

RT
BP5

3
4 EA_REF
5

SGND
6SS
7 VFB
8 COMP

PAD

16

ILIM

15

VIN

14BOOST

HDRV

13
12

SW

BP10

11

LDRV

10

PGND

9

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+

V

TT

−

UDG−03080

Copyright  2006, Texas Instruments Incorporated

1



V

C

SLVS612 − APRIL 2006

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

T

A

−40°C to 85°C Plastic HTSSOP(PWP)

(1)

The PWP package is also available taped and reeled. Add an R suffix to the device type
(i.e., TPS40056PWPR). See the application section of the data sheet for PowerPAD
drawing and layout information.

PACKAGE PART NUMBER

(1)

TPS40056PWP

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted

VIN 45

Input voltage range, V

Output voltage range, V
Output current, I
Operating junction temperature range, T
Storage temperature, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260

(2)

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only ,
and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is
not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

IN

O

OUT

J

stg

VFB, SS, SYNC, EA_REF −0.3 to 6
SW −0.3 to 45
SW, transient < 50 ns −2.5
COMP, RT, SS −0.3 to 6
RT 200 µA

(2)

TPS40056 UNIT

−40 to 125

−55 to 150

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT

Input voltage, V
Operating free-air temperature, T

I

A

PWP PACKAGE

(TOP VIEW)

(3)(4)

10 40 V

−40 85 °C

V

°C

SYNC

RT

BP5

EA_REF

SGND

SS/SD

VFB

COMP

(3)

For more information on the PWP package, refer to TI Technical Brief, Literature No. SLMA002.

(4)

PowerPADt heat slug must be connected to SGND (pin 5) or electrically isolated from all other pins.

2

1
2
3

THERMAL

4
5
6
7
8

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PAD

16
15
14
13
12
11
10

ILIM
VIN
BOOST
HDRV
SW
BP10
LDRV

9

PGND

ELECTRICAL CHARACTERISTICS

TA = −40°C to 85°C, VIN = 12 Vdc, RT = 90.9 kΩ, fSW = 500 kHz, V
otherwise noted)

PARAMETER

INPUT SUPPLY

V

IN

OPERATING CURRENT

I

DD

BP5

V

BP5

OSCILLATOR/RAMP GENERATOR

f

OSC

V

RAMP

V

IH

V

IL

I

SYNC

V

RT

SOFT START

I

SS

V

SS

t

DSCH

t

SS

BP10

V

BP10

ERROR AMPLIFIER

V

EA_REF

G

BW

G

BW

A

VOL

I

OH

I

OL

V

OH

V

OL

I

BIAS

(1)
(2)

Input voltage range, VIN 10 40 V

Quiescent current

Ouput voltage I

Accuracy 9 V ≤ VIN≤ 40 V 520 580 640 kHz
PWM ramp voltage
High-level input voltage, SYNC 2 5
Low-level input voltage, SYNC 0.8 V
Input current, SYNC 5 10 µA
Pulse width, SYNC 50 ns
RT voltage 2.38 2.50 2.58 V

Maximum duty cycle
Minumum duty cycle VFB ≥ EA_REF + 0.05 V 0%

Soft-start source current 1.65 2.35 3.05 µA
Soft-start clamp voltage 3.7 V
Discharge time CSS = 220 pF 1.6 2.2 2.8
Soft-start time CSS = 220 pF, 0 V ≤ VSS≤ 1.6 V 100 155 205

Ouput voltage 9.0 9.6 10.3 V

Error amplifier reference input voltage
Input offset voltage 0.5 V ≤ VFB≤ 2.25 V −6 6 mV
Input offset voltage 0.2 V ≤ VFB≤ 0.5 V −10 0 10 MV
Gain bandwidth 0.2 V ≤ VFB≤ 0.5 V 1.5 3.5 MHz
Gain bandwidth 0.5 V ≤ VFB≤ 2.25 V 2.5 5.0 MHz
Open loop gain 60 80 dB
High-level output source current 1.5 4.0
Low-level output sink current 2.0 4.0
High-level output voltage I
Low-level output voltage I
Input bias current VFB = 1.2 V 100 200 nA

Ensured by design. Not production tested.
Common mode range extends to ground, but not tested below 200 mV.

(1)

(1)(2)

Output drivers not switching,
VFB = 1.3 V

= 1 mA 4.5 5.0 5.5 V

LOAD

V

PEAK−VVAL

VFB = 0 V, fSW≤ 600 kHz 90%
VFB = 0 V, 600 kHz ≤ fSW≤ 1 MHz

10 V ≤ VIN≤ 40 V 0.2 2.5 V

SOURCE

= 500 µA 0.20 0.35

SINK

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SLVS612 − APRIL 2006

EA_REF

= 1.25 V, all parameters at zero power dissipation (unless

TEST CONDITIONS MIN TYP MAX UNIT

1.5 3.0 mA

2.0

85%

mA

= 500 µA 3.2 3.5

V

µs

V

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3



ns

OS

VOSOffset voltage SW vs. ILIM

mV

SLVS612 − APRIL 2006

ELECTRICAL CHARACTERISTICS

TA = −40°C to 85°C, VIN = 12 Vdc, RT = 90.9 kΩ, fSW = 500 kHz, V
otherwise noted)

PARAMETER

CURRENT LIMIT

I

SINK

t

ON

t

OFF

V

OUTPUT DRIVER

t

LRISE

t

LFALL

t

HRISE

t

HFALL

V
V
V
V

SS/SD SHUTDOWN

V
V

BOOST REGULATOR

V

BOOST

SW NODE

I

LEAK

THERMAL SHUTDOWN

T

SD

UVLO

(1)

Current limit sink current 8 10 12 µA

V

= 11.7 V, VSW = (V

Propagation delay to output
Switch leading-edge blanking pulse time

Off time during a fault 7 cycles

Offset voltage SW vs. ILIM

Low-side driver rise time
Low-side driver fall time
High-side driver rise time
High-side driver fall time

High-level ouput voltage, HDRV I

OH

Low-level ouput voltage, HDRV I

OL

High-level ouput voltage, LDRV I

OH

Low-level ouput voltage, LDRV I

OL

Minimum controllable pulse width

Shutdown threshold voltage Outputs off 90 125 165

SD

Device active threshold voltage 165 210 260

EN

Output voltage VIN = 12.0 V 19 20 21 V

Leakage current

Shutdown temperature
Hysteresis

Input voltage UVLO threshold 8.20 8.75 9.25
Input voltage UVLO hysteresis 1.0

Ensured by design. Not production tested.

(1)

(1)

(1)

(1)

(1)

ILIM

V

= 11.7 V, VSW = (V

ILIM

V

= 11.6 V, TA = 25°C −100 −70 −40

ILIM

V

= 11.6 V, 0°C ≤ TA ≤ 85°C

ILIM

V

= 11.6 V, −40°C ≤ TA ≤ 85°C −125 −15

ILIM

C

LOAD

C

LOAD

HDRV =
HDRV =
LDRV =
LDRV =

EA_REF

= 2200 pF

= 2200 pF, (HDRV − SW)

−0.1 A (HDRV − SW)

0.1 A (HDRV − SW) 0.75

−0.1 A

0.1 A 0.5

= 1.25 V all parameters at zero power dissipation (unless

TEST CONDITIONS MIN TYP MAX UNIT

− 0.5 V) 300

ILIM
ILIM

− 2 V)
100

−125 −30

BOOST

−1.5 V

BP10

−1.4 V

250

48 96
24 48
48 96
36 72

BOOST

−1.0 V

BP10

− 1.0 V

100 150 ns

25 µA

165

20

ns

mV

ns

V

mV

°C

V

4

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I/O

DESCRIPTION

SLVS612 − APRIL 2006

TERMINAL FUNCTIONS

TERMINAL

NAME NO.

BOOST 14 O

BP5 3

BP10 11 O

COMP 8 O

HDRV 13 O

ILIM 16 I

EA_REF 4 I Non-inverting input to the error amplifier and used as the reference for the feedback loop.
LDRV 10 O

PGND 9 −
RT 2 I A resistor is connected from this pin to ground to set the internal oscillator and switching frequency.

SGND 5 − Signal ground reference for the device.

SS/SD 6 I

SW 12 I This pin is connected to the switched node of the converter and used for overcurrent sensing.
SYNC 1 I

VFB 7 I
VIN 15 I Supply voltage for the device.

Gate drive voltage for the high side N-channel MOSFET. The BOOST voltage is 9 V greater than the input
voltage. A 0.1-µF ceramic capacitor should be connected from this pin to the SW pin.

5-V reference. This pin should be bypassed to ground with a 0.1-µF ceramic capacitor. This pin may be used
with an external dc load of 1 mA or less.

O

10-V reference used for gate drive of the N-channel synchronous rectifier. This pin should be bypassed by a 1-µF
ceramic capacitor. This pin may be used with an external dc load of 1 mA or less.

Output of the error amplifier , input to the PWM comparator. A feedback network is connected from this pin to the
VFB pin to compensate the overall loop. The comp pin is internally clamped above the peak of the ramp to
improve large signal transient response.

Floating gate drive for the high-side N-channel MOSFET. This pin switches from BOOST (MOSFET on) to SW
(MOSFET off).

Current limit pin, used to set the overcurrent threshold. An internal current sink from this pin to ground sets a
voltage drop across an external resistor connected from this pin to VCC. The voltage on this pin is compared
to the voltage drop (VIN −SW) across the high side MOSFET during conduction.

Gate drive for the N-channel synchronous rectifier. This pin switches from BP10 (MOSFET on) to ground
(MOSFET off).

Power ground reference for the device. There should be a low-impedance path from this pin to the source(s)
of the lower MOSFET(s).

Soft-start programming pin. A capacitor connected from this pin to ground programs the soft-start time. The
capacitor is charged with an internal current source of 2.3 µA. The resulting voltage ramp on the SS pin is used
as a second non-inverting input to the error amplifier. Output voltage regulation is controlled by the SS voltage
ramp until the voltage on the SS pin reaches the internal reference voltage , EA_REF V. Pulling this pin low
disables the controller.

Syncronization input for the device. This pin can be used to synchronize the oscillator to an external master
frequency. If synchronization is not used, connect this pin to SGND.

Inverting input to the error amplifier . In normal operation the voltage on this pin is equal to the EA_REF reference
voltage.



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

SLVS612 − APRIL 2006

FUNCTIONAL BLOCK DIAGRAM

VIN

ILIM

16

BP10

1115

BP10

RT

SYNC

BP5

COMP

EA_REF

VFB

SS/SD

2

1

BP5

3 7

8

4

7

6

7

Restart

Clock

Oscillator

+
+

0.7 V

+

7

RAMP

0.7 VREF

+

10 V Regulator

7

7
7
7
7

QR

CLK

7

3−Bit Up/Down

Fault Counter

Restart

7

7

7

Fault

CL

5

SGND

N−channel

Driver

BP10

7

N−channel

Driver

1.5 VREF

0.7 VREF

Reference

Voltages

Fault

7

CL

7

+

CLK

1.5 VREF

3.5 VREF
BP5

SQ

7

14

BOOST

13

HDRV

12

SW

10

LDRV

9

PGND

UDG−03081

6

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(1)

(2)

SLVS612 − APRIL 2006

APPLICATION INFORMATION

The TPS40056 allows the user to optimize the PWM controller to the specific application.
The TPS40056 is the controller of choice for synchronous buck designs, the output of which is required to track

another voltage. It has two quadrant operation and can source or sink output current, providing the best transient
response.

SW NODE RESISTOR AND DIODE

The SW node of the converter will be negative during the dead time when both the upper and lower MOSFETs
are off. The magnitude of this negative voltage is dependent on the lower MOSFET body diode and the output
current which flows during this dead time. This negative voltage could affect the operation of the controller,
especially at low input voltages.

Therefore, a resistor ( 3.3 Ω to 4.7 Ω) and Schottky diode must be placed between the lower MOSFET drain
and pin 12, SW, of the controller as shown in Figure 10. The Schottky diode must have a voltage rating to
accommodate the input voltage and ringing on the SW node of the converter . A 30-V Schottky such as a BAT54
or a 40-V Schottky such as a Zetex ZHCS400 or Vishay SD103AWS are adequate. These components are
shown in Figure 10 as R

and D2.

SW



SETTING THE SWITCHING FREQUENCY (PROGRAMMING THE CLOCK OSCILLATOR)

The TPS40056 has independent clock oscillator and ramp generator circuits. The clock oscillator serves as the
master clock to the ramp generator circuit. The switching frequency , f
a single resistor (R

R

+ ǒ

T

) to ground. The clock frequency is related to RT, in kΩ by Equation (1).

T

f

17.82 10

SW

1

* 23ǓkW

*6

in kHz, of the clock oscillator is set by

SW

UVLO OPERATION

The TPS40056 uses fixed UVLO protection. The fixed UVLO monitors the input voltage. The UVLO circuit holds
the soft-start low until the input voltage has exceeded the undervoltage threshold.

TRACKING CONFIGURATION (V

Setting the output, V
divider(s) R4,R5,R1 and R6 as shown in Figure 1. The voltage on the EA_REF input should be in the range of

0.2 V to 2.5 V. If the output voltage is less than 2.5 V, resistor R6 can be omitted. For example in the DDR case,
if the voltage V
and omit R6. In general, the output voltage, V
in Equation (2).

V

OUT

TRKIN

+ V

TRKIN

to track another voltage, V

OUT

ramps up to 2.5 V and it is desired to have V

R5

ǒ

R4 ) R5

TRACKING VIN)

OUT

R6 ) R1

Ǔ ǒ

R6

, is simply a matter of selecting the proper voltage

TRKIN

to track it and come up to 1.25 V, set R4=R5

, in terms of VTRKIN and the two voltage dividers is shown

OUT

Ǔ

V

OUT

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

0

4

BP10 AND BP5

SLVS612 − APRIL 2006

600

500

R4

V

TRKIN

Figure 1. Tracking Configuration, V

SWITCHING FREQUENCY

TIMING RESISTANCE

R5

vs

TPS40056PWP

EA_REF

4

5

SGND

6

SS

7

VFB

8 9PGNDCOMP

HDRV

SW

BP10

LDRV

13

12

11

10

10

+

V

OUT

R3

R1

−

UDG−06020

OUT

Tracks V

R6

TRKIN

vs

INPUT VOLTAGE

9
8

BP10

400

300

200

− Timing Resistance − kΩ
T

R

100

0

0

200 400 600 800 100

fSW − Switching Frequency − kHz

Figure 2

7

6

5
4

− Output Voltage − V
3

OUT

V

2

1
0

2

6481210 1

VIN − Input Voltage − V

Figure 3

BP5

8

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(3)

(4)

SLVS612 − APRIL 2006

APPLICATION INFORMATION

BP5 AND BP10 INTERNAL VOLTAGE REGULATORS

Start-up characteristics of the BP5 and BP10 regulators are shown in Figure 2. Slight variations in the BP5
occurs dependent upon the switching frequency. Variation in the BP10 regulation characteristics is also based
on the load presented by switching the external MOSFETs.

SELECTING THE INDUCTOR VALUE

The inductor value determines the magnitude of ripple current in the output capacitors as well as the load current
at which the converter enters discontinuous mode. Too large an inductance results in lower ripple current but
is physically larger for the same load current. Too small an inductance results in larger ripple currents and a
greater number of (or more expensive output capacitors for) the same output ripple voltage requirement. A good
compromise is to select the inductance value such that the converter doesn’t enter discontinuous mode until
the load approximated somewhere between 10% and 30% of the rated output. The inductance value is
described in equation (3).



where:.

D V

O

ǒ

VIN* V

L +

VIN DI f

is the output voltage

Ǔ

V

O

SW

O

(Henries)

D ∆I is the peak-to-peak inductor current

CALCULATING THE OUTPUT CAPACITANCE

The output capacitance depends on the output ripple voltage requirement, output ripple current, as well as any
output voltage deviation requirement during a load transient.

The output ripple voltage is a function of both the output capacitance and capacitor ESR. The worst case output
ripple is described in equation (4).

8 C

1

O

f

SW

Ǔ

V

ƫ

P*P

DV + DI

The output ripple voltage is typically between 90% and 95% due to the ESR component.
The output capacitance requirement typically increases in the presence of a load transient requirement. During

a step load, the output capacitance must provide energy to the load (light to heavy load step) or absorb excess
inductor energy (heavy to light load step) while maintaining the output voltage within acceptable limits. The
amount of capacitance depends on the magnitude of the load step, the speed of the loop and the size of the
inductor.

ESR )

ƪ

ǒ

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9



(5)

(6)

(7)

(8)

(9)

SLVS612 − APRIL 2006

APPLICATION INFORMATION

Stepping the load from a heavy load to a light load results in an output overshoot. Excess energy stored in the
inductor must be absorbed by the output capacitance. The energy stored in the inductor is described in
equation (5).

1

E

+

L I2(Joules)

L

2

where:

2

I

+

where:

D I
D I

Energy in the capacitor is described in equation (7).

where:

where:

D V
D V

Substituting equation (6) into equation (5), then substituting equation (8) into equation (7), then setting equation
(7) equal to equation (5), and then solving for C

is the output current under heavy load conditions

OH

is the output current under light load conditions

OL

E

+

C

2

V

+

is the final peak capacitor voltage

f

is the initial capacitor voltage

i

+

C

O

2

ǒ

Ǔ

ƪ

I

*

OH

1

C V2(Joules)

2

2

ǒ

Ǔ

ƪ

V

*

f

ǒ

ƪ

I

L

ǒ

ƪ

V

OH

Ǔ

f

2

ǒ

Ǔ

ǒ

(

ƫ

ƫ

V

ǒ

I

Ǔ

i

ǒ

Volts

OL

2

ƫ

Amperes

2

2

Ǔ

ƫ

I

OL

2

ǒ

Ǔ

V

i

2

Ǔ

*

2

ǒ

*

)

Ǔ

(Farads)

2

Ǔ

yields the capacitance described in equation (9).

O

10

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