Texas Instruments TPS1100D, TPS1100PWR, TPS1100DR, TPS1100PWLE Datasheet
TPS1100, TPS1100Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Low r
DS(on)
. . . 0.18 Ω Typ at VGS = –10 V
D
3 V Compatible
D
Requires No External V
CC
D
TTL and CMOS Compatible Inputs
D
V
GS(th)
= –1.5 V Max
D
Available in Ultrathin TSSOP Package (PW)
D
ESD Protection Up to 2 kV Per
MIL-STD-883C, Method 3015
description
The TPS1100 is a single P-channel
enhancement-mode MOSFET. The device has
been optimized for 3-V or 5-V power distribution
in battery-powered systems by means of Texas
Instruments LinBiCMOS process. With a
maximum V
GS(th)
of –1.5 V and an I
DSS
of only
0.5 µA, the TPS1100 is the ideal high-side switch
for low-voltage, portable battery-management
systems where maximizing battery life is a primary
concern. The low r
DS(on)
and excellent ac
characteristics (rise time 10 ns typical) make the
TPS1100 the logical choice for low-voltage
switching applications such as power switches for
pulse-width-modulated (PWM) controllers or
motor/bridge drivers.
The ultrathin thin shrink small-outline package or
TSSOP (PW) version with its smaller footprint and
reduction in height fits in places where other
P-channel MOSFET s cannot. The size advantage
is especially important where board real estate is
at a premium and height restrictions do not allow
for a small-outline integrated circuit (SOIC)
package.
AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
SMALL OUTLINE
(D)
PLASTIC DIP
(P)
CHIP FORM
(Y)
–40°C to 85°C TPS1100D TPS1100PWLE TPS1100Y
The D package is available taped and reeled. Add an R suffix to device type (e.g.,
TPS1100DR). The PW package is available only left-end taped and reeled
(indicated by the LE suffix on the device type; e.g., TPS1 100PWLE). The chip form
is tested at 25°C.
Caution. This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic
fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to
MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to these high-impedance circuits.
LinBiCMOS is a trademark of Texas Instruments Incorporated.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
2
3
4
8
7
6
5
SOURCE
SOURCE
SOURCE
GATE
DRAIN
DRAIN
DRAIN
DRAIN
D OR PW PACKAGE
(TOP VIEW)
D PACKAGE PW PACKAGE
SOURCE
DRAIN
GATE
ESD-
Protection
Circuitry
NOTE A: For all applications, all source pins should be connected
and all drain pins should be connected.
schematic
TPS1100, TPS1100Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
Such applications include notebook computers, personal digital assistants (PDAs), cellular telephones, and
PCMCIA cards. For existing designs, the D-packaged version has a pinout common with other p-channel
MOSFETs in SOIC packages.
TPS1100Y chip information
This chip, when properly assembled, displays characteristics similar to the TPS1 100. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform.
BONDING PAD ASSIGNMENTS
CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 × 4 MILS MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%
ALL DIMENSIONS ARE IN MILS
57
64
TPS1100Y
(2)
(6)
(1)
(3)
(7)
(8)
(5)(4)
DRAINSOURCE
SOURCE
SOURCE
GATE
DRAIN
DRAIN
DRAIN
(2)
(1)
(3)
(4)
(6)
(7)
(8)
(5)
TPS1100, TPS1100Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS
SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
†
UNIT
Drain-to-source voltage, V
DS
–15 V
Gate-to-source voltage, V
GS
2 or –15 V
p
TA = 25°C ±0.41
D package
TA = 125°C ±0.28
V
GS
= –
2.7 V
p
TA = 25°C ±0.4
PW package
TA = 125°C ±0.23
p
TA = 25°C ±0.6
D package
TA = 125°C ±0.33
V
GS
= –3
V
p
TA = 25°C ±0.53
°
PW package
TA = 125°C ±0.27
Continuous drain current (T
J
=
150°C), I
D
‡
p
TA = 25°C ±1
A
D package
TA = 125°C ±0.47
V
GS
= –4.5
V
p
TA = 25°C ±0.81
PW package
TA = 125°C ±0.37
p
TA = 25°C ±1.6
D package
TA = 125°C ±0.72
V
GS
= –
10 V
p
TA = 25°C ±1.27
PW package
TA = 125°C ±0.58
Pulsed drain current, I
D
‡
TA = 25°C ±7 A
Continuous source current (diode conduction), I
S
TA = 25°C –1 A
Storage temperature range, T
stg
–55 to 150 °C
Operating junction temperature range, T
J
–40 to 150 °C
Operating free-air temperature range, T
A
–40 to 125 °C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
‡
Maximum values are calculated using a derating factor based on R
θJA
= 158°C/W for the D package and R
θJA
= 248°C/W for the PW package.
These devices are mounted on a FR4 board with no special thermal considerations.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
‡
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 85°C
POWER RATING
TA = 125°C
POWER RATING
D 791 mW 6.33 mW/°C 506 mW 411 mW 158 mW
PW 504 mW 4.03 mW/°C 323 mW 262 mW 101 mW
‡
Maximum values are calculated using a derating factor based on R
θJA
= 158°C/W for the D package and R
θJA
= 248°C/W
for the PW package. These devices are mounted on an FR4 board with no special thermal considerations when tested.
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