TEXAS INSTRUMENTS TPS1100, TPS1100Y Technical data

CHIP FORM

TPS1100, TPS1100Y

SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS

SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995

D

Low r

DS(on)

D

3 V Compatible

D

Requires No External V

D

TTL and CMOS Compatible Inputs

D

V

GS(th)

D

Available in Ultrathin TSSOP Package (PW)

D

ESD Protection Up to 2 kV Per
MIL-STD-883C, Method 3015

. . . 0.18 Ω Typ at VGS = –10 V

CC

= –1.5 V Max

description

The TPS1100 is a single P-channel
enhancement-mode MOSFET. The device has
been optimized for 3-V or 5-V power distribution
in battery-powered systems by means of Texas
Instruments LinBiCMOS process. With a
maximum V

0.5 µA, the TPS1100 is the ideal high-side switch
for low-voltage, portable battery-management
systems where maximizing battery life is a primary
concern. The low r
characteristics (rise time 10 ns typical) make the
TPS1100 the logical choice for low-voltage
switching applications such as power switches for
pulse-width-modulated (PWM) controllers or
motor/bridge drivers.

of –1.5 V and an I

GS(th)

DS(on)

and excellent ac

DSS

of only

D PACKAGE PW PACKAGE

schematic

SOURCE
SOURCE
SOURCE

GATE

ESD-

Protection

Circuitry

GATE

D OR PW PACKAGE

(TOP VIEW)

1
2
3
4

DRAIN

8

DRAIN

7

DRAIN

6

DRAIN

5

SOURCE

The ultrathin thin shrink small-outline package or
TSSOP (PW) version with its smaller footprint and
reduction in height fits in places where other
P-channel MOSFET s cannot. The size advantage
is especially important where board real estate is
at a premium and height restrictions do not allow
for a small-outline integrated circuit (SOIC)
package.

AVAILABLE OPTIONS

T

A

–40°C to 85°C TPS1100D TPS1100PWLE TPS1100Y

The D package is available taped and reeled. Add an R suffix to device type (e.g.,
TPS1100DR). The PW package is available only left-end taped and reeled
(indicated by the LE suffix on the device type; e.g., TPS1 100PWLE). The chip form
is tested at 25°C.

Caution. This device contains circuits to protect its inputs and outputs against damage due to high static voltages or electrostatic
fields. These circuits have been qualified to protect this device against electrostatic discharges (ESD) of up to 2 kV according to
MIL-STD-883C, Method 3015; however, it is advised that precautions be taken to avoid application of any voltage higher than
maximum-rated voltages to these high-impedance circuits.

LinBiCMOS is a trademark of Texas Instruments Incorporated.

SMALL OUTLINE

NOTE A: For all applications, all source pins should be connected

PACKAGED DEVICES

PLASTIC DIP

(D)

DRAIN

and all drain pins should be connected.

(P)

(Y)

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1995, Texas Instruments Incorporated

1

TPS1100, TPS1100Y
SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS

SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995

description (continued)

Such applications include notebook computers, personal digital assistants (PDAs), cellular telephones, and
PCMCIA cards. For existing designs, the D-packaged version has a pinout common with other p-channel
MOSFETs in SOIC packages.

TPS1100Y chip information

This chip, when properly assembled, displays characteristics similar to the TPS1 100. Thermal compression or
ultrasonic bonding may be used on the doped aluminum bonding pads. The chips may be mounted with
conductive epoxy or a gold-silicon preform.

BONDING PAD ASSIGNMENTS

57

(5)
(6)

(8)
(7)

64

(4)

(3)

(1)
(2)

(1)

SOURCE
SOURCE

(2)
(3)

GATE

CHIP THICKNESS: 15 MILS TYPICAL
BONDING PADS: 4 × 4 MILS MINIMUM
TJmax = 150°C
TOLERANCES ARE ±10%
ALL DIMENSIONS ARE IN MILS

TPS1100Y

(8)
(7)

(6)
(5)(4)

DRAINSOURCE
DRAIN

DRAIN
DRAIN

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D package

V

2.7 V

PW package

D package

V

V

PW package

Continuous drain current (T

150°C), I

‡

A

D package

V

V

PW package

D package

V

10 V

PW package

TPS1100, TPS1100Y

SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS

SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Drain-to-source voltage, V
Gate-to-source voltage, V

Pulsed drain current, I
Continuous source current (diode conduction), I
Storage temperature range, T

Operating junction temperature range, T
Operating free-air temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 °C

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

‡

Maximum values are calculated using a derating factor based on R
These devices are mounted on a FR4 board with no special thermal considerations.

DS

GS

p

= –

GS

p

p

= –3

GS

p

°

=

J

‡

D

stg

D

p

= –4.5

GS

p

p

= –

GS

p

S

J

A

= 158°C/W for the D package and R

θJA

TA = 25°C ±0.41
TA = 125°C ±0.28
TA = 25°C ±0.4
TA = 125°C ±0.23
TA = 25°C ±0.6
TA = 125°C ±0.33
TA = 25°C ±0.53
TA = 125°C ±0.27
TA = 25°C ±1
TA = 125°C ±0.47
TA = 25°C ±0.81
TA = 125°C ±0.37
TA = 25°C ±1.6
TA = 125°C ±0.72
TA = 25°C ±1.27
TA = 125°C ±0.58
TA = 25°C ±7 A
TA = 25°C –1 A

= 248°C/W for the PW package.

θJA

2 or –15 V

–55 to 150 °C
–40 to 150 °C

–40 to 125 °C

†

UNIT

–15 V

DISSIPATION RATING TABLE

PACKAGE

D 791 mW 6.33 mW/°C 506 mW 411 mW 158 mW

PW 504 mW 4.03 mW/°C 323 mW 262 mW 101 mW

‡

Maximum values are calculated using a derating factor based on R
for the PW package. These devices are mounted on an FR4 board with no special thermal considerations when tested.

TA ≤ 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

‡

TA = 70°C

POWER RATING

θJA

TA = 85°C

POWER RATING

= 158°C/W for the D package and R

POWER RATING

TA = 125°C

= 248°C/W

θJA

3

TPS1100, TPS1100Y

PARAMETER

TEST CONDITIONS

UNIT

I

gg

V

V

V

A

r

mΩ

I

A

PARAMETER

TEST CONDITIONS

UNIT

DD

,

L

,

D

,

SINGLE P-CHANNEL ENHANCEMENT-MODE MOSFETS

SLVS078C – DECEMBER 1993 – REVISED AUGUST 1995

electrical characteristics at TJ = 25°C (unless otherwise noted)

static

TPS1100 TPS1100Y

MIN TYP MAX MIN TYP MAX

V

GS(th)

V

SD

I

GSS

DSS

DS(on)

g

fs

†

Pulse test: pulse duration ≤ 300 µs, duty cycle ≤ 2%

Gate-to-source
threshold voltage

Source-to-drain voltage
(diode-forward

†

voltage)
Reverse gate current,

drain short circuited to
source

Zero-gate-voltage drain
current

Static drain-to-source
on-state resistance

Forward
transconductance

†

†

VDS = VGS, ID = –250 µA –1 –1.25 –1.50 –1.25 V

IS = –1 A, VGS = 0 V –0.9 –0.9 V

VDS = 0 V, VGS = –12 V ±100 nA

= –12 V,

DS

VGS = –10 V ID = –1.5 A 180 180
VGS = –4.5 V
VGS = –3 V
VGS = –2.7 V

VDS = –10 V, ID = –2 A 2.5 2.5 S

= 0

GS

ID = –0.5 A 291 400 291

= –0.2

D

TJ = 25°C –0.5
TJ = 125°C –10

µ

476 700 476
606 850 606

dynamic

Q

g

Q

gs

Q

gd

t

d(on)

t

d(off)

t

r

t

f

t

rr(SD)

TPS1100, TPS1100Y

MIN TYP MAX

Total gate charge 5.45
Gate-to-source charge
Gate-to-drain charge 1.4
Turn-on delay time 4.5 ns
Turn-off delay time
Rise time
Fall time 2
Source-to-drain reverse recovery time IF = 5.3 A, di/dt = 100 A/µs 16

VDS = –10 V, VGS = –10 V, ID = –1 A

V

= –10 V, R

RG = 6 Ω,

= 10 Ω,I

See Figures 1 and 2

= –1 A,

0.87

13 ns
10

nC

ns

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265