Texas Instruments TPIC6A595DW, TPIC6A595NE, TPIC6A595DWR Datasheet
TPIC6A595
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS005A – APRIL 1993 – REVISED JANUARY 1995
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Low r
DS(on)
...1 Ω Typ
D
Output Short-Circuit Protection
D
Avalanche Energy ...75 mJ
D
Eight 350-mA DMOS Outputs
D
50-V Switching Capability
D
Devices Are Cascadable
D
Low Power Consumption
description
The TPIC6A595 is a monolithic, high-voltage,
high-current power logic 8-bit shift register
designed for use in systems that require relatively
high load power. The device contains a built-in
voltage clamp on the outputs for inductive
transient protection. Power driver applications
include relays, solenoids, and other medium-current or high-voltage loads. Each open-drain
DMOS transistor features an independent
chopping current-limiting circuit to prevent
damage in the case of a short circuit.
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit, D-type storage
register. Data transfers through both the shift and
storage registers on the rising edge of the shiftregister clock (SRCK) and the register clock
(RCK), respectively. The storage register
transfers data to the output buffer when shiftregister clear (SRCLR
) is high. When SRCLR is
low, the input shift register is cleared. When output
enable (G) is held high, all data in the output buffers is held low and all drain outputs are off. When G is held
low, data from the storage register is transparent to the output buf fers. The serial output (SER OUT) allows for
cascading of the data from the shift register to additional devices.
Outputs are low-side, open-drain DMOS transistors with output ratings of 50 V and a 350-mA continuous sink
current capability . When data in the output buffers is low, the DMOS-transistor outputs are off. When data is high,
the DMOS-transistor outputs have sink current capability.
Separate power ground (PGND) and logic ground (LGND) terminals are provided to facilitate maximum system
flexibility . All PGND terminals are internally connected, and each PGND terminal must be externally connected
to the power system ground in order to minimize parasitic impedance. A single-point connection between LGND
and PGND must be made externally in a manner that reduces crosstalk between the logic and load circuits.
The TPIC6A595 is offered in a thermally-enhanced dual-in-line (NE) package and a wide-body surface-mount
(DW) package. The TPIC6A595 is characterized for operation over the operating case temperature range of
–40°C to 125°C.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
DRAIN2
DRAIN3
SRCLR
G
PGND
PGND
RCK
SRCK
DRAIN4
DRAIN5
DRAIN1
DRAN0
SER IN
V
CC
PGND
PGND
LGND
SER OUT
DRAIN7
DRAIN6
NE PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DRAIN2
DRAIN3
SRCLR
G
PGND
PGND
PGND
PGND
RCK
SRCK
DRAIN4
DRAIN5
DRAIN1
DRAIN0
SER IN
V
CC
PGND
PGND
PGND
PGND
LGND
SER OUT
DRAIN7
DRAIN6
DW PACKAGE
(TOP VIEW)
TPIC6A595
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS005A – APRIL 1993 – REVISED JANUARY 1995
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
SRG8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
EN3
C2
R
C1
1D
G
RCK
SRCLR
SRCK
SER IN
DRAIN0
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
DRAIN6
DRAIN7
SER OUT
2
2
3
3
TPIC6A595
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS005A – APRIL 1993 – REVISED JANUARY 1995
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
G
RCK
SRCLR
SRCK
SER IN
CLR
D
C1
D
C2
CLR
D
C1
SER OUT
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
D
C2
D
C2
D
C2
D
C2
D
C2
D
C2
D
C2
DRAIN0
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
DRAIN6
DRAIN7
Current Limit and Charge Pump
PGND
TPIC6A595
POWER LOGIC 8-BIT SHIFT REGISTER
SLIS005A – APRIL 1993 – REVISED JANUARY 1995
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematic of inputs and outputs
EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS
V
CC
Input
LGND
PGND
DRAIN
25 V
12 V
LGND
R
SENSE
TYPICAL OF SERIAL OUT
V
CC
LGND
SER OUT
absolute maximum ratings over recommended operating case temperature range (unless
otherwise noted)
†
Logic supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic input voltage range, V
I
–0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power DMOS drain-to-source voltage, VDS (see Note 2) 50 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous source-drain diode anode current 1 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed source-drain diode anode current (see Note 3) 2 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed drain current, each output, all outputs on, I
Dn,
T
A
= 25°C (see Note 3) 1.1 A. . . . . . . . . . . . . . . . . . . . .
Continuous drain current, each output, all outputs on, I
Dn,
TA = 25°C 350 mA. . . . . . . . . . . . . . . . . . . . . . . . . .
Peak drain current, single output, T
A
= 25°C (see Note 3) 1.1 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Single-pulse avalanche energy, E
AS
(see Figure 6) 75 mJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Avalanche current, IAS (see Note 4) 600 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating case temperature range, TC –40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ –40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to LGND and PGND.
2. Each power DMOS source is internally connected to PGND.
3. Pulse duration ≤ 100 µs and duty cycle ≤ 2 %.
4. DRAIN supply voltage = 15 V, starting junction temperature (TJS) = 25°C, L = 210 mH, IAS = 600 mA (see Figure 6).
DISSIPATION RATING TABLE
PACKAGE
TC ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TC = 25°C
TC = 125°C
POWER RATING
DW 1750 mW 14 mW/°C 350 mW
NE 2500 mW 20 mW/°C 500 mW
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