TPIC6A259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS004B – APRIL 1993 – REVISED SEPTEMBER 1995
• Low r
DS(on)
...1 Ω Typ
• Output Short-Circuit Protection
• Avalanche Energy...75 mJ
•Eight 350-mA DMOS Outputs
• 50-V Switching Capability
• Four Distinct Function Modes
• Low Power Consumption
description
This power logic 8-bit addressable latch controls
open-drain DMOS-transistor outputs and is
designed for general-purpose storage applications in digital systems. Specific uses include
working registers, serial-holding registers, and
decoders or demultiplexers. This is a multifunctional device capable of operating as eight
addressable latches or an 8-line demultiplexer
with active-low DMOS outputs. Each open-drain
DMOS transistor features an independent
chopping current-limiting circuit to prevent
damage in the case of a short circuit.
Four distinct modes of operation are selectable by
controlling the clear (CLR
as enumerated in the function table. In the
addressable-latch mode, data at the data-in (D)
terminal is written into the addressed latch. The
addressed DMOS-transistor output inverts the
data input with all unaddressed DMOS-transistor
outputs remaining in their previous states. In the
memory mode, all DMOS-transistor outputs
remain in their previous states and are unaffected
by the data or address inputs. To eliminate the
possibility of entering erroneous data in the latch,
enable G
should be held high (inactive) while the
address lines are changing. In the 8-line
demultiplexing mode, the addressed output is
inverted with respect to the D input and all other
outputs are high. In the clear mode, all outputs are
high and unaffected by the address and data
inputs.
Separate power ground (PGND) and logic ground
(LGND) terminals are provided to facilitate
maximum system flexibility. All PGND terminals
are internally connected, and each PGND
terminal must be externally connected to the
power system ground in order to minimize
parasitic impedance. A single-point connection
between LGND and PGND must be made
externally in a manner that reduces crosstalk
between the logic and load circuits.
) and enable (G) inputs
NE PACKAGE
(TOP VIEW)
DRAIN2
DRAIN3
LGND
PGND
PGND
DRAIN4
DRAIN5
DRAIN2
DRAIN3
LGND
PGND
PGND
PGND
PGND
DRAIN4
DRAIN5
INPUTS
CLR G
HHLLH
H H X Memory
LLLLH
LH
D
L
L
X
LATCH SELECTION TABLE
SELECT INPUTS DRAIN
S2 S1 S0
L
L
L
L
H
H
H
H
1
2
S1
3
4
5
6
7
S2
8
G
9
10
DW PACKAGE
(TOP VIEW)
1
2
S1
3
4
5
6
7
8
S2
9
G
10
11
12
FUNCTION TABLE
OUTPUT OF
ADDRESSED
DRAIN
L
H
Q
io
L
H
H H Clear
L
L
L
H
H
L
H
H
L
L
L
H
H
L
H
H
DRAIN1
20
DRAIN0
19
S0
18
V
17
CC
PGND
16
PGND
15
14
CLR
13
D
12
DRAIN7
11
DRAIN6
DRAIN1
24
DRAIN0
23
S0
22
V
21
CC
PGND
20
PGND
19
PGND
18
PGND
17
CLR
16
D
15
DRAIN7
14
DRAIN6
13
EACH
OTHER
DRAIN
Q
io
Q
io
Q
io
H
H
ADDRESSED
0
1
2
3
4
5
6
7
FUNCTION
Addressable
Latch
8-Line
Demultiplexer
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1995, Texas Instruments Incorporated
1
TPIC6A259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS004B – APRIL 1993 – REVISED SEPTEMBER 1995
description (continued)
The TPIC6A259 is offered in a thermally-enhanced dual-in-line (NE) package and a wide-body , surface-mount
(DW) package. The TPIC6A259 is characterized for operation over the operating case temperature range of
–40°C to 125°C.
logic symbol
†
0S0
0
2S2
G8
Z9D
Z10
9,0D
10,0R
9,1D
10,1R
9,2D
10,2R
9,3D
10,3R
9,4D
10,4R
9,5D
10,5R
9,6D
10,6R
9,7D
10,7R
8M
7
DRAIN0
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
DRAIN6
DRAIN7
S1
G
CLR
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
D
CLR
G
S0
TPIC6A259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS004B – APRIL 1993 – REVISED SEPTEMBER 1995
DRAIN0
D
C1
CLR
DRAIN1
D
C1
CLR
DRAIN2
S1
S2
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
D
C1
CLR
DRAIN3
DRAIN4
Current Limit and Charge Pump
DRAIN5
DRAIN6
DRAIN7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
C1
CLR
PGND
3
TPIC6A259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS004B – APRIL 1993 – REVISED SEPTEMBER 1995
schematic of inputs and outputs
EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS
V
CC
Input
25 V
LGND
12 V
LGND
R
SENSE
DRAIN
PGND
absolute maximum ratings over the recommended operating case temperature range (unless
otherwise noted)
Logic supply voltage, V
Logic input voltage range, V
Power DMOS drain-to-source voltage, V
Continuous source-to-drain diode anode current 1 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed source-to-drain diode anode current (see Note 3) 2 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed drain current, each output, all outputs on, I
Continuous drain current, each output, all outputs on, I
Peak drain current single output, T
Single-pulse avalanche energy, E
Avalanche current, I
Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, T
Operating case temperature range, T
Storage temperature range, T
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to LGND and PGND.
2. Each power DMOS source is internally connected to PGND.
3. Pulse duration ≤ 100 µs, and duty cycle ≤ 2%.
4. DRAIN supply voltage = 15 V , starting junction temperature (TJS) = 25°C, L = 210 mH, and IAS = 600 mA (see Figure 6).
†
(see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
–0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
C
(see Figure 6) 75 mJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Note 4) 600 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AS
AS
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
(see Note 2) 50 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS
, T
= 25°C (see Note 3) 1.1 A. . . . . . . . . . . . . . . . . . . . .
D
C
T
= 25°C 350 mA. . . . . . . . . . . . . . . . . . . . . . . . . . .
D,
C
= 25°C (see Note 3) 1.1 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C
J
DISSIPATION RATING TABLE
PACKAGE
DW 1750 mW 14 mW/°C 350 mW
NE 2500 mW 20 mW/°C 500 mW
4
TC ≤ 25°C
POWER RATING
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DERATING FACTOR
ABOVE TC = 25°C
TC = 125°C
POWER RATING
TPIC6A259
IDOff-state drain current
A
r
Ω
L
,
D
,
F
µ
R
Thermal resistance, junction-to-case
All eight outputs with equal power
°C/W
R
Thermal resistance, junction-to-ambient
All eight outputs with equal power
°C/W
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS004B – APRIL 1993 – REVISED SEPTEMBER 1995
recommended operating conditions
MIN MAX UNIT
Logic supply voltage, V
High-level input voltage, V
Low-level input voltage, V
Pulsed drain output current, TC = 25°C, VCC = 5 V (see Notes 3 and 5) –1.8 0.6 A
Setup time, D high before G↑,tsu (see Figure 2) 10 ns
Hold time, D high before G↑, th (see Figure 2) 5 ns
Pulse duration, tw (see Figure 2) 15 ns
Operating case temperature, T
CC
IH
IL
C
electrical characteristics, VCC = 5 V, TC = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
(BR)DSX
V
SD
I
IH
I
IL
I
CC
I
OK
I
(nom)
DS(on)
Drain-to-source breakdown voltage ID = 1 mA 50 V
Source-to-drain diode forward
voltage
High-level input current VI = V
Low-level input current VI = 0 –1 µA
Logic supply current IO = 0, VI = VCC or 0 0.5 5 mA
Output current at which chopping
starts
Nominal current
Static drain-to-source on-state
resistance
IF = 350 mA, See Note 3 0.8 1.1 V
CC
TC = 25°C, See Note 5 and Figures 3 and 4 0.6 0.8 1.1 A
V
VCC = 5 V, See Notes 5, 6, and 7
VDS = 40 V, TC = 25°C 0.1 1
VDS = 40 V, TC = 125°C 0.2 5
ID = 350 mA, TC = 25°C
ID = 350 mA, TC = 125°C
DS(on)
= 0.5 V, I
= ID,TC = 85°C,
(nom)
See Notes 5 and 6
and Figures 9 and 10
4.5 5.5 V
0.85 V
CC
0 0.15 V
–40 125 °C
V
CC
CC
350 mA
1 1.5
1.7 2.5
1 µA
V
V
µ
switching characteristics, VCC = 5 V, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
Propagation delay time, high- to low-level output from D 30 ns
PHL
t
Propagation delay time, low- to high-level output from D
PLH
t
Rise time, drain output
r
t
Fall time, drain output 30 ns
f
t
Reverse-recovery-current rise time
a
t
Reverse-recovery time
rr
NOTES: 3. Pulse duration ≤ 100 µs and duty cycle ≤ 2%.
5. Technique should limit TJ – TC to 10°C maximum.
6. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
7. Nominal current is defined for a consistent comparison between devices from different sources. It is the current that produces a
voltage drop of 0.5 V at TC = 85°C.
thermal resistance
PARAMETER TEST CONDITIONS MIN MAX UNIT
θJC
θJA
DW
NE
DW
NE
C
= 30 pF, I
See Figures 1, 2, and 11
IF = 350 mA, di/dt = 20 A/µs,
See Notes 5 and 6 and Figure 5
p
p
= 350 mA,
p
p
125 ns
60 ns
100 ns
300 ns
10
°
10
50
°
50
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
TPIC6A259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS004B – APRIL 1993 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
Word
Generator
(see Note A)
Word
Generator
(see Note A)
Word
Generator
(see Note A)
5 V 24 V
V
CC
S0
S1
S2
DUT
G
CLR
D
TEST CIRCUIT
TEST CIRCUIT
LGND
5 V
V
CC
D
G
LGND
DRAIN
PGND
DUT
CLR
DRAIN
PGND
CLR
I
D
RL = 68 Ω
Output
CL = 30 pF
(see Note B)
S0
S1
S2
G
D
DRAIN5
DRAIN3
Figure 1. Typical Operation Mode
G
24 V
I
D
68 Ω
Output
CL = 30 pF
(see Note B)
D
Output
G
D
VOLTAGE WAVEFORMS
50%
t
PLH
90%
10%
t
r
SWITCHING TIMES
50%
t
su
50%
t
w
INPUT SETUP AND HOLD WAVEFORMS
50%
t
50%
90%
h
t
PHL
10%
t
5 V
0 V
5 V
0 V
5 V
0 V
5 V
0 V
5 V
0 V
5 V
0 V
24 V
0.5 V
24 V
0.5 V
5 V
0 V
5 V
0 V
24 V
0.5 V
f
5 V
0 V
5 V
0 V
Figure 2. Test Circuit, Switching Times, and Voltage Waveforms
NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, tw = 300 ns, pulsed repetition rate (PRR) = 5 kHz,
6
ZO = 50 Ω.
B. CL includes probe and jig capacitance.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TPIC6A259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS004B – APRIL 1993 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
OUTPUT CURRENT
vs
TIME FOR INCREASING LOAD RESISTANCE
1.5
I
1.25
I
OK
1
0.75
0.5
O
I – Output Current – A
0.25
0
NOTES: A. Figure 3 illustrates the output current characteristics of the device energizing a load having initially low, increasing resistance, e.g.,
an incandescent lamp. In region 1, chopping occurs and the peak current is limited to IOK. In region 2, output current is continuous.
The same characteristics occur in reverse order when the device energizes a load having an initially high, decreasing resistance.
B. Region 1 duty cycle is approximately 2%.
Region 1
Time
(see Notes A
and B)
Region 2
OK
O
I – Output Current
First output current pulses after turn-on in chopping mode
with resistive load.
REGION 1 CURRENT WAVEFORM
0
t
t
1
t
≈ 40 µs
1
t
2
1
t2 ≈ 2.5 ms
Time
t
t
2
1
Figure 3. Chopping-Mode Characteristics
OUTPUT CURRENT LIMIT
vs
CASE TEMPERATURE
1.5
VCC = 5.5 V
1.2
0.9
0.6
O
I – Output Current Limit – A
0.3
0
– 50 – 25 0 25 50 75
VCC = 4.5 V
100
TC – Case Temperature – °C
Figure 4
125 150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
TPIC6A259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS004B – APRIL 1993 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
DRAIN
Circuit
Under
Test
I
(see Note B)
t
1
V
(see Note A)
NOTES: A. The VGG amplitude and RG are adjusted for di/dt = 20 A/µs. A VGG double-pulse train is used to set IF = 0.35 A, where t1 = 10 µs,
GG
t2 = 7 µs, and t3 = 3 µs.
B. The DRAIN terminal under test is connected to the TP K test point. All other terminals are connected together and connected to the
TP A test point.
C. IRM = maximum recovery current
F
t
2
t
3
R
G
50 Ω
TEST CIRCUIT
TP K
Driver
L = 1 mH
TP A
2500 µF
250 V
24 V
+
–
(see Note C)
0.35 A
I
F
0
I
RM
di/dt = 20 A/µs
t
a
t
rr
CURRENT WAVEFORM
25% of I
RM
Figure 5. Reverse-Recovery-Current Test Circuit and Waveforms of Source-Drain Diode
5 V
V
CC
S2
S1
Word
Generator
(see Note A)
†
Non-JEDEC symbol for avalanche time.
NOTES: A. The word generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω.
B. Input pulse duration, tw, is increased until peak current IAS = 600 mA.
Energy test level is defined as EAS = (IAS × V
S0
DUT
G
D
CLR
LGND
TEST CIRCUIT
DRAIN
PGND
I
D
15 V
1 Ω
L = 210 mH
V
DS
(BR)DSX
Input
I
D
V
DS
× tav)/2 = 75 mJ.
See Note B
VOLTAGE AND CURRENT WAVEFORMS
Figure 6. Single-Pulse Avalanche Energy Test Circuit and Waveforms
t
w
tav†
5 V
0 V
IAS = 600 mA
V
(BR)DSX
MIN
= 50 V
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POWER LOGIC 8-BIT ADDRESSABLE LATCH
TYPICAL CHARACTERISTICS
TPIC6A259
SLIS004B – APRIL 1993 – REVISED SEPTEMBER 1995
MAXIMUM CONTINUOUS
DRAIN CURRENT OF EACH OUTPUT
vs
NUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY
0.7
0.6
TA = 25°C
0.5
0.4
TA = 100°C
0.3
of Each Output – A
0.2
– Maximum Continuous Drain Current
0.1
D
I
0
12345
N – Number of Outputs Conducting Simultaneously
TA = 125°C
Figure 7 Figure 8
VCC = 5 V
678
MAXIMUM PEAK DRAIN CURRENT
OF EACH OUTPUT
vs
NUMBER OF OUTPUTS CONDUCTING
SIMULTANEOUSLY
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
– Maximum Peak Drain Current of Each Output – A
0
DM
I
12345678
N – Number of Outputs Conducting Simultaneously
d = 80%
VCC = 5 V
TA = 25°C
d = tw/t
period
d = 1 ms/t
period
d = 20%d = 50%
STATIC DRAIN-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
Ω
2
1.75
TC = 125°C
1.5
1.25
TC = 25°C
1
0.75
TC = – 40°C
0.5
– Static Drain-Source On-State Resistance –r
0.25
0
DS(on)
0 0.2 0.4 0.6
Current Limit
ID – Drain Current – A
VCC = 5 V
See Note A
0.8 1
Figure 9 Figure 10
NOTE A: Technique should limit TJ – TC to 10°C maximum.
1.2
STATIC DRAIN-SOURCE
ON-STATE RESISTANCE
vs
LOGIC SUPPLY VOLTAGE
Ω
2
1.75
T
= 125°C
1.5
1.25
1
0.75
0.5
0.25
– Static Drain-Source On-State Resistance –r
DS(on)
ID = 350 mA
See Note A
0
45 67
C
TC = 25°C
TC = –40°C
VCC – Logic Supply Voltage – V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
TPIC6A259
POWER LOGIC 8-BIT ADDRESSABLE LATCH
SLIS004B – APRIL 1993 – REVISED SEPTEMBER 1995
TYPICAL CHARACTERISTICS
SWITCHING TIME
CASE TEMPERATURE
140
ID = 350 mA
See Note A
120
100
80
60
Switching Time – ns
40
20
– 50 0 50 100 150
NOTE A: Technique should limit TJ – TC to 10°C maximum.
t
PLH
TC – Case Temperature – °C
vs
t
r
t
PHL
t
f
NE PACKAGE
TRANSIENT THERMAL IMPEDANCE
vs
ON TIME
100
C
°
d = 50%
d = 20%
10
d = 10%
d = 5%
d = 2%
1
Z – Transient Thermal Impedance – /W
JA
θ
Single Pulse
0.1
0.001 0.01 1 10 100
0.1
t – On Time – s
Figure 11
THERMAL INFORMATION
The single-pulse curve represents measured data. The curves
for various pulse durations are based on the following equation:
Z
q
JA
Where:
ǒ
Z
t
w
q
ǒ
Z
t
c
q
ǒ
Z
tw)
t
q
1000
c
t
w
+
Ť
Ť
t
c
ǒ
)
Ǔ
Ǔ
Ǔ
d = tw/t
Ǔ
Z
t
w
q
= the single-pulse thermal impedance
for t = tw seconds
= the single-pulse thermal impedance
for t = tc seconds
= the single-pulse thermal impedance
for t = tw + tc seconds
c
t
w
–Z
)
R
q
JA
ǒ
Ǔ
t
c
q
t
c
t
w
1 –
Ť
Ť
t
c
I
D
0
ǒ
tw)
Ǔ
t
c
Z
q
10
Figure 12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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