Texas Instruments TPIC6A259NE, TPIC6A259DW Datasheet

TPIC6A259

POWER LOGIC 8-BIT ADDRESSABLE LATCH

SLIS004B – APRIL 1993 – REVISED SEPTEMBER 1995

• Low r

DS(on)

...1 Ω Typ

• Output Short-Circuit Protection

• Avalanche Energy...75 mJ

•Eight 350-mA DMOS Outputs

• 50-V Switching Capability

• Four Distinct Function Modes

• Low Power Consumption

description

This power logic 8-bit addressable latch controls
open-drain DMOS-transistor outputs and is
designed for general-purpose storage appli­cations in digital systems. Specific uses include
working registers, serial-holding registers, and
decoders or demultiplexers. This is a multi­functional device capable of operating as eight
addressable latches or an 8-line demultiplexer
with active-low DMOS outputs. Each open-drain
DMOS transistor features an independent
chopping current-limiting circuit to prevent
damage in the case of a short circuit.

Four distinct modes of operation are selectable by
controlling the clear (CLR
as enumerated in the function table. In the
addressable-latch mode, data at the data-in (D)
terminal is written into the addressed latch. The
addressed DMOS-transistor output inverts the
data input with all unaddressed DMOS-transistor
outputs remaining in their previous states. In the
memory mode, all DMOS-transistor outputs
remain in their previous states and are unaffected
by the data or address inputs. To eliminate the
possibility of entering erroneous data in the latch,
enable G

should be held high (inactive) while the
address lines are changing. In the 8-line
demultiplexing mode, the addressed output is
inverted with respect to the D input and all other
outputs are high. In the clear mode, all outputs are
high and unaffected by the address and data
inputs.

Separate power ground (PGND) and logic ground
(LGND) terminals are provided to facilitate
maximum system flexibility. All PGND terminals
are internally connected, and each PGND
terminal must be externally connected to the
power system ground in order to minimize
parasitic impedance. A single-point connection
between LGND and PGND must be made
externally in a manner that reduces crosstalk
between the logic and load circuits.

) and enable (G) inputs

NE PACKAGE

(TOP VIEW)

DRAIN2
DRAIN3

LGND
PGND
PGND

DRAIN4
DRAIN5

DRAIN2
DRAIN3

LGND
PGND
PGND
PGND
PGND

DRAIN4
DRAIN5

INPUTS

CLR G

HHLLH

H H X Memory
LLLLH

LH

D

L

L

X

LATCH SELECTION TABLE

SELECT INPUTS DRAIN

S2 S1 S0

L
L
L
L
H
H
H
H

1
2

S1

3
4
5
6
7

S2

8

G

9
10

DW PACKAGE

(TOP VIEW)

1
2

S1

3
4
5
6
7
8

S2

9

G

10
11
12

FUNCTION TABLE

OUTPUT OF

ADDRESSED

DRAIN

L

H

Q

io

L
H
H H Clear

L

L

L

H

H

L

H

H

L

L

L

H

H

L

H

H

DRAIN1

20

DRAIN0

19

S0

18

V

17

CC

PGND

16

PGND

15
14

CLR

13

D

12

DRAIN7

11

DRAIN6

DRAIN1

24

DRAIN0

23

S0

22

V

21

CC

PGND

20

PGND

19

PGND

18

PGND

17

CLR

16

D

15

DRAIN7

14

DRAIN6

13

EACH

OTHER

DRAIN

Q

io

Q

io

Q

io

H
H

ADDRESSED

0
1
2
3
4
5
6
7

FUNCTION

Addressable
Latch

8-Line
Demultiplexer

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1995, Texas Instruments Incorporated

1

TPIC6A259
POWER LOGIC 8-BIT ADDRESSABLE LATCH

SLIS004B – APRIL 1993 – REVISED SEPTEMBER 1995

description (continued)

The TPIC6A259 is offered in a thermally-enhanced dual-in-line (NE) package and a wide-body , surface-mount
(DW) package. The TPIC6A259 is characterized for operation over the operating case temperature range of
–40°C to 125°C.

logic symbol

†

0S0

0

2S2
G8
Z9D

Z10

9,0D
10,0R

9,1D
10,1R

9,2D
10,2R

9,3D
10,3R

9,4D
10,4R

9,5D
10,5R

9,6D

10,6R

9,7D
10,7R

8M

7

DRAIN0

DRAIN1

DRAIN2

DRAIN3

DRAIN4

DRAIN5

DRAIN6

DRAIN7

S1

G

CLR

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

D

CLR

G

S0

TPIC6A259

POWER LOGIC 8-BIT ADDRESSABLE LATCH

SLIS004B – APRIL 1993 – REVISED SEPTEMBER 1995

DRAIN0

D
C1
CLR

DRAIN1

D
C1
CLR

DRAIN2

S1

S2

D
C1
CLR

D
C1
CLR

D
C1
CLR

D
C1
CLR

D
C1
CLR

DRAIN3

DRAIN4

Current Limit and Charge Pump

DRAIN5

DRAIN6

DRAIN7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D
C1
CLR

PGND

3

TPIC6A259
POWER LOGIC 8-BIT ADDRESSABLE LATCH

SLIS004B – APRIL 1993 – REVISED SEPTEMBER 1995

schematic of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS

V

CC

Input

25 V

LGND

12 V

LGND

R

SENSE

DRAIN

PGND

absolute maximum ratings over the recommended operating case temperature range (unless
otherwise noted)

Logic supply voltage, V
Logic input voltage range, V
Power DMOS drain-to-source voltage, V

Continuous source-to-drain diode anode current 1 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pulsed source-to-drain diode anode current (see Note 3) 2 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pulsed drain current, each output, all outputs on, I
Continuous drain current, each output, all outputs on, I
Peak drain current single output, T
Single-pulse avalanche energy, E
Avalanche current, I

Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating virtual junction temperature range, T
Operating case temperature range, T
Storage temperature range, T

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values are with respect to LGND and PGND.

2. Each power DMOS source is internally connected to PGND.

3. Pulse duration ≤ 100 µs, and duty cycle ≤ 2%.

4. DRAIN supply voltage = 15 V , starting junction temperature (TJS) = 25°C, L = 210 mH, and IAS = 600 mA (see Figure 6).

†

(see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

–0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

C

(see Figure 6) 75 mJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

(see Note 4) 600 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AS

AS

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

(see Note 2) 50 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DS

, T

= 25°C (see Note 3) 1.1 A. . . . . . . . . . . . . . . . . . . . .

D

C

T

= 25°C 350 mA. . . . . . . . . . . . . . . . . . . . . . . . . . .

D,

C

= 25°C (see Note 3) 1.1 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C

J

DISSIPATION RATING TABLE

PACKAGE

DW 1750 mW 14 mW/°C 350 mW

NE 2500 mW 20 mW/°C 500 mW

4

TC ≤ 25°C

POWER RATING

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DERATING FACTOR

ABOVE TC = 25°C

TC = 125°C

POWER RATING