Texas Instruments TPIC6596N, TPIC6596DWR, TPIC6596DW Datasheet

TPIC6596

POWER LOGIC 8-BIT SHIFT REGISTER

SLIS096 – APRIL 2000

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Low r

DS(on)

. . . 1.3 Ω Typ

D

Avalanche Energy ...75 mJ

D

Eight Power DMOS Transistor Outputs of
250-mA Continuous Current

D

1.5-A Pulsed Current Per Output

D

Output Clamp Voltage at 45 V

D

Enhanced Cascading for Multiple Stages

D

All Registers Cleared With Single Input

D

Low Power Consumption

description

The TPIC6596 is a monolithic, high-voltage, high­current power 8-bit shift register designed for use
in systems that require relatively high load power.
The device contains a built-in voltage clamp on
the outputs for inductive transient protection.
Power driver applications include relays, sole­noids, and other medium-current or high-voltage
loads.

This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage
register. Data transfers through both the shift and
storage registers on the rising edge of the
shift-register clock (SRCK) and the register clock
(RCK) respectively . The storage register transfers
data to the output buffer when shift-register clear
(SRCLR

) is high. When SRCLR is low, all
registers in the device are cleared. When output
enable (G) is held high, all data in the output
buffers is held low and all drain outputs are off.
When G

is held low, data from the storage register
is transparent to the output buffers. The serial
output (SER OUT) is clocked out of the device on
the falling edge of SRCK to provide additional hold time for cascaded applications. This will provide improved
performance for applications where clock signals may be skewed, devices are not located near one another,
or the system must tolerate electromagnetic interference.

Outputs are low-side, open-drain DMOS transistors with output ratings of 45 V and 250-mA continuous sink
current capability. When data in the output buffers is low, the DMOS-transistor outputs are off. When data is
high, the DMOS-transistor outputs have sink current capability.

Separate power and logic level ground pins are provided to facilitate maximum system flexibility . Pins 1, 10, 1 1,
and 20 are internally connected, and each pin must be externally connected to the power system ground in order
to minimize parasitic inductance. A single-point connection between pin 19, logic ground (LGND), and pins 1,
10, 1 1, and 20, power grounds (PGND), must be externally made in a manner that reduces crosstalk between
the logic and load circuits.

The TPIC6596 is characterized for operation over the operating case temperature range of –40°C to 125°C.

Copyright  2000, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

†

This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

PGND

V

CC

SER IN
DRAIN0
DRAIN1
DRAIN2
DRAIN3

SRCLR

G

PGND

PGND
LGND
SER OUT
DRAIN7
DRAIN6
DRAIN5
DRAIN4
SRCK
RCK
PGND

DW OR N PACKAGE

(TOP VIEW)

logic symbol

†

2

SRG8

9
12

8
13

3

EN3

C2

R

C1

1D

G

RCK

SRCLR

SRCK

SER IN

4

6

5

14

7

16

15

18

17

DRAIN0
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
DRAIN6
DRAIN7
SER OUT

2

TPIC6596
POWER LOGIC 8-BIT SHIFT REGISTER

SLIS096 – APRIL 2000

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

G

RCK

SRCLR

SRCK

SER IN

CLR

D

C1

D

C2

SER OUT

4

DRAIN0

5

DRAIN1

1, 10, 11, 20

PGND

6

DRAIN2

7

DRAIN3

14

DRAIN4

15

DRAIN5

16

DRAIN6

17

DRAIN7

9

8

3

12

13

18

CLR

D

C1

CLR

D

C1

CLR

D

C1

CLR

D

C1

CLR

D

C1

CLR

D

C1

CLR

D

C1

D

C2

D

C2

D

C2

D

C2

D

C2

D

C2

D

C2

CLR

CLR

CLR

CLR

CLR

CLR

CLR

CLR

CLR

D

C1

TPIC6596

POWER LOGIC 8-BIT SHIFT REGISTER

SLIS096 – APRIL 2000

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

schematic of inputs and outputs

EQUIVALENT OF EACH INPUT TYPICAL OF ALL DRAIN OUTPUTS

V

CC

Input

LGND

PGND

DRAIN

45 V

12 V

25 V

12 V

LGND

absolute maximum ratings over recommended operating case temperature range (unless
otherwise noted)

†

Logic supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Logic input voltage range, VI –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power DMOS drain-to-source voltage, VDS (see Note 2) 45 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous source-drain diode anode current 1 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pulsed source-drain diode anode current 2 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pulsed drain current, each output, all outputs on, I

Dn,

T

A

= 25°C (see Note 3) 750 mA. . . . . . . . . . . . . . . . . . .

Continuous drain current, each output, all outputs on, I

Dn,

TA = 25°C 250 mA. . . . . . . . . . . . . . . . . . . . . . . . . .

Peak drain current single output, I

DM,TA

= 25°C (see Note 3) 2 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Single-pulse avalanche energy, EAS (see Figure 4) 75 mJ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Avalanche current, I

AS

(see Note 4) 1 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating virtual junction temperature range, TJ –40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. All voltage values are with respect to LGND and PGND.

2. Each power DMOS source is internally connected to PGND.

3. Pulse duration ≤ 100 µs, duty cycle ≤ 2 %

4. DRAIN supply voltage = 15 V, starting junction temperature (TJS) = 25°C, L = 100 mH, IAS = 1 A (see Figure 4).

DISSIPATION RATING TABLE

PACKAGE

TA ≤ 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

TA = 125°C

POWER RATING

DW 1125 mW 9.0 mW/°C 225 mW

N 1150 mW 9.2 mW/°C 230 mW