TPIC5403
4-CHANNEL INDEPENDENT GATE-PROTECTED
POWER DMOS ARRAY
SLIS038A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995
• Low r
DS(on)
• High Voltage Output...60 V
•Extended ESD Capability...4000 V
• Pulsed Current...11.25 A Per Channel
• Fast Commutation Speed
description
The TPIC5403 is a monolithic gate-protected
power DMOS array that consists of four
independent electrically isolated N-channel
enhancement-mode DMOS transistors. Each
transistor features integrated high-current zener
diodes (Z
in the event that an overstress condition occurs.
. . . 0.23 Ω Typ
and Z
CXa
) to prevent gate damage
CXb
DRAIN1
DRAIN1
GATE1
GND
SOURCE1
SOURCE1
SOURCE2
SOURCE2
GND
GATE2
DRAIN2
DRAIN2
DW PACKAGE
(TOP VIEW)
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
DRAIN3
DRAIN3
GATE3
GND
SOURCE3
SOURCE3
SOURCE4
SOURCE4
GND
GATE4
DRAIN4
DRAIN4
These zener diodes also provide up to 4000 V of
ESD protection when tested using the
human-body model of a 100-pF capacitor in series
with a 1.5-kΩ resistor.
The TPIC5403 is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for operation
over the case temperature range of –40°C to 125°C.
schematic
GATE1
GATE2
1, 2
3
5, 6
11, 12
10
7, 8
Z
Z
C1b
C1a
Q2
Z
Z
C2b
C2a
Q1
D1
D3
Z1
D2 D4
Z2 Z4
4, 9, 16, 21
GND
Z3
DRAIN1
SOURCE1
DRAIN2
SOURCE2
NOTE A: For correct operation, no terminal may be taken below GND.
Q3
Z
Z
Z
C3b
Z
C3a
C4b
C4a
Q4
23, 24
22
19, 20
13, 14
15
17, 18
DRAIN3
GATE3
SOURCE3
DRAIN4
GATE4
SOURCE4
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1995, Texas Instruments Incorporated
1
TPIC5403
4-CHANNEL INDEPENDENT GATE-PROTECTED
POWER DMOS ARRAY
SLIS038A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995
absolute maximum ratings over operating case temperature range (unless otherwise noted)
Drain-to-source voltage, V
60 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS
†
Source-to-GND voltage 100 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Drain-to-GND voltage 100 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gate-to-source voltage range, V
Continuous drain current, each output, T
Continuous source-to-drain diode current, T
Pulsed drain current, each output, I
Continuous gate-to-source zener diode current, T
Pulsed gate-to-source zener diode current, T
Single-pulse avalanche energy, E
Continuous total power dissipation, T
Operating virtual junction temperature range, T
Operating case temperature range, T
Storage temperature range, T
–9 V to 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GS
max
AS
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
= 25°C 2.25 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C
= 25°C 2.25 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C
, TC = 25°C (see Note 1 and Figure 15) 11.25 A. . . . . . . . . . . . . . . . .
= 25°C ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C
= 25°C ±500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C
, TC = 25°C (see Figures 4, 15, and 16) 17.2 mJ. . . . . . . . . . . . . . . . . . .
= 25°C (see Figure 15) 1.39 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C
–40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C
–40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
J
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Pulse duration = 10 ms, duty cycle = 2%
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4-CHANNEL INDEPENDENT GATE-PROTECTED
I
Zero-gate-voltage drain current
DS
,
A
I
Leakage current, drain-to-GND
V
V
A
r
Static drain-to-source on-state resistance
D
,
Ω
F
trrReverse-recovery time
ns
V
See
di/dt
100 A/
QRRTotal diode charge
See Figures 1 and 14
C
SLIS038A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995
electrical characteristics, TC = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
(BR)DSX
V
GS(th)
V
(BR)GS
V
(BR)SG
V
(BR)
V
DS(on)
V
F(SD)
V
F
DSS
I
GSSF
I
GSSR
lkg
DS(on)
g
fs
C
iss
C
oss
C
rss
NOTES: 2. Technique should limit TJ – TC to 10°C maximum.
Drain-to-source breakdown voltage ID = 250 µA, VGS = 0 60 V
Gate-to-source threshold voltage
Gate-to-source breakdown voltage IGS = 250 µA 18 V
Source-to-gate breakdown voltage ISG = 250 µA 9 V
Reverse drain-to-GND breakdown voltage (across
D1, D2, D3, and D4)
Drain-to-source on-state voltage
Forward on-state voltage, source-to-drain
Forward on-state voltage, GND-to-drain
Forward gate current, drain short circuited to source VGS = 15 V, VDS = 0 20 200 nA
Reverse gate current, drain short circuited to
source
Forward transconductance
Short-circuit input capacitance, common source 200 250
Short-circuit output capacitance, common source
Short-circuit reverse-transfer capacitance,
common source
3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
ID = 1 mA,
See Figure 5
Drain-to-GND current = 250 µA 100 V
ID = 2.25 A,
See Notes 2 and 3
IS = 2.25 A,
VGS = 0 (Z1, Z2, Z3, Z4),
See Notes 2 and 3 and Figure 12
ID = 2.25 A (D1, D2, D3, D4),
See Notes 2 and 3
V
= 48 V,
VGS = 0
VSG = 5 V, VDS = 0 10 100 nA
= 48
DGND
VGS = 10 V,
I
= 2.25 A,
See Notes 2 and 3
and Figures 6 and 7
VDS = 15 V, ID = 1.125 A,
See Notes 2 and 3 and Figure 9
VDS = 25 V, VGS = 0,
f = 1 MHz, See Figure 11
TPIC5403
POWER DMOS ARRAY
VDS = VGS,
VGS = 10 V,
TC = 25°C 0.05 1
TC = 125°C 0.5 10
TC = 25°C 0.05 1
TC = 125°C 0.5 10
TC = 25°C 0.23 0.27
TC = 125°C 0.35 0.4
1.5 1.75 2.2 V
0.5 0.62 V
0.9 1.1 V
2.5 V
1.6 2.1 S
100 175
60 75
µ
µ
p
source-to-drain and GND-to-drain diode characteristics, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IS = 1.125 A,
= 0,
GS
Figures 1 and 14
Z1, Z2, Z3, and Z4 80
VDS = 48 V,
=
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
µs,
D1, D2, D3, and D4 160
Z1, Z2, Z3, and Z4
D1, D2, D3, and D4 0.5
0.12
µ
3
TPIC5403
DD
,
L
,
r1
,
ns
See Figure 3
nH
4-CHANNEL INDEPENDENT GATE-PROTECTED
POWER DMOS ARRAY
SLIS038A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995
resistive-load switching characteristics, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
d(on)
t
d(off)
t
r2
t
f2
Q
Q
Q
L
D
L
S
R
g
thermal resistance
R
θJA
R
θJB
R
θJP
NOTES: 4. Package mounted on an FR4 printed-circuit board with no heatsink
Turn-on delay time 32 55
Turn-off delay time
Rise time
Fall time 7 15
Total gate charge
g
Threshold gate-to-source charge
gs(th)
Gate-to-drain charge
gd
Internal drain inductance 5
Internal source inductance 5
Internal gate resistance 0.25 Ω
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Junction-to-ambient thermal resistance See Notes 4 and 7 90 °C/W
Junction-to-board thermal resistance See Notes 5 and 7 49 °C/W
Junction-to-pin thermal resistance See Notes 6 and 7 28 °C/W
5. Package mounted on a 24 inch2, 4-layer FR4 printed-circuit board
6. Package mounted in intimate contact with infinite heatsink
7. All outputs with equal power
V
= 25 V, R
tf1 = 10 ns,
VDS = 48 V,
= 20 Ω,t
See Figure 2
ID = 1.125 A, VGS = 10 V,
= 10 ns,
27 50
14 30
6.6 8
0.6 0.7
2.8 3.2
nC
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4-CHANNEL INDEPENDENT GATE-PROTECTED
SLIS038A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
1.5
TPIC5403
POWER DMOS ARRAY
0.75
0
– 0.75
– 1.5
– 2.25
– 3
– Source-to-Drain Diode Current – AI
S
– 3.75
– 4.25
†
IRM = maximum recovery current
‡
The above waveform is representative of D1, D2, D3, and D4 in shape only.
Shaded Area = QRR
†
I
RM
t
rr(SD)
0 50 100 150 200 250 300
Reverse di/dt = 100 A/µs
Time – ns
25% of I
VDS = 48 V
VGS = 0
TJ = 25°C
Z1 – Z4
350 400 450 500
†
RM
‡
Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode
VDD = 25 V
Pulse Generator
R
gen
NOTE A: CL includes probe and jig capacitance.
50 Ω
V
GS
50 Ω
TEST CIRCUIT
Figure 2. Resistive-Switching Test Circuit and Voltage Waveforms
t
r1
R
L
V
DS
DUT
CL 30 pF
(see Note A)
V
GS
t
d(on)
V
DS
t
f2
VOLTAGE WAVEFORMS
t
f1
10 V
0 V
t
d(off)
t
r2
V
V
DD
DS(on)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
TPIC5403
4-CHANNEL INDEPENDENT GATE-PROTECTED
POWER DMOS ARRAY
SLIS038A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
Current
Regulator
12-V
Battery
0
0.2 µF
50 kΩ
IG = 100 µA
V
0.3 µF
DS
Same Type
as DUT
V
DD
DUT
10 V
V
GS
Q
gs(th)
Q
g
Q
gd
Gate Voltage
Time
VOLTAGE WAVEFORM
IG Current-
Sampling Resistor
TEST CIRCUIT
ID Current-
Sampling Resistor
Figure 3. Gate-Charge Test Circuit and Voltage Waveform
VDD = 25 V
t
159 µH
V
V
Pulse Generator
(see Note A)
50 Ω
R
gen
TEST CIRCUIT
NOTES: A. The pulse generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω.
B. Input pulse duration (tw) is increased until peak current IAS = 11.25 A.
Energy test level is defined as EAS+
V
GS
50 Ω
I
D
DS
DUT
IAS
GS
I
D
V
DS
V
(BR)DSX
2
w
VOLTAGE AND CURRENT WAVEFORMS
t
av
+
17.2 mJ.
t
av
15 V
0 V
I
AS
(see Note B)
0 V
V
(BR)DSX
0 V
= 60 V Min
Figure 4. Single-Pulse Avalanche-Energy Test Circuit and Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4-CHANNEL INDEPENDENT GATE-PROTECTED
SLIS038A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995
TYPICAL CHARACTERISTICS
TPIC5403
POWER DMOS ARRAY
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
2.5
VDS = V
2
1.5
1
0.5
– Gate-to-Source Threshold Voltage – V
GS(th)
V
0
–40 –20 0 20 40 60 80 100 120 140 160
GS
ID = 1 mA
ID = 100 µA
TJ – Junction Temperature – °C
Figure 5 Figure 6
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
0.6
ID = 2.25 A
Ω
0.4
VGS = 10 V
– Static Drain-to-Source
0.2
On-State Resistance –
DS(on)
r
0
–40 –20 0 20 40 60 80 100 120 140 160
TJ – Junction Temperature – °C
VGS = 15 V
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
0.5
TJ = 25°C
0.4
Ω
0.3
VGS = 10 V
0.2
– Static Drain-to-Source
On-State Resistance –
DS(on)
r
0.1
0.1 1 10 100
VGS = 15 V
ID – Drain Current – A
Figure 7 Figure 8
DRAIN CURRENT
DRAIN-TO-SOURCE VOLTAGE
10
VGS = 15 V VGS = 10 V
9
8
7
6
5
4
– Drain Current – A
D
3
I
2
1
0
0123456
VDS – Drain-to-Source Voltage – V
vs
∆VGS = 0.4 V
TJ = 25°C
(unless otherwise
noted)
VGS = 4 V
VGS = 6 V
PRODUCT PREVIEW
78910
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
TPIC5403
4-CHANNEL INDEPENDENT GATE-PROTECTED
POWER DMOS ARRAY
SLIS038A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995
TYPICAL CHARACTERISTICS
DISTRIBUTION OF
FORWARD TRANSCONDUCTANCE
50
Total Number of Units = 688
VDS = 15 V
45
ID = 1.125 A
40
TJ = 25°C
35
10
9
8
7
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
TJ = 40°C
TJ = 25°C
TJ = 75°C
TJ = 125°C
TJ = 150°C
30
25
20
15
Percentage of Units – %
10
5
0
1.97522.025
gfs – Forward Transconductance – S
DRAIN-TO-SOURCE VOLTAGE
400
VGS = 0
f = 1MHz
360
TJ = 25°C
C
320
280
240
200
@ 0 V = 301 pF
iss
C
@ 0 V = 384 pF
oss
C
@ 10 V = 144 pF
rss
C
iss
6
5
4
– Drain Current – A
D
3
I
2
1
0
0123456
VGS – Gate-to-Source Voltage – V
2.050
2.075
2.1
2.125
2.150
2.175
2.2
2.225
Figure 9 Figure 10
CAPACITANCE
vs
SOURCE-TO-DRAIN DIODE CURRENT
vs
SOURCE-TO-DRAIN VOLTAGE
10
VGS = 0
TJ = 125°C
1
78910
TJ = 40°C
TJ = 25°C
160
120
C – Capacitance – pF
80
40
0
0 4 8 12162024
8
C
oss
C
rss
28 32 36 40
VDS – Drain-to-Source Voltage – V
– Source-to-Drain Diode Current – A
SD
I
TJ = 150°C
0.1
0.1 1
VSD – Source-to-Drain Voltage – V
Figure 11 Figure 12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TJ = 75°C
10
60
ID = 1.125 A
TJ = 25°C
See Figure 3
50
TPIC5403
4-CHANNEL INDEPENDENT GATE-PROTECTED
POWER DMOS ARRAY
SLIS038A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995
TYPICAL CHARACTERISTICS
DRAIN-TO-SOURCE VOLTAGE AND
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
12
10
VDD = 20 V
40
30
20
– Drain-to-Source Voltage – V
DS
V
10
0
012
175
150
125
100
VDD = 30 V
VDD = 48 V
VDD = 20 V
34 6
Qg – Gate Charge – nC
Figure 13
REVERSE-RECOVERY TIME
vs
REVERSE di/dt
VDS = 48 V
VGS = 0
IS = 1.125 A
TJ = 25°C
See Figure 1
D1, D2, D3, and D4
8
6
4
2
0
75
– Gate-to-Source Voltage – V
GS
V
75
50
– Reverse-Recovery Time – ns
rr
t
25
Z1, Z2, Z3, and Z4
0
0 100 200 300
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
400 500 600
Reverse di/dt – A/µs
Figure 14
9
TPIC5403
4-CHANNEL INDEPENDENT GATE-PROTECTED
POWER DMOS ARRAY
SLIS038A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995
THERMAL INFORMATION
MAXIMUM DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
100
TC = 25°C
10
10 ms
1
– Maximum Drain Current – A
D
I
R
θJA
§
†
1 ms
1 µs
†
500 µs
†
†
‡
R
θJP
DC Conditions
0.1
0.1 1 10 100
VDS – Drain-to-Source Voltage – V
†
Less than 2% duty cycle
‡
Device mounted in intimate contact with infinite heatsink.
§
Device mounted on FR4 printed circuit board with no heatsink.
Figure 15
MAXIMUM PEAK AVALANCHE CURRENT
vs
TIME DURATION OF AVALANCHE
100
See Figure 4
10
TC = 25°C
TC = 125°C
10
– Maximum Peak Avalanche Current – A
AS
I
1
0.01 0.1
1.0 10
tav – Time Duration of Avalanche – ms
Figure 16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
100
4-CHANNEL INDEPENDENT GATE-PROTECTED
SLIS038A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995
THERMAL INFORMATION
TPIC5403
POWER DMOS ARRAY
JUNCTION-TO-BOARD THERMAL RESISTANCE
100
DC Conditions
C/W
°
– Junction-to-Board Thermal Resistance –
JBθ
R
d = 0.5
d = 0.2
10
d = 0.1
d = 0.05
d = 0.02
1
d = 0.01
DW PACKAGE
†
vs
PULSE DURATION
Single Pulse
0.1
0.0001 0.001
†
Device mounted on 24in2, 4-layer FR4 printed-circuit board with no heatsink.
NOTE A: Z
(t) = r(t) R
θJB
tw = pulse duration
tc = cycle time
d = duty cycle = tw/t
θJB
c
0.01
tw – Pulse Duration – s
0.1 1 100
Figure 17
t
c
t
w
10
I
D
0
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright 1998, Texas Instruments Incorporated
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