TEXAS INSTRUMENTS TPIC5401 Technical data

H-BRIDGE GATE-PROTECTED

POWER DMOS ARRAY

SLIS024A – DECEMBER 1993 – REVISED MARCH 1994

D

Low r

DS(on)

D

High Voltage Output...60 V

D

Extended ESD Capability...4000 V

description

The TPIC5401 is a monolithic gate-protected power DMOS array that consists of four N-channel
enhancement-mode DMOS transistors, two of which are configured with a common source. Each transistor
features integrated high-current zener diodes (Z
overstress condition occurs. These zener diodes also provide up to 4000 V of ESD protection when tested using
the human-body model of a 100-pF capacitor in series with a 1.5-kΩ resistor.

The TPIC5401 is offered in a 16-pin thermally enhanced dual-in-line (NE) package and a 20-pin wide-body
surface-mount (DW) package and is characterized for operation over the case temperature range of –40°C to
125°C.

. . . 0.3 Ω Typ

NE PACKAGE

(TOP VIEW)

CXa

D
D

and Z

Pulsed Current...10 A Per Channel
Fast Commutation Speed

) to prevent gate damage in the event that an

CXb

DW PACKAGE

(TOP VIEW)

TPIC5401

SOURCE2/GND

SOURCE4/GND

schematic

DRAIN2

GATE2

GND
GND

GATE4

DRAIN4

DRAIN1

GATE1

SOURCE1

DRAIN2

Z
Z

C1b
C1a

16
15
14
13
12
11
10

9

Q1

Q2

SOURCE1
DRAIN1
GATE1
GND
GND
GATE3
DRAIN3
SOURCE3

D1

D2Z1 Z3

SOURCE4/GND

NC – No internal connection

1
2
3
4
5
6
7
8

GND

GATE4

NC

DRAIN4

SOURCE3

DRAIN3

GATE3

NC
NC

1
2
3
4
5
6
7
8
9
10

SOURCE2/GND

20

GATE2

19

NC

18

NC

17

DRAIN2

16

SOURCE1

15
14

DRAIN1

13

GATE1

12

NC

11

NC

Q3

Z

C3b

Z

C3a

Q4

DRAIN3

GATE3

SOURCE3
DRAIN4

GATE2

Z

C2b

Z

C2a

NOTE: For correct operation, no terminal pin may be taken below GND.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Z2 Z4

GND, SOURCE2, SOURCE4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

GATE4

Z

C4b

Z

C4a

Copyright  1994, Texas Instruments Incorporated

1

TPIC5401
H-BRIDGE GATE-PROTECTED
POWER DMOS ARRAY

SLIS024A – DECEMBER 1993 – REVISED MARCH 1994

absolute maximum ratings over operating case temperature range (unless otherwise noted)

Drain-to-source voltage, V

60 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DS

†

Source-to-GND voltage (Q1, Q3) 100 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Drain-to-GND voltage (Q1, Q3) 100 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Drain-to-GND voltage (Q2, Q4) 60 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Gate-to-source voltage range, V
Continuous drain current, each output, T

–9 V to 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GS

= 25°C: DW package 1.7 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C

NE package 2 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous source-to-drain diode current, T
Pulsed drain current, each output, I

max

Continuous gate-to-source zener-diode current, T
Pulsed gate-to-source zener-diode current, T
Single-pulse avalanche energy, E

, TC = 25°C (see Figures 4, 15, and 16) 21 mJ. . . . . . . . . . . . . . . . . . . . . .

AS

= 25°C 2 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C

, TC = 25°C (see Note 1 and Figure 15) 10 A. . . . . . . . . . . . . . . . . . . .

= 25°C ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C

= 25°C ±500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C

Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating virtual junction temperature range, T
Operating case temperature range, T

–40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C

–40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

J

Storage temperature range, –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: Pulse duration = 10 ms, duty cycle = 2%

DISSIPATION RATING TABLE

PACKAGE

DW

NE

TC ≤ 25°C

POWER RATING

1389 mW
2075 mW

DERATING FACTOR

ABOVE TC = 25°C

11.1 mW/°C

16.6 mW/°C

TC = 125°C

POWER RATING

279 mW
415 mW

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I

Zero-gate-voltage drain current

DS

,

A

I

Leakage current, drain-to-GND

V

V

A

r

Static drain-to-source on-state resistance

D

,

Ω

F

V

GS

g

di/dt

100 A/µs

See Figures 1 and 14

electrical characteristics, TC = 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

(BR)DSX

V

GS(th)

V

(BR)GS

V

(BR)SG

V

(BR)

V

DS(on)

V

F(SD)

V

F

DSS

I

GSSF

I

GSSR

lkg

DS(on)

g

fs

C

iss

C

oss

C

rss

NOTES: 2. Technique should limit TJ – TC to 10°C maximum.

Drain-to-source breakdown voltage ID = 250 µA, VGS = 0 60 V
Gate-to-source threshold voltage
Gate-to-source breakdown voltage IGS = 250 µA 18 V

Source-to-gate breakdown voltage ISG = 250 µA 9 V
Reverse drain-to-GND breakdown voltage

(across D1, D2)
Drain-to-source on-state voltage

Forward on-state voltage, source-to-drain

Forward on-state voltage, GND-to-drain

Forward-gate current, drain short circuited to source VGS = 15 V, VDS = 0 20 200 nA
Reverse-gate current, drain short circuited to source VSG = 5 V, VDS = 0 10 100 nA

Forward transconductance
Short-circuit input capacitance, common source 220 275

Short-circuit output capacitance, common source
Short-circuit reverse-transfer capacitance,

common source

3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.

ID = 1 mA,
See Figure 5

Drain-to-GND current = 250 µA 100 V
ID = 2 A,

See Notes 2 and 3
IS = 2 A,

VGS = 0 (Z1, Z2, Z3, Z4),
See Notes 2 and 3 and Figure 12

ID = 2 A (D1, D2),
See Notes 2 and 3

V

= 48 V,

VGS = 0

= 48

DGND

VGS = 10 V,
I

= 2 A,
See Notes 2 and 3
and Figures 6 and 7

VDS = 15 V, ID = 1 A,
See Notes 2 and 3 and Figure 9

VDS = 25 V, VGS = 0,
f = 1 MHz, See Figure 11

TPIC5401

H-BRIDGE GATE-PROTECTED

POWER DMOS ARRAY

SLIS024A – DECEMBER 1993 – REVISED MARCH 1994

VDS = V

VGS = 10 V,

TC = 25°C 0.05 1
TC = 125°C 0.5 10

TC = 25°C 0.05 1
TC = 125°C 0.5 10

TC = 25°C 0.3 0.35

TC = 125°C 0.47 0.5

GS,

1.5 1.85 2.2 V

0.6 0.7 V

1 1.2 V

7.5 V

1.6 1.9 S

120 150
100 125

µ

µ

p

source-to-drain and GND-to-drain diode characteristics, TC = 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

rr

Q

Reverse-recovery time

Total diode charge

RR

IS = 1 A,

= 0,

See Fi

ures 1 and 14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

VDS = 48 V,

=

Z1 and Z3 120
Z2 and Z4 280
D1 and D2 260

,

Z1 and Z3
Z2 and Z4 0.9
D1 and D2 2.2

ns

0.12
µC

3

TPIC5401

DD

,

L

,

en

,

ns

See Figure 3

nH

R

Junction-to-ambient thermal resistance (see Note 4)

R

Junction-to-pin thermal resistance

H-BRIDGE GATE-PROTECTED
POWER DMOS ARRAY

SLIS024A – DECEMBER 1993 – REVISED MARCH 1994

resistive-load switching characteristics, TC = 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

d(on)

t

d(off)

t

r

t

f

Q
Q
Q
L

d

L

s

R

thermal resistances

R

NOTE 4: Package mounted on an FR4 printed-circuit board with no heatsink.

Turn-on delay time 32 65
Turn-off delay time
Rise time
Fall time 25 50
Total gate charge

g

Threshold gate-to-source charge

gs(th)

Gate-to-drain charge

gd

Internal drain inductance 5
Internal source inductance 5
Internal gate resistance 0.25 Ω

g

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

θJA

Junction-to-board thermal resistance DW

θJB

θJP

p

V

= 25 V, R

t

= 10 ns,

dis

VDS = 48 V,

DW 90
NE 60

DW 30
NE 25

= 25 Ω,t

See Figure 2

ID = 1 A, VGS = 10 V,

All outputs with equal power

= 10 ns,

40 80
15 30

6.6 8

0.8 1

2.6 3.2

53

nC

°C/W

PARAMETER MEASUREMENT INFORMATION

2

1

0

– 1

– 2

– Source-to-Drain Diode Current – AI

S

– 3

– 4

0 200 400 600 800 1000 1200

†

IRM = maximum recovery current

‡

The above waveform is representative of Z2, Z4, D1, and D2 in shape only.

I

RM

†

t

rr(SD)

Reverse di/dt = 100 A/µs

25% of I

Shaded Area = Q

Time – ns

Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode

VDS = 48 V
VGS = 0
TJ = 25°C
Z1 and Z3

†

RM

RR

‡

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265