TEXAS INSTRUMENTS TPIC5323L Technical data

TPIC5323L

3-CHANNEL INDEPENDENT GATE-PROTECTED LOGIC-LEVEL

POWER DMOS ARRAY

SLIS044A – NOVEMBER 1994 – REVISED SEPTEMBER 1995

GND

D PACKAGE

(TOP VIEW)

1

16

2

15

3

14

4

13

5

12

6

11

7

10

8

9

GATE1
SOURCE1
SOURCE1
DRAIN1
DRAIN1
SOURCE3
SOURCE3
GATE3

D

Low r

DS(on)

D

Voltage Output...60 V

D

Input Protection Circuitry...18 V

D

Pulsed Current...3 A Per Channel

D

Extended ESD Capability...4000 V

D

Direct Logic-Level Interface

. . . 0.6 Ω Typ

description

The TPIC5323L is a monolithic gate-protected
logic-level power DMOS array that consists of

DRAIN2

DRAIN2
SOURCE2
SOURCE2

GATE2
DRAIN3
DRAIN3

three electrically isolated independent N-channel
enhancement-mode DMOS transistors. Each transistor features integrated high-current zener diodes (Z
and Z

) to prevent gate damage in the event that an overstress condition occurs. These zener diodes also

CXb

provide up to 4000 V of ESD protection when tested using the human-body model of a 100-pF capacitor in series
with a 1.5-kΩ resistor.

The TPIC5323L is offered in a standard 16-pin small-outline surface-mount (D) package and is characterized
for operation over the case temperature of –40°C to 125°C.

schematic

DRAIN1

DRAIN2 DRAIN3GATE2 GATE3

95

6, 71, 212, 13

CXa

Q1 Q2 Q3

Z

Z

16

C1b

C1a

14, 15

SOURCE1

GATE1

NOTE A: For correct operation, no terminal can be taken below GND.

D1

Z1 Z2

Z

C2b

Z

C2a

8 3, 4 10, 11

GND

SOURCE2

D2

Z

Z

D3

Z3

C3b

C3a

SOURCE3

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1995, Texas Instruments Incorporated

1

TPIC5323L
3-CHANNEL INDEPENDENT GATE-PROTECTED

SLIS044A – NOVEMBER 1994 – REVISED SEPTEMBER 1995

absolute maximum ratings over operating case temperature range (unless otherwise noted)

Drain-to-source voltage, V

60 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DS

†

Source-to-GND voltage 100 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Drain-to-GND voltage 100 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Gate-to-source voltage range, V
Continuous drain current, each output, T
Continuous source-to-drain diode current, T
Pulsed drain current, each output, I
Continuous gate-to-source zener diode current, T
Pulsed gate-to-source zener diode current, T
Single-pulse avalanche energy, E
Continuous total power dissipation, T
Operating virtual junction temperature range, T
Operating case temperature range, T
Storage temperature range, T

–9 V to 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GS

max

AS

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

= 25°C 1 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C

= 25°C 1 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C

, TC = 25°C (see Note 1 and Figure 15) 3 A. . . . . . . . . . . . . . . . . . . . .

= 25°C ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C

= 25°C ±500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C

, TC = 25°C (see Figures 4 and 16) 22.5 mJ. . . . . . . . . . . . . . . . . . . . . . .

= 25°C (see Figure 15) 1.09 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C

–40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C

–40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

J

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: Pulse duration = 10 ms, duty cycle = 2%

2

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I

Zero-gate-voltage drain current

DS

,

A

I

Leakage current, drain-to-GND

V

V

Α

r

Static drain-to-source on-state resistance

D

,

Ω

F

trrReverse-recovery time

ns

V

GS

g

di/dt

100 A/µs

QRRTotal diode charge

See Figures 1 and 14

C

3-CHANNEL INDEPENDENT GATE-PROTECTED

SLIS044A – NOVEMBER 1994 – REVISED SEPTEMBER 1995

electrical characteristics, TC = 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

(BR)DSX

V

GS(th)

V

(BR)GS

V

(BR)SG

V

(BR)

V

DS(on)

V

F(SD)

V

F

DSS

I

GSSF

I

GSSR

lkg

DS(on)

g

fs

C

iss

C

oss

C

rss

NOTES: 2. Technique should limit TJ – TC to 10°C maximum.

Drain-to-source breakdown voltage ID = 250 µA, VGS = 0 60 V
Gate-to-source threshold voltage
Gate-to-source breakdown voltage IGS = 250 µA 18 V

Source-to-gate breakdown voltage ISG = 250 µA 9 V
Reverse drain-to-GND breakdown voltage (across

D1, D2, D3)
Drain-to-source on-state voltage

Forward on-state voltage, source-to-drain

Forward on-state voltage, GND-to-drain

Forward-gate current, drain short circuited to source VGS = 15 V, VDS = 0 20 200 nA
Reverse-gate current, drain short circuited to source VSG = 5 V, VDS = 0 10 100 nA

Forward transconductance
Short-circuit input capacitance, common source 107 137

Short-circuit output capacitance, common source
Short-circuit reverse transfer capacitance,

common source

3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.

ID = 1 mA,
See Figure 5

Drain-to-GND current = 250 µA 100 V
ID = 1 A,

See Notes 2 and 3
IS = 1 A,

VGS = 0 (Z1, Z2, Z3),
See Notes 2 and 3 and Figure 12

ID = 1 A (D1, D2, D3),
See Notes 2 and 3

V

= 48 V,

VGS = 0

= 48

DGND

VGS = 5 V,
I

= 1 A,
See Notes 2 and 3
and Figures 6 and 7

VDS = 15 V, ID = 500 mA,
See Notes 2 and 3 and Figure 9

VDS = 25 V, VGS = 0,
f = 1 MHz, See Figure 11

TPIC5323L

VDS = VGS,

VGS = 5 V,

TC = 25°C 0.05 1
TC = 125°C 0.5 10

TC = 25°C 0.05 1
TC = 125°C 0.5 10

TC = 25°C 0.6 0.65

TC = 125°C 0.85 0.9

1.5 1.8 2.2 V

0.6 0.7 V

0.9 1.1 V

4 V

0.89 1.06 S

71 89
22 28

µ

µ

p

source-to-drain and GND-to-drain diode characteristics, TC = 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

IS = 500 mA,

= 0,

See Fi

ures 1 and 14

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VDS = 48 V,

=

Z1, Z2, and Z3 75
D1, D2, and D3 190

,

Z1, Z2, and Z3
D1, D2, and D3 0.85

0.08

µ

3

TPIC5323L

DD

,

L

,

r1

,

ns

See Figure 3

nH

3-CHANNEL INDEPENDENT GATE-PROTECTED

SLIS044A – NOVEMBER 1994 – REVISED SEPTEMBER 1995

resistive-load switching characteristics, TC = 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

d(on)

t

d(off)

t

r2

t

f2

Q
Q
Q
L

D

L

S

R

thermal resistance

R
R
R

NOTES: 4. Package mounted on an FR4 printed-circuit board with no heatsink.

Turn-on delay time 34 50
Turn-off delay time
Rise time
Fall time 15 25
Total gate charge

g

Threshold gate-to-source charge

gs(th)

Gate-to-drain charge

gd

Internal drain inductance 5
Internal source inductance 5
Internal gate resistance 0.25 Ω

g

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Junction-to-ambient thermal resistance See Notes 4 and 7 115

θJA

Junction-to-board thermal resistance See Notes 5 and 7 64

θJB

Junction-to-pin thermal resistance See Notes 6 and 7 33

θJP

5. Package mounted on a 24 in2, 4-layer FR4 printed-circuit board.

6. Package mounted in intimate contact with infinite heatsink.

7. All outputs with equal power

V

= 25 V, R

tf1 = 10 ns,

VDS = 48 V,

See Figure 2

ID = 500 mA, VGS = 5 V,

= 50 Ω,t

= 10 ns,

50 70
20 30

2 2.45

0.3 0.95

1.2 1.48

nC

°C/W

PARAMETER MEASUREMENT INFORMATION

1

0.5

0

– 0.5

– 1

– 1.5

– 2

– Source-to-Drain Diode Current – A

S

I

– 2.5

– 3

0 50 100 150 200 250 300 350 400 450 500

†

IRM = maximum recovery current

‡

The above waveform is representative of D1, D2, and D3 in shape only.

I

RM

†

Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode

Reverse di/dt = 100 A/µs

Shaded Area = Q

t

rr(SD)

Time – ns

25% of I

RM

TJ = 25°C
Z1, Z2, and Z3

†

RR

‡

4

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PARAMETER MEASUREMENT INFORMATION

Pulse Generator

R

gen

NOTE A: CL includes probe and jig capacitance.

50 Ω

V

GS

50 Ω

TEST CIRCUIT

Figure 2. Resistive-Switching Test Circuit and Voltage Waveforms

VDD = 25 V

R

L

DUT

TPIC5323L

3-CHANNEL INDEPENDENT GATE-PROTECTED

SLIS044A – NOVEMBER 1994 – REVISED SEPTEMBER 1995

t

f1

V

DS

CL = 30 pF
(see Note A)

t

d(on)

t

r1

V

GS

t

f2

V

DS

VOLTAGE WAVEFORMS

5 V

0 V

t

d(off)

t

r2

V

DD

V

DS(on)

12-V

Battery

0.2 µF

0 V

Current

Regulator

Same Type

50 kΩ

IG = 100 µA

IG Current-

Sampling Resistor

TEST CIRCUIT

0.3 µF

V

DS

as DUT

V

DD

DUT

ID Current-

Sampling Resistor

5 V

V

Figure 3. Gate-Charge Test Circuit and Waveform

GS

Q

gs(th)

Q

g

Q

gd

Gate Voltage

Time

VOLTAGE WAVEFORM

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5

TPIC5323L
3-CHANNEL INDEPENDENT GATE-PROTECTED

SLIS044A – NOVEMBER 1994 – REVISED SEPTEMBER 1995

PARAMETER MEASUREMENT INFORMATION

VDD = 25 V

t

2.92 mH
V

V

Pulse Generator

(see Note A)

50 Ω

R

gen

TEST CIRCUIT

†

Non-JEDEC symbol for avalanche time

NOTES: A. The pulse generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω.

B. Input pulse duration (tw) is increased until peak current IAS = 3 A.

Energy test level is defined as EAS+

V

50 Ω

GS

I

D

DS

DUT

IAS

GS

V

DS

V

(BR)DSX

2

I

D

Figure 4. Single-Pulse Avalanche-Energy Test Circuit and Waveforms

w

VOLTAGE AND CURRENT WAVEFORMS

t

av

+

22.5 mJ, where tav+

†

t

av

5 V

0 V

I

AS

(see Note B)

0 V

V

(BR)DSX

0 V

avalanche time.

= 60 V Min

GATE-TO-SOURCE THRESHOLD VOLTAGE

vs

JUNCTION TEMPERATURE

2.5

2

1.5

1

– Gate-to-Source Threshold Voltage – V

0.5

GS(th)

V

0
–40 –20

VDS = V

GS

ID = 1 mA

ID = 100 µA

0 20406080
TJ – Junction Temperature – °C

TYPICAL CHARACTERISTICS

STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE

1.2

1

ΩOn-State Resistance –

0.8

0.6

– Static Drain-to-Source

0.4

DS(on)

r

0.2

0

100 120 140 160

–40 –20

vs

JUNCTION TEMPERATURE

ID = 1 A

VGS = 4.5 V

VGS = 5 V

0 20406080

TJ – Junction Temperature – °C

100 120 140 160

Figure 5

6

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Figure 6

TPIC5323L

3-CHANNEL INDEPENDENT GATE-PROTECTED

SLIS044A – NOVEMBER 1994 – REVISED SEPTEMBER 1995

TYPICAL CHARACTERISTICS

STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE

vs

DRAIN CURRENT

10

TJ = 25°C

ΩOn-State Resistance –

1

– Static Drain-to-Source

DS(on)

r

0.1

0.1 1 10

VGS = 4.5 V

VGS = 5 V

ID – Drain Current – A

Figure 7 Figure 8

DISTRIBUTION OF

FORWARD TRANSCONDUCTANCE

50

Total Number of
Units = 2064

45

VDS = 15 V

40

ID = 0.5 A
TJ = 25°C

35

30

DRAIN CURRENT

vs

DRAIN-TO-SOURCE VOLTAGE

3

2.5

2

1.5

– Drain Current – A

1

D

I

0.5

0

0246810

VDS – Drain-to-Source Voltage – V

n

VGS = 0.4 V

TJ = 25°C

VGS = 4 V

V

GS

= 2.8 V

DRAIN CURRENT

vs

GATE-TO-SOURCE VOLTAGE

3

T

= –40°C

J

TJ = 25°C

TJ = 75°C

2

TJ = 125°C

TJ = 150°C

25

20
15

Percentage of Units – %

10

5
0

0.90

0.92

0.94

0.96

gfs – Forward Transconductance – S

0.9811.02

Figure 9

1.04

– Drain Current – A

D

I

1.06

1.08

1.10

1.12

1.14

1.16

1.18

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1

0

146

0235 78

VGS – Gate-to-Source Voltage – V

Figure 10

7

TPIC5323L

Á

3-CHANNEL INDEPENDENT GATE-PROTECTED

SLIS044A – NOVEMBER 1994 – REVISED SEPTEMBER 1995

TYPICAL CHARACTERISTICS

DRAIN-TO-SOURCE VOLTAGE

250

VGS = 0

225

f = 1 MHz
TJ = 25°C

200

C

= 160 pF

iss(0)

C

= 216 pF

175
150
125
100

C – Capacitance – pF

oss(0)

C

= 78 pF

rss(0)

75

50
25

0

4 8 12 16 20 24

VDS – Drain-to-Source Voltage – V

DRAIN-TO-SOURCE VOLTAGE AND

GATE-TO-SOURCE VOLTAGE

60

ID = 500 mA
TJ = 25°C
See Figure 3

50

40

VDD = 30 V

CAPACITANCE

vs

C

iss

C

oss

C

rss

Figure 11

vs

GATE CHARGE

VDD = 20 V

28 32 36 40

12

10

8

SOURCE-TO-DRAIN DIODE CURRENT

vs

SOURCE-TO-DRAIN VOLTAGE

5

VGS = 0

4
3

2

1

TJ = 75°C

TJ = 125°C

– Source-to-Drain Diode Current – A

SD

I

TJ = 150°C

0.1

VSD – Source-to-Drain Voltage – V

TJ = 25°C

TJ = –40°C

110

Figure 12

REVERSE-RECOVERY TIME

vs

REVERSE di/dt

220
200
180
160
140

VDS = 48 V
VGS = 0
IS = 500 mA
TJ = 25°C
See Figure 1

30

20

– Drain-to-Source Voltage – V

DS

V

10

0

8

VDD = 48 V

VDD = 20 V

0.5 1 1.5 2 2.5 3
Qg – Gate Charge – nC

Figure 13 Figure 14

– Reverse-Recovery Time – ns

t

120
100

80
60

rr

40
20

0

6

4

– Gate-to-Source Voltage – V

GS

V

2

3.5 4

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0

D1, D2, and D3

Q1, Q2, and Q3

100 300 500

200 400

Reverse di/dt – A/µs

600

TPIC5323L

3-CHANNEL INDEPENDENT GATE-PROTECTED

SLIS044A – NOVEMBER 1994 – REVISED SEPTEMBER 1995

THERMAL INFORMATION

MAXIMUM DRAIN CURRENT

vs

DRAIN-TO-SOURCE VOLTAGE

10

TC = 25°C

1 µs

†

10 ms

†

1

– Maximum Drain Current – A

D

I

DC Conditions

0.1

†

Less than 2% duty cycle

‡

Device mounted in intimate contact with infinite heatsink.

§

Device mounted on FR4 printed-circuit board with no heatsink.

1

VDS – Drain-to-Source Voltage – V

1 ms

†

500 µs

§

θ

JA

10 100

‡

θ

JP

Figure 15

MAXIMUM PEAK AVALANCHE CURRENT

vs

TIME DURATION OF AVALANCHE

5

See Figure 4

4

†

3

TC = 25°C

TC = 125°C

2

– Maximum Peak Avalanche Current – A

AS

I

1

0.01 0.1 1
tav – Time Duration of Avalanche – ms

10

Figure 16

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9

TPIC5323L
3-CHANNEL INDEPENDENT GATE-PROTECTED

SLIS044A – NOVEMBER 1994 – REVISED SEPTEMBER 1995

THERMAL INFORMATION

C/W

°

100

10

1

DC Conditions

d = 0.5

d = 0.2

d = 0.1

d = 0.05

d = 0.02

d = 0.01

D PACKAGE

†

JUNCTION-TO-BOARD THERMAL RESISTANCE

vs

PULSE DURATION

– Junction-to-Board Thermal Resistance –

JBθ

R

0.1

0.0001 0.001

†

Device mounted on 24 in2, 4-layer FR4 printed-circuit board with no heatsink.

NOTE A: ZθB(t) = r(t) R

Single Pulse

tw+
tc+
d+duty cycle+twń

θJB

pulse duration

cycle time

0.01 0.1 1 10
tw – Pulse Duration – s

t

c

Figure 17

t

c

t

w

I

D
0

100

10

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T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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BE FULLY AT THE CUSTOMER’S RISK.

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safeguards must be provided by the customer to minimize inherent or procedural hazards.

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Copyright  1998, Texas Instruments Incorporated