TPIC5303
3-CHANNEL INDEPENDENT GATE-PROTECTED
POWER DMOS ARRAY
SLIS039A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995
• Low r
DS(on)
• High Voltage Output...60 V
•Extended ESD Capability...4000 V
• Pulsed Current...5 A Per Channel
• Fast Commutation Speed
description
The TPIC5303 is a monolithic gate-protected
power DMOS array that consists of three
independent electrically isolated N-channel
. . . 0.4 Ω Typ
DRAIN2
DRAIN2
SOURCE2
SOURCE2
GATE2
DRAIN3
DRAIN3
GND
D PACKAGE
(TOP VIEW)
1
16
2
15
3
14
4
13
5
12
6
11
7
10
8
9
GATE1
SOURCE1
SOURCE1
DRAIN1
DRAIN1
SOURCE3
SOURCE3
GATE3
enhancement-mode DMOS transistors. Each
transistor features integrated high-current zener
diodes (Z
CXa
and Z
) to prevent gate damage in the event that an overstress condition occurs. These zener
CXb
diodes also provide up to 4000 V of ESD protection when tested using the human-body model of a 100-pF
capacitor in series with a 1.5-kΩ resistor.
The TPIC5303 is offered in a standard 16-pin small-outline surface-mount (D) package and is characterized for
operation over the case temperature range of –40°C to 125°C.
schematic
DRAIN1
DRAIN2 DRAIN3GATE2 GATE3
95
6, 71, 212, 13
Q1 Q2 Q3
Z
Z
16
C1b
C1a
14, 15
SOURCE1
GATE1
NOTE A: For correct operation, no terminal pin may be taken below GND.
D1
Z1 Z2
Z
C2b
Z
C2a
8 3, 4 10, 11
GND
SOURCE2
D2
Z
Z
D3
Z3
C3b
C3a
SOURCE3
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1995, Texas Instruments Incorporated
1
TPIC5303
3-CHANNEL INDEPENDENT GATE-PROTECTED
POWER DMOS ARRAY
SLIS039A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995
absolute maximum ratings over operating case temperature range (unless otherwise noted)
Drain-to-source voltage, V
60 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DS
†
Source-to-GND voltage (Q1, Q2, and Q3) 100 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Drain-to-GND voltage (Q1, Q2, and Q3) 100 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gate-to-source voltage range, V
Continuous drain current, each output, T
Continuous source-to-drain diode current, T
Pulsed drain current, each output, I
Continuous gate-to-source zener-diode current, T
Pulsed gate-to-source zener-diode current, T
Single-pulse avalanche energy, E
Continuous total power dissipation, T
Operating virtual junction temperature range, T
Operating case temperature range, T
Storage temperature range, T
–9 V to 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
GS
max
AS
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
= 25°C 1.4 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C
= 25°C 1.4 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C
, TC = 25°C (see Note 1 and Figure 15) 5 A. . . . . . . . . . . . . . . . . . . . .
= 25°C ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C
= 25°C ±500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C
, TC = 25°C (see Figures 4, 15, and 16) 10.2 mJ. . . . . . . . . . . . . . . . . . .
= 25°C (see Figure 15) 1.08 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C
–40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C
–40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
J
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Pulse duration = 10 ms, duty cycle = 2%
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-CHANNEL INDEPENDENT GATE-PROTECTED
I
Zero-gate-voltage drain current
DS
,
A
I
Leakage current, drain-to-GND
V
V
A
r
Static drain-to-source on-state resistance
D
,
Ω
F
trrReverse-recovery time
ns
V
g
di/dt
100 A/
QRRTotal diode charge
See Figures 1 and 14
C
SLIS039A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995
electrical characteristics, TC = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
(BR)DSX
V
GS(th)
V
(BR)GS
V
(BR)SG
V
(BR)
V
DS(on)
V
F(SD)
V
F
DSS
I
GSSF
I
GSSR
lkg
DS(on)
g
fs
C
iss
C
oss
C
rss
NOTES: 2. Technique should limit TJ – TC to 10°C maximum.
Drain-to-source breakdown voltage ID = 250 µA, VGS = 0 60 V
Gate-to-source threshold voltage
Gate-to-source breakdown voltage IGS = 250 µA 18 V
Source-to-gate breakdown voltage ISG = 250 µA 9 V
Reverse drain-to-GND breakdown voltage (across
D1, D2, D3)
Drain-to-source on-state voltage
Forward on-state voltage, source-to-drain
Forward on-state voltage, GND-to-drain
Forward-gate current, drain short circuited to
source
Reverse-gate current, drain short circuited to
source
Forward transconductance
Short-circuit input capacitance, common source 107 137
Short-circuit output capacitance, common source
Short-circuit reverse transfer capacitance, common
source
3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
ID = 1 mA,
See Figure 5
Drain-to-GND current = 250 µA 100 V
ID = 1.4 A,
See Notes 2 and 3
IS = 1.4 A,
VGS = 0 (Z1, Z2, Z3),
See Notes 2 and 3 and Figure 12
ID = 1.4 A (D1, D2, D3),
See Notes 2 and 3
V
= 48 V,
VGS = 0
VGS = 15 V, VDS = 0 20 200 nA
VSG = 5 V, VDS = 0 10 100 nA
= 48
DGND
VGS = 10 V,
I
= 1.4 A,
See Notes 2 and 3
and Figures 6 and 7
VDS = 15 V, ID = 0.7 A,
See Notes 2 and 3 and Figure 9
VDS = 25 V, VGS = 0,
f = 1 MHz, See Figure 11
TPIC5303
POWER DMOS ARRAY
VDS = V
VGS = 10 V,
TC = 25°C 0.05 1
TC = 125°C 0.5 10
TC = 25°C 0.05 1
TC = 125°C 0.5 10
TC = 25°C 0.4 0.46
TC = 125°C 0.62 0.66
GS,
1.5 1.8 2.2 V
0.56 0.64 V
0.9 1.1 V
5 V
1 1.19 S
71 89
22 28
µ
µ
p
source-to-drain and GND-to-drain diode characteristics, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IS = 0.7 A,
= 0,
GS
See Fi
ures 1 and 14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VDS = 48 V,
=
Z1, Z2, and Z3 92
D1, D2, and D3 244
µs,
Z1, Z2, and Z3
D1, D2, and D3 1.3
0.1
µ
3
TPIC5303
DD
,
L
,
r1
,
ns
See Figure 3
nH
3-CHANNEL INDEPENDENT GATE-PROTECTED
POWER DMOS ARRAY
SLIS039A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995
resistive-load switching characteristics, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
d(on)
t
d(off)
t
r2
t
f2
Q
Q
Q
L
D
L
S
R
g
thermal resistance
R
θJA
R
θJB
R
θJP
NOTES: 4. Package mounted on an FR4 printed-circuit board with no heatsink.
Turn-on delay time 25 40
Turn-off delay time
Rise time
Fall time 7 14
Total gate charge
g
Threshold gate-to-source charge
gs(th)
Gate-to-drain charge
gd
Internal drain inductance 5
Internal source inductance 5
Internal gate resistance 0.25 Ω
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Junction-to-ambient thermal resistance See Notes 4 and 7 115
Junction-to-board thermal resistance See Notes 5 and 7 64
Junction-to-pin thermal resistance See Notes 6 and 7 33
5. Package mounted on a 24 inch2, 4-layer FR4 printed-circuit board.
6. Package mounted in intimate contact with infinite heatsink.
7. All outputs with equal power
V
= 25 V, R
tf1 = 10 ns,
VDS = 48 V,
= 36 Ω,t
See Figure 2
ID = 0.7 A, VGS = 10 V,
= 10 ns,
27 40
15 25
2.1 2.6
0.3 0.38
1.2 1.5
nC
°C/W
PARAMETER MEASUREMENT INFORMATION
1
Reverse di/dt = 100 A/µs
0.5
0
– 0.5
25% of I
– 1
Shaded Area = QRR
– 1.5
– 2
– Source-to-Drain Diode Current – AI
S
– 2.5
†
I
RM
– 3
0 100 200 300 400
†
IRM = maximum recovery current
‡
The above waveform is representative of D1, D2, and D3 in shape only.
t
rr(SD)
500 600 700 800 900 1000
Time – ns
†
RM
VDS = 48 V
VGS = 0
TJ = 25°C
Z1, Z2, and Z3
‡
Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VDD = 25 V
Pulse Generator
R
gen
NOTE A: CL includes probe and jig capacitance.
50 Ω
V
GS
50 Ω
TEST CIRCUIT
TPIC5303
3-CHANNEL INDEPENDENT GATE-PROTECTED
POWER DMOS ARRAY
SLIS039A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995
t
r1
R
L
V
DS
DUT
CL 30 pF
(see Note A)
V
t
d(on)
GS
t
f2
V
DS
VOLTAGE WAVEFORMS
t
f1
10 V
0 V
t
d(off)
t
r2
V
DD
V
DS(on)
12-V
Battery
0.2 µF
0 V
Figure 2. Resistive-Switching Test Circuit and Voltage Waveforms
Current
Regulator
Q
g
Gate Voltage
VOLTAGE WAVEFORM
50 kΩ
IG = 100 µA
IG Current-
Sampling Resistor
TEST CIRCUIT
0.3 µF
V
DS
Same Type
as DUT
V
DD
DUT
ID Current-
Sampling Resistor
10 V
V
GS
Q
gs(th)
Figure 3. Gate-Charge Test Circuit and Waveform
Q
gd
Time
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
TPIC5303
E
3-CHANNEL INDEPENDENT GATE-PROTECTED
POWER DMOS ARRAY
SLIS039A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
VDD = 25 V
476 µH
V
Pulse Generator
(see Note A)
50 Ω
R
gen
I
V
GS
50 Ω
TEST CIRCUIT
V
D
DS
DUT
GS
V
DS
t
t
w
I
D
VOLTAGE AND CURRENT WAVEFORMS
av
15 V
0 V
I
AS
(see Note B)
0 V
V
0 V
(BR)DSX
= 60 V Min
NOTES: A. The pulse generator has the following characteristics: tr ≤ 10 ns, tf ≤ 10 ns, ZO = 50 Ω.
B. Input pulse duration (tw) is increased until peak current IAS = 5 A.
IAS
Energy test level is defined as EAS+
tav = avalanche time.
V
(BR)DSX
2
t
av
+
10.2 mJ, where
Figure 4. Single-Pulse Avalanche Energy Test Circuit and Waveforms
TYPICAL CHARACTERISTICS
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
2.5
VDS = V
2
1.5
1
GS
ID = 1 mA
ID = 100 µA
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANC
JUNCTION TEMPERATURE
0.8
ID = 1.4 A
0.6
ΩOn-State Resistance –
VGS = 10 V
0.4
– Static Drain-to-Source
vs
VGS = 15 V
– Gate-to-Source Threshold Voltage – V
GS(th)
V
6
0.5
0
–40 –20
0.2
DS(on)
r
0 20406080
TJ – Junction Temperature – °C
100 120 140 160
0
–40 –20
0 20406080
TJ – Junction Temperature – °C
Figure 5 Figure 6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
100 120 140 160
3-CHANNEL INDEPENDENT GATE-PROTECTED
SLIS039A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995
TYPICAL CHARACTERISTICS
TPIC5303
POWER DMOS ARRAY
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
1
0.9
TJ = 25°C
0.8
0.7
0.6
ΩOn-State Resistance –
0.5
0.4
0.3
– Static Drain-to-Source
0.2
DS(on)
r
0.1
0.1 1
VGS = 10 V
VGS = 15 V
ID – Drain Current – A
Figure 7 Figure 8
10
DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
5
VGS = 15 V
4.5
n
4
3.5
3
2.5
2
– Drain Current – A
D
I
1.5
1
0.5
0
024 6
VDS – Drain-to-Source Voltage – V
VGS = 0.4 V
TJ = 25°C
(unless otherwise
noted
VGS = 10 V
VGS = 5.6 V
VGS = 4 V
VGS = 2.8 V
8
FORWARD TRANSCONDUCTANCE
75
70
65
60
55
50
45
40
35
30
25
Percentage of Units – %
20
15
10
5
0
1.04
1.07
1.10
gfs – Forward Transconductance – S
DRAIN CURRENT
DISTRIBUTION OF
GATE-TO-SOURCE VOLTAGE
5
1.13
1.16
1.19
Total Number of
Units = 2064
VDS = 15 V
ID = 0.7 A
TJ = 25°C
1.22
1.25
1.28
1.31
1.34
1.37
1.40
4
3
2
– Drain Current – A
D
I
1
0
0235
146
VGS – Gate-to-Source Voltage – V
T
= –40°C
J
TJ = 25°C
TJ = 75°C
Figure 9 Figure 10
vs
TJ = 125°C
TJ = 150°C
78
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
TPIC5303
3-CHANNEL INDEPENDENT GATE-PROTECTED
POWER DMOS ARRAY
SLIS039A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995
TYPICAL CHARACTERISTICS
CAPACITANCE
DRAIN-TO-SOURCE VOLTAGE
250
VGS = 0
225
f = 1 MHz
TJ = 25°C
200
C
@ 0 V = 160 pF
iss
C
@ 0 V = 216 pF
175
150
125
100
C – Capacitance – pF
oss
C
@ 0 V = 78 pF
rss
75
50
25
0
0 4 8 12162024
VDS – Drain-to-Source Voltage – V
Figure 11 Figure 12
DRAIN-TO-SOURCE VOLTAGE AND
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
60
ID = 0.7 A
TJ = 25°C
See Figure 3
50
VDD = 20 V
40
30
20
– Drain-to-Source Voltage – V
DS
V
10
0
0 0.5 1 1.5 2 2.5 3
VDD = 30 V
VDD = 20 V
Qg – Gate Charge – nC
vs
C
C
C
iss
oss
rss
28 32 36 40
VDD = 48 V
3.5 4
12
10
8
6
4
2
0
– Source-to-Drain Diode Current – A
SD
I
– Gate-to-Source Voltage – V
– Reverse-Recovery Time – ns
rr
GS
t
V
SOURCE-TO-DRAIN DIODE CURRENT
vs
SOURCE-TO-DRAIN VOLTAGE
10
VGS = 0
1
TJ = 75°C
TJ = 125°C
TJ = 150°C
0.1
0.1 1 10
VSD – Source-to-Drain Voltage – V
TJ = 25°C
TJ = –40°C
REVERSE-RECOVERY TIME
vs
REVERSE di/dt
280
260
240
220
200
180
160
140
120
100
80
60
40
20
0
0 200 400
Z1, Z2, and Z3
100 300 500
Reverse di/dt – A/µs
D1, D2, and D3
VDS = 48 V
VGS = 0
IS = 0.7 A
TJ = 25°C
See Figure 1
600
Figure 13 Figure 14
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3-CHANNEL INDEPENDENT GATE-PROTECTED
SLIS039A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995
THERMAL INFORMATION
MAXIMUM DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
10
TC = 25°C
†
1 µs
†
10 ms
†
1 ms
1
– Maximum Drain Current – A
D
I
DC Conditions
0.1
0.1 1
VDS – Drain-to-Source Voltage – V
†
Less than 2% duty cycle
‡
Device mounted on FR4 printed-circuit board with no heatsink.
§
Device mounted in intimate contact with infinite heatsink.
R
θJA
‡
Figure 15
†
500 µs
§
R
θJP
10 100
TPIC5303
POWER DMOS ARRAY
MAXIMUM PEAK AVALANCHE CURRENT
vs
TIME DURATION OF AVALANCHE
10
See Figure 4
TC = 25°C
– Maximum Peak Avalanche Current – A
AS
I
1
0.01 0.1 1 10
TC = 125°C
tav – Time Duration of Avalanche – ms
Figure 16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
TPIC5303
3-CHANNEL INDEPENDENT GATE-PROTECTED
POWER DMOS ARRAY
SLIS039A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995
THERMAL INFORMATION
C/W
°
100
10
1
DC Conditions
d = 0.5
d = 0.2
d = 0.1
d = 0.05
d = 0.02
D PACKAGE
†
JUNCTION-TO-BOARD THERMAL RESISTANCE
vs
PULSE DURATION
d = 0.01
– Junction-to-Board Thermal Resistance –
JBθ
R
0.1
0.0001 0.001
†
Device mounted on 24 in2, 4-layer FR4 printed-circuit board with no heatsink
NOTE A: Z
Single Pulse
(t) = r(t) R
θJB
tw = pulse duration
tc = cycle time
d = duty cycle = tw/t
θJB
0.01 0.1 1 100
tw – Pulse Duration – s
c
Figure 17
t
c
t
w
10
I
D
0
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
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Copyright 1998, Texas Instruments Incorporated
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