TEXAS INSTRUMENTS TPIC5203 Technical data

TPIC5203

2-CHANNEL INDEPENDENT GATE-PROTECTED

POWER DMOS ARRAY

SLIS040 – SEPTEMBER 1994

• Low r

DS(on)

• High Voltage Output...60 V

•Extended ESD Capability...4000 V

• Pulsed Current...8 A Per Channel

• Fast Commutation Speed

. . . 0.26 Ω Typ

GND

SOURCE1

GATE2

DRAIN2

D PACKAGE

(TOP VIEW)

1
2
3
4

8
7
6
5

DRAIN1
GATE1
SOURCE2
NC

description

NC – No internal connection

The TPIC5203 is a monolithic gate-protected
power DMOS array that consists of two
independent electrically isolated N-channel enhancement-mode DMOS transistors. Each transistor features
integrated high-current zener diodes (Z

CXa

and Z

) to prevent gate damage in the event that an overstress

CXb

condition occurs. These zener diodes also provide up to 4000 V of ESD protection when tested using the
human-body model of a 100-pF capacitor in series with a 1.5-kΩ resistor.

The TPIC5203 is offered in a standard eight-pin small-outline surface-mount (D) package and is characterized
for operation over the case temperature range of –40°C to 125°C.

schematic

GATE1

Z
Z

7

C1b
C1a

DRAIN1

Q1

8

D1

Z1

GATE2

Z
Z

3

C2b
C2a

DRAIN2

Q2

4

D2

Z2

2

SOURCE1

NOTE: For correct operation, no terminal pin may be taken below GND.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

1 6

GND

SOURCE2

Copyright  1994, Texas Instruments Incorporated

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2–1

TPIC5203
2-CHANNEL INDEPENDENT GATE-PROTECTED
POWER DMOS ARRAY

SLIS040 – SEPTEMBER 1994

absolute maximum ratings over operating case temperature range (unless otherwise noted)

Drain-to-source voltage, V

60 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DS

†

Source-to-GND voltage (Q1, Q2) 100 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Drain-to-GND voltage (Q1, Q2) 100 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Gate-to-source voltage range, V
Continuous drain current, each output, T
Continuous source-to-drain diode current, T
Pulsed drain current, each output, I
Continuous gate-to-source zener diode current, T
Pulsed gate-to-source zener-diode current, T
Single-pulse avalanche energy, E
Continuous total dissipation, T
Operating virtual junction temperature range, T
Operating case temperature range, T
Storage temperature range, T

–9 V to 18 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GS

max

AS

= 25°C (see Figure 15) 962 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

= 25°C 1.6 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C

= 25°C 1.6 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C

, TC = 25°C (see Note 1 and Figure 15) 8 A. . . . . . . . . . . . . . . . . . . . .

= 25°C ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C

= 25°C ±500 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C

, TC = 25°C (see Figures 4, 15, and 16) 21.6 mJ. . . . . . . . . . . . . . . . . . .

–40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C

J

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: Pulse duration = 10 ms, duty cycle = 2%

2–2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2-CHANNEL INDEPENDENT GATE-PROTECTED

I

Zero-gate-voltage drain current

DS

,

A

I

Leakage current, drain-to-GND

V

V

A

r

Static drain-to-source on-state resistance

D

,

Ω

F

trrReverse-recovery time

ns

V

g

di/dt

100 A/

QRRTotal diode charge

See Figures 1 and 14

nC

electrical characteristics, TC = 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

(BR)DSX

V

GS(th)

V

(BR)GS

V

(BR)SG

V

(BR)

V

DS(on)

V

F(SD)

V

F

DSS

I

GSSF

I

GSSR

lkg

DS(on)

g

fs

C

iss

C

oss

C

rss

NOTES: 2. Technique should limit TJ – TC to 10°C maximum.

Drain-to-source breakdown voltage ID = 250 µA, VGS = 0 60 V
Gate-to-source threshold voltage
Gate-to-source breakdown voltage IGS = 250 µA 18 V

Source-to-gate breakdown voltage ISG = 250 µA 9 V
Reverse drain-to-GND breakdown voltage (across

D1, D2)
Drain-to-source on-state voltage

Forward on-state voltage, source-to-drain

Forward on-state voltage, GND-to-drain

Forward-gate current, drain short circuited to
source

Reverse-gate current, drain short circuited to
source

Forward transconductance
Short-circuit input capacitance, common source 150 275

Short-circuit output capacitance, common source
Short-circuit reverse transfer capacitance, common

source

3. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.

ID = 1 mA,
See Figure 5

Drain-to-GND current = 250 µA 100 V
ID = 1.6 A,

See Notes 2 and 3
IS = 1.6 A,

VGS = 0 (Z1, Z2),
See Notes 2 and 3 and Figure 12

ID = 1.6 A (D1, D2),
See Notes 2 and 3

V

= 48 V,

VGS = 0

VGS = 15 V, VDS = 0 20 200 nA

VSG = 5 V, VDS = 0 10 100 nA

= 48

DGND

VGS = 10 V,
I

= 1.6 A,
See Notes 2 and 3
and Figures 6 and 7

VDS = 15 V, ID = 800 mA,
See Notes 2 and 3 and Figure 9

VDS = 25 V, VGS = 0,
f = 1 MHz, See Figure 11

TPIC5203

POWER DMOS ARRAY

SLIS040 – SEPTEMBER 1994

VDS = V

VGS = 10 V,

TC = 25°C 0.05 1
TC = 125°C 0.5 10

TC = 25°C 0.05 1
TC = 125°C 0.5 10

TC = 25°C 0.26 0.31

TC = 125°C 0.41 0.45

GS,

1.5 2.05 2.2 V

0.42 0.5 V

1 1.2 V

5 V

1.5 1.83 S

100 150

40 125

µ

µ

p

source-to-drain and GND-to-drain diode characteristics, TC = 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

IS = 800 mA,

= 0,

GS

See Fi

ures 1 and 14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

VDS = 48 V,

=

µs,

Z1 and Z2 50
D1 and D2 265
Z1 and Z2
D1 and D2 1240

63

2–3

TPIC5203

DD

,

L

,

en

,

ns

See Figure 3

nH

2-CHANNEL INDEPENDENT GATE-PROTECTED
POWER DMOS ARRAY

SLIS040 – SEPTEMBER 1994

resistive-load switching characteristics, TC = 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

d(on)

t

d(off)

t

r

t

f

Q
Q
Q
L

D

L

S

R

g

thermal resistance

R

θJA

R

θJB

R

θJP

NOTES: 4. Package mounted on an FR4 printed-circuit board with no heatsink

Turn-on delay time 25 50
Turn-off delay time
Rise time
Fall time 7 15
Total gate charge

g

Threshold gate-to-source charge

gs(th)

Gate-to-drain charge

gd

Internal drain inductance 5
Internal source inductance 5
Internal gate resistance 0.25 Ω

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Junction-to-ambient thermal resistance See Notes 4 and 7 130
Junction-to-board thermal resistance See Notes 5 and 7 79
Junction-to-pin thermal resistance See Notes 6 and 7 34

5. Package mounted on a 24 inch2, 4-layer FR4 printed-circuit board

6. Package mounted in intimate contact with infinite heatsink

7. All outputs with equal power

V

= 25 V, R

t

= 10 ns,

dis

VDS = 48 V,

= 30 Ω,t

See Figure 2

ID = 0.8 A, VGS = 10 V,

= 10 ns,

27 50
15 30

4.7 5.9

0.5 0.6

1.9 2.4

nC

°C/W

PARAMETER MEASUREMENT INFORMATION

1.5

1

Reverse di/dt = 100 A/µs

0.5

0

– 0.5

– 1

– 1.5

– Source-to-Drain Diode Current – AI

S

– 2

†

I

RM

– 2.5

0 50 100 150 200 250 300 350 400 450 500

†

IRM = maximum recovery current

‡

The above waveform is representative of D1 and D2 in shape only.

Shaded Area = QRR

t

rr(SD)

Time – ns

25% of I

VDS = 48 V
VGS = 0
TJ = 25°C
Z1 and Z2

RM

‡

†

Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diode

2–4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265