Texas Instruments TPIC46L03DBR, TPIC46L03DB, TPIC46L02DB, TPIC46L01DBLE, TPIC46L01DB Datasheet
TPIC46L01, TPIC46L02, TPIC46L03
6-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS055A – NOVEMBER 1996 - REVISED SEPTEMBER 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
6-Channel Serial-in/Parallel-in Low-side
Pre-FET Driver
D
Device Can Be Cascaded
D
Internal 55-V Inductive Load Clamp and
V
GS
Protection Clamp for External Power
FETs
D
Independent Shorted-Load/Short-to-Battery
Fault Detection on All Drain Terminals
D
Independent Off-State Open-Load Fault
Sense
D
Over-Battery-Voltage Lockout Protection
and Fault Reporting
D
Under-Battery-Voltage Lockout Protection
for TPIC46L01 and TPIC46L02
D
Asynchronous Open-Drain Fault Flag
D
Device Output Can be Wire-ORed with
Multiple External Devices
D
Fault Status Returned Through Serial
Output Terminal
D
Internal Global Power-on Reset of Device
D
High-Impedance CMOS Compatible Inputs
With Hysteresis
D
TPIC46L01 and TPIC46L03 Disables the
Gate Output When a Shorted-Load Fault
Occurs
D
TPIC46L02 Transitions the Gate Output to a
Low-Duty-Cycle PWM Mode When a
Shorted-Load Fault Occurs
description
The TPIC46L01, TPIC46L02, and TPIC46L03 are low-side predrivers that provide serial input interface and
parallel input interface to control six external field-effect transistor(FET) power switches such as offered in the
TI TPIC family of power arrays. These devices are designed primarily for low-frequency switching, inductive
load applications such as solenoids and relays. Fault status for each channel is available in a serial-data format.
Each driver channel has independent off-state open-load detection and on-state shorted-load/short-to-battery
detection. Battery overvoltage and undervoltage detection and shutdown are provided. Battery and output load
faults provide real-time fault reporting to the controller. Each channel also provides inductive-voltage-transient
protection for the external FET.
These devices provide control of output channels through a serial input interface or a parallel input interface.
A command to enable the output from either interface enables the respective channel GATE output to the
external FET . The serial input interface is recommended when the number of signals between the control device
and the predriver must be minimized, and the speed of operation is not critical. In applications where the
predriver must respond very quickly or asynchronously, the parallel input interface is recommended.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
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FL T
VCOMPEN
VCOMP
IN0
IN1
IN2
IN3
IN4
IN5
CS
SDO
SDI
SCLK
V
CC
V
BAT
GATE0
DRAIN0
GATE1
DRAIN1
DRAIN2
GATE2
GATE3
DRAIN3
DRAIN4
GATE4
DRAIN5
GATE5
GND
DB PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
TPIC46L01, TPIC46L02, TPIC46L03
6-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS055A – NOVEMBER 1996 - REVISED SEPTEMBER 1997
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
For serial operation, the control device must transition CS from high to low to activate the serial input interface.
When this occurs, SDO is enabled, fault data is latched into the serial input interface, and the FLT
flag is
refreshed.
Data is clocked into the serial registers on low-to-high transitions of SCLK through SDI. Each string of data must
consist of 8 bits of data. In applications where multiple devices are cascaded together, the string of data must
consist of 8 bits for each device. A high data bit turns the respective output channel on and a low data bit turns
it off. Fault data for the device is clocked out of SDO as serial input data is clocked into the device. Fault data
consists of fault flags for the over-battery voltage (bit 8), under-battery voltage (bit 7) (not on TPIC46L03) and
shorted/open-load flags (bits 1-6) for each of the six output channels. A logic-high bit in the fault data indicates
a fault and a logic-low bit indicates that no fault is present on that channel. Fault register bits are set or cleared
asynchronously to reflect the current state of the hardware. The fault must be present when CS
is transitioned
from high to low to be captured and reported in the serial fault data. New faults cannot be captured in the serial
register when CS
is low. CS must be transitioned high after all of the serial data has been clocked into the device.
A low-to-high transition of CS
transfers the last six bits of serial data to the output buffer, puts SDO in a
high-impedance state, and clears and re-enables the fault register. The TPIC46L01/L02/L03 was designed to
allow the serial input interfaces of multiple devices to be cascaded together to simplify the serial interface to the
controller. Serial input data flows through the device and is transferred out SDO following the fault data in
cascaded configurations.
For parallel operation, data is asynchronously transferred directly from the parallel input interface (IN0-IN5) to
the respective GA TE output. SCLK or CS
are not required for parallel control. A 1 on the parallel input turns the
respective channel on, where a 0 turns it off. Note that either the serial interface or the parallel interface can
enable a channel. Under parallel operation, fault data must still be collected through the serial data interface.
The predrivers monitor the drain voltage for each channel to detect shorted-load or open-load fault conditions
in the on and off states respectively. These devices offer the option of using an internally generated
fault-reference voltage or an externally supplied VCOMP for fault detection. The internal fault reference is
selected by connecting VCOMPEN
to GND and the external reference is selected by connecting VCOMPEN
to V
CC
. The drain voltage is compared to the fault-reference voltage when the channel is turned on to detect
shorted-load conditions and when the channel is off to detect open-load conditions. When a shorted-load fault
occurs using the TPIC46L01 or TPIC46L03, the channel is turned off and a fault signal is sent to FLT
as well
as to the serial fault-register bit. When a shorted-load fault occurs while using the TPIC46L02, the channel
transitions into a low-duty-cycle, pulse-width-modulated (PWM) signal as long as the fault is present.
Shorted-load conditions must be present for at least the shorted-load deglitch time, t
(STBDG)
, in order to be
flagged as a fault. A fault signal is sent to FL T
as well as the serial fault register bit. More detail on fault detection
operation is presented in the device operation section of this data sheet.
The TPIC46L01 and TPIC46L02 provide protection from over-battery voltage and under-battery voltage
conditions irrespective of the state of the output channels. The TPIC46L03 provides protection from over-battery
voltage conditions irrespective of the state of the output channels When the battery voltage is greater than the
overvoltage threshold or less than the undervoltage threshold (except for the TPIC46L03, which has no
undervoltage threshold), all channels are disabled and a fault signal is sent to FL T
as well as to the respective
fault register bits. The outputs return to normal operation once the battery voltage fault has been corrected.
When an over-battery/under-battery voltage condition occurs, the device reports the battery fault, but disables
fault reporting for open and shorted-load conditions. Fault reporting for open and shorted-load conditions are
re-enabled after the battery fault condition has been corrected.
These devices provide inductive transient protection on all channels. The drain voltage is clamped to protect
the FET . This clamp voltage is defined by the sum of V
C
and turn-on voltage of the external FET . The predriver
also provides a gate-to-source voltage (V
GS
) clamp to protect the GA TE-source terminals of the power FET from
exceeding their rated voltages.
These devices provide pulldown resistors on all inputs except CS
. A pullup resistor is used on CS.
TPIC46L01, TPIC46L02, TPIC46L03
6-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS055A – NOVEMBER 1996 - REVISED SEPTEMBER 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematic diagram
Parallel Register
PREZ
D
Q
GND
Serial Register
Fault Logic UVLO†OVLO
8
SDO
FLT
8
STB and Open-Load Fault
Protection
OSC
BIAS
V
bg
S
B
A
Gate
Drive Block
DRAIN 0
DRAIN 1
DRAIN 2
DRAIN 3
DRAIN 4
DRAIN 5
GATE 0
GATE 1
GATE 2
GATE 3
GATE 4
GATE 5
OVLO
UVLO
†
2
VCOMPEN
VCOMP
SDI
SCLK
CS
IN 0
IN 1
IN 2
IN 3
IN 4
IN 5
V
BAT
8
V
CC
6
†
UVLO is not in TPIC46L03
TPIC46L01, TPIC46L02, TPIC46L03
6-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS055A – NOVEMBER 1996 - REVISED SEPTEMBER 1997
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME NO.
I/O
DESCRIPTION
CS 10 I Chip select. A high to low transition on the CS enables SDO, latches fault data into the serial interface, and
refreshes the fault flag. When CS
is high, the fault registers can change fault status. On the falling edge of CS, fault
data is latched into the serial output register and transferred using SDO and SCLK. On a low to high transition of
CS
, serial data is latched in to the output control register.
DRAIN0
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5
26
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23
20
19
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I FET drain inputs. DRAIN0 through DRAIN5 are used for both open-load and short-circuit fault detection at the drain
of the external FETs. They are also used for inductive transient protection.
FLT 1 O Fault flag. FLT is an open-drain output that provides a real-time fault flag for shorted-load/open-load/over-battery
voltage/under-battery voltage faults. The device can be ORed with FL T
on other devices for interrupt handling. FLT
requires an external pullup resistor.
GATE0
GATE1
GATE2
GATE3
GATE4
GATE5
27
25
22
21
18
16
O Gate drive output. GATE0 through GA TE5 outputs are derived from the V
BAT
supply. Internal clamps prevent the
voltages on these nodes from exceeding the VGS rating on most FETs.
GND 15 I Ground and substrate
IN0
IN1
IN2
IN3
IN4
IN5
4
5
6
7
8
9
I Parallel gate driver inputs. IN0 through IN5 are real-time controls for the gate predrive circuitry. They are CMOS
compatible with hysteresis.
SCLK 13 I Serial clock. SCLK clocks the shift register. Serial data is clocked into SDI and serial fault data is clocked out of
SDO on the falling edge of the serial clock.
SDI 12 I Serial data input. Output control data is clocked into the serial register through SDI. A 1 on SDI commands a
particular gate output on and a 0 turns it off.
SDO 11 O Serial data output. SDO is a 3-state output that transfers fault data to the controling device. It also passes serial
input data to the next stage for cascaded operation. SDO is taken to a high-impedance state when CS
is in a high
state.
V
BAT
28 I Battery supply voltage input
V
CC
14 I Logic supply voltage
VCOMPEN 2 I Fault reference voltage select. VCOMPEN selects the internally generated fault reference voltage (0) or an
external fault reference (1) to be used in the shorted- and open-load fault detection circuitry.
VCOMP 3 I Fault reference voltage. VCOMP provides an external fault reference voltage for the shorted- and open-load fault
detection circuitry.
TPIC46L01, TPIC46L02, TPIC46L03
6-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS055A – NOVEMBER 1996 - REVISED SEPTEMBER 1997
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
(see Note 1) –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Battery supply voltage range, V
BAT
–0.3 V to 60 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range,V
I
(at any input) –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(SDO and FLT) –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Drain-to-source input voltage, V
DS
–0.3 V to 60 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage, V
O
–0.3 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating case temperature range, T
C
–40°C to + 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thermal resistance, junction to ambient, R
θJA
112°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, T
J
150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–40°C to + 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
recommended operating conditions
MIN NOM MAX UNIT
Logic supply voltage, V
CC
4.5 5.0 5.5 V
Battery supply voltage, V
BAT
8 24 V
High-level input voltage, V
IH
0.85 V
CC
V
CC
V
Low-level input voltage, V
IL
0 0.15 V
CC
V
Setup time, SDI high before SCLK rising edge, tsu (see Figure 5) 10 ns
Hold time, SDI high after SCLK rising edge, th (see Figure 5) 10 ns
Case temperature, T
C
–40 125 °C
TPIC46L01, TPIC46L02, TPIC46L03
6-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER
SLIS055A – NOVEMBER 1996 - REVISED SEPTEMBER 1997
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
BAT
Supply current, V
BAT
All outputs off, V
BAT
= 12 V 300 500 700 µA
I
CC
Supply current, V
CC
All outputs off, V
BAT
= 5.5 V 1 2.6 4.2 mA
V
(turnon)
Turn-on voltage, logic operational, V
CC
V
BAT
= 5.5 V,
Check output functionality
2.6 3.5 4.4 V
V
(ovsd)
Over-battery-voltage shutdown
32 34 36 V
V
hys(ov)
Over-battery-voltage reset hysteresis
Gate disabled
,
See Figure 16
0.5 1 1.5 V
V
(uvsd)
Under-battery-voltage shutdown,
(TPIC46L01, L02 only)
4.1 4.8 5.4 V
V
hys(uv)
Under-battery-voltage reset hysteresis,
(TPIC46L01, L02 only)
Gate disabled
,
See Figure 17
100 200 300 mV
8 V < V
BAT
< 24, IO = 100 µA 7 13.5 V
VGGate drive voltage
5.5 V < V
BAT
< 8 V, IO = 100 µA 5 7 V
I
O(H)
Maximum current output for drive terminals,
pullup
V
OUT
= GND 0.5 1.2 2.5 mA
I
O(L)
Maximum current output for drive terminals,
pulldown
V
OUT
= 7 V 0.5 1.2 2.5 mA
V
(stb)
Short-to-battery/shorted-load/open-load
detection voltage
VCOMPEN = L 1.1 1.25 1.4 V
V
hys(stb)
Short-to-battery hysteresis 40 100 150 mV
V
D(open)
Open-load off-state detection drain voltage
threshold
VCOMPEN = L 1.1 1.25 1.4 V
V
hys(open)
Open-load hysteresis 40 100 150 mV
I
I(open)
Open-load off-state detection current 30 60 80 µA
I
I(PU)
Input pullup current (CS) VCC = 5 V, VIN = 0 10 µA
I
I(PD)
Input pulldown current VCC = 5 V, VIN = 5 V 10 µA
V
I(hys)
Input voltage hysteresis VCC = 5 V 0.6 0.85 1.1 V
V
O(SH)
High-level serial output voltage IO = 1 mA 0.8 V
CC
V
V
O(SL)
Low-level serial output voltage IO = 1 mA 0.1 0.4 V
I
OZ(SD)
3-state current serial-data output VCC = 0 to 5.5 V -10 1 10 µA
V
O(CFLT)
Fault-interrupt output voltage IO = 1 mA 0.1 0.5 V
V
I(COMP)
Fault-external reference voltage VCOMPEN = H 1 3 V
V
C
Output clamp voltage, (TPIC46L01, L02 only) dc < 1%, tw = 100 µs 47 55 63 V
V
C
Output clamp voltage, (TPIC46L03 only) dc < 1%, tw = 100 µs 47 60 V
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