TEXAS INSTRUMENTS TPIC46L01, TPIC46L02, TPIC46L03 Technical data

TPIC46L01, TPIC46L02, TPIC46L03

6-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER

SLIS055A – NOVEMBER 1996 - REVISED SEPTEMBER 1997

D

6-Channel Serial-in/Parallel-in Low-side
Pre-FET Driver

D

Device Can Be Cascaded

D

Internal 55-V Inductive Load Clamp and
V

Protection Clamp for External Power

GS

FETs

D

Independent Shorted-Load/Short-to-Battery
Fault Detection on All Drain Terminals

D

Independent Off-State Open-Load Fault
Sense

D

Over-Battery-Voltage Lockout Protection
and Fault Reporting

D

Under-Battery-Voltage Lockout Protection
for TPIC46L01 and TPIC46L02

D

Asynchronous Open-Drain Fault Flag

D

Device Output Can be Wire-ORed with
Multiple External Devices

D

Fault Status Returned Through Serial
Output Terminal

D

Internal Global Power-on Reset of Device

D

High-Impedance CMOS Compatible Inputs
With Hysteresis

D

TPIC46L01 and TPIC46L03 Disables the
Gate Output When a Shorted-Load Fault
Occurs

D

TPIC46L02 Transitions the Gate Output to a
Low-Duty-Cycle PWM Mode When a
Shorted-Load Fault Occurs

description

FL T

IN0
IN1
IN2
IN3
IN4
IN5

CS

SDO

SDI

SCLK

V

CC

DB PACKAGE

(TOP VIEW)

1

28

2

27

3

26

4

25

5

24

6

23

7

22

8

21

9

20

10

19

11

18

12

17

13

16

14

15

V

BAT

GATE0
DRAIN0
GATE1
DRAIN1
DRAIN2
GATE2
GATE3
DRAIN3
DRAIN4
GATE4
DRAIN5
GATE5
GND

VCOMPEN

VCOMP

The TPIC46L01, TPIC46L02, and TPIC46L03 are low-side predrivers that provide serial input interface and
parallel input interface to control six external field-effect transistor(FET) power switches such as offered in the
TI TPIC family of power arrays. These devices are designed primarily for low-frequency switching, inductive
load applications such as solenoids and relays. Fault status for each channel is available in a serial-data format.
Each driver channel has independent off-state open-load detection and on-state shorted-load/short-to-battery
detection. Battery overvoltage and undervoltage detection and shutdown are provided. Battery and output load
faults provide real-time fault reporting to the controller. Each channel also provides inductive-voltage-transient
protection for the external FET.

These devices provide control of output channels through a serial input interface or a parallel input interface.
A command to enable the output from either interface enables the respective channel GATE output to the
external FET . The serial input interface is recommended when the number of signals between the control device
and the predriver must be minimized, and the speed of operation is not critical. In applications where the
predriver must respond very quickly or asynchronously, the parallel input interface is recommended.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1997, Texas Instruments Incorporated

1

TPIC46L01, TPIC46L02, TPIC46L03
6-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER

SLIS055A – NOVEMBER 1996 - REVISED SEPTEMBER 1997

For serial operation, the control device must transition CS from high to low to activate the serial input interface.
When this occurs, SDO is enabled, fault data is latched into the serial input interface, and the FLT
refreshed.

Data is clocked into the serial registers on low-to-high transitions of SCLK through SDI. Each string of data must
consist of 8 bits of data. In applications where multiple devices are cascaded together, the string of data must
consist of 8 bits for each device. A high data bit turns the respective output channel on and a low data bit turns
it off. Fault data for the device is clocked out of SDO as serial input data is clocked into the device. Fault data
consists of fault flags for the over-battery voltage (bit 8), under-battery voltage (bit 7) (not on TPIC46L03) and
shorted/open-load flags (bits 1-6) for each of the six output channels. A logic-high bit in the fault data indicates
a fault and a logic-low bit indicates that no fault is present on that channel. Fault register bits are set or cleared
asynchronously to reflect the current state of the hardware. The fault must be present when CS
from high to low to be captured and reported in the serial fault data. New faults cannot be captured in the serial
register when CS
A low-to-high transition of CS
high-impedance state, and clears and re-enables the fault register. The TPIC46L01/L02/L03 was designed to
allow the serial input interfaces of multiple devices to be cascaded together to simplify the serial interface to the
controller. Serial input data flows through the device and is transferred out SDO following the fault data in
cascaded configurations.

For parallel operation, data is asynchronously transferred directly from the parallel input interface (IN0-IN5) to
the respective GA TE output. SCLK or CS
respective channel on, where a 0 turns it off. Note that either the serial interface or the parallel interface can
enable a channel. Under parallel operation, fault data must still be collected through the serial data interface.

is low. CS must be transitioned high after all of the serial data has been clocked into the device.

transfers the last six bits of serial data to the output buffer, puts SDO in a

are not required for parallel control. A 1 on the parallel input turns the

is transitioned

flag is

The predrivers monitor the drain voltage for each channel to detect shorted-load or open-load fault conditions
in the on and off states respectively. These devices offer the option of using an internally generated
fault-reference voltage or an externally supplied VCOMP for fault detection. The internal fault reference is
selected by connecting VCOMPEN
to V
shorted-load conditions and when the channel is off to detect open-load conditions. When a shorted-load fault
occurs using the TPIC46L01 or TPIC46L03, the channel is turned off and a fault signal is sent to FLT
as to the serial fault-register bit. When a shorted-load fault occurs while using the TPIC46L02, the channel
transitions into a low-duty-cycle, pulse-width-modulated (PWM) signal as long as the fault is present.
Shorted-load conditions must be present for at least the shorted-load deglitch time, t
flagged as a fault. A fault signal is sent to FL T
operation is presented in the device operation section of this data sheet.

The TPIC46L01 and TPIC46L02 provide protection from over-battery voltage and under-battery voltage
conditions irrespective of the state of the output channels. The TPIC46L03 provides protection from over-battery
voltage conditions irrespective of the state of the output channels When the battery voltage is greater than the
overvoltage threshold or less than the undervoltage threshold (except for the TPIC46L03, which has no
undervoltage threshold), all channels are disabled and a fault signal is sent to FL T
fault register bits. The outputs return to normal operation once the battery voltage fault has been corrected.
When an over-battery/under-battery voltage condition occurs, the device reports the battery fault, but disables
fault reporting for open and shorted-load conditions. Fault reporting for open and shorted-load conditions are
re-enabled after the battery fault condition has been corrected.

These devices provide inductive transient protection on all channels. The drain voltage is clamped to protect
the FET . This clamp voltage is defined by the sum of V
also provides a gate-to-source voltage (V
exceeding their rated voltages.

. The drain voltage is compared to the fault-reference voltage when the channel is turned on to detect

CC

to GND and the external reference is selected by connecting VCOMPEN

as well

as well as the serial fault register bit. More detail on fault detection

and turn-on voltage of the external FET . The predriver

) clamp to protect the GA TE-source terminals of the power FET from

GS

C

(STBDG)

as well as to the respective

, in order to be

These devices provide pulldown resistors on all inputs except CS

2

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. A pullup resistor is used on CS.

schematic diagram

TPIC46L01, TPIC46L02, TPIC46L03

6-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER

SLIS055A – NOVEMBER 1996 - REVISED SEPTEMBER 1997

8

Fault Logic UVLO†OVLO

SDI

SCLK

CS

IN 0
IN 1

IN 2
IN 3
IN 4
IN 5

Serial Register

V

CC

Parallel Register

8

GND

8

6

STB and Open-Load Fault

Protection

OSC

SDO

PREZ

D

DRAIN 0
DRAIN 1
DRAIN 2
DRAIN 3
DRAIN 4
DRAIN 5

S

FLT

Q

VCOMPEN

V

BAT

†

UVLO is not in TPIC46L03

2

OVLO

UVLO

BIAS

Gate

Drive Block

†

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

V

bg

B

A

GATE 0
GATE 1
GATE 2
GATE 3
GATE 4

GATE 5

VCOMP

3

TPIC46L01, TPIC46L02, TPIC46L03

I/O

DESCRIPTION

6-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER

SLIS055A – NOVEMBER 1996 - REVISED SEPTEMBER 1997

Terminal Functions

TERMINAL

NAME NO.

CS 10 I Chip select. A high to low transition on the CS enables SDO, latches fault data into the serial interface, and

DRAIN0
DRAIN1
DRAIN2
DRAIN3
DRAIN4
DRAIN5

FLT 1 O Fault flag. FLT is an open-drain output that provides a real-time fault flag for shorted-load/open-load/over-battery

GATE0
GATE1
GATE2
GATE3
GATE4
GATE5

GND 15 I Ground and substrate
IN0

IN1
IN2
IN3
IN4
IN5

SCLK 13 I Serial clock. SCLK clocks the shift register. Serial data is clocked into SDI and serial fault data is clocked out of

SDI 12 I Serial data input. Output control data is clocked into the serial register through SDI. A 1 on SDI commands a

SDO 11 O Serial data output. SDO is a 3-state output that transfers fault data to the controling device. It also passes serial

V

BAT

V

CC

VCOMPEN 2 I Fault reference voltage select. VCOMPEN selects the internally generated fault reference voltage (0) or an

VCOMP 3 I Fault reference voltage. VCOMP provides an external fault reference voltage for the shorted- and open-load fault

26
24
23
20
19
17

27
25
22
21
18
16

4
5
6
7
8
9

28 I Battery supply voltage input
14 I Logic supply voltage

refreshes the fault flag. When CS
data is latched into the serial output register and transferred using SDO and SCLK. On a low to high transition of
CS

, serial data is latched in to the output control register.

I FET drain inputs. DRAIN0 through DRAIN5 are used for both open-load and short-circuit fault detection at the drain

of the external FETs. They are also used for inductive transient protection.

voltage/under-battery voltage faults. The device can be ORed with FL T
requires an external pullup resistor.

O Gate drive output. GATE0 through GA TE5 outputs are derived from the V

voltages on these nodes from exceeding the VGS rating on most FETs.

I Parallel gate driver inputs. IN0 through IN5 are real-time controls for the gate predrive circuitry. They are CMOS

compatible with hysteresis.

SDO on the falling edge of the serial clock.

particular gate output on and a 0 turns it off.

input data to the next stage for cascaded operation. SDO is taken to a high-impedance state when CS
state.

external fault reference (1) to be used in the shorted- and open-load fault detection circuitry .

detection circuitry.

is high, the fault registers can change fault status. On the falling edge of CS, fault

on other devices for interrupt handling. FLT

supply. Internal clamps prevent the

BAT

is in a high

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

TPIC46L01, TPIC46L02, TPIC46L03

6-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER

SLIS055A – NOVEMBER 1996 - REVISED SEPTEMBER 1997

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Battery supply voltage range, V
Input voltage range,V
Output voltage range, V
Drain-to-source input voltage, V
Output voltage, V

–0.3 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

Operating case temperature range, T
Thermal resistance, junction to ambient, R
Operating virtual junction temperature range, T
Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to GND.

(see Note 1) –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(at any input) –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

(SDO and FLT) –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

–0.3 V to 60 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BA T

–0.3 V to 60 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DS

–40°C to + 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C

–40°C to + 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

112°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

θJA

150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

J

recommended operating conditions

MIN NOM MAX UNIT

Logic supply voltage, V
Battery supply voltage, V
High-level input voltage, V
Low-level input voltage, V
Setup time, SDI high before SCLK rising edge, tsu (see Figure 5) 10 ns
Hold time, SDI high after SCLK rising edge, th (see Figure 5) 10 ns
Case temperature, T

CC

BAT

IH

IL

C

4.5 5.0 5.5 V
8 24 V

0.85 V

CC

0 0.15 V

–40 125 °C

V

CC

CC

V
V

†

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

TPIC46L01, TPIC46L02, TPIC46L03

Gate disabled

See Figure 16

Gate disabled

See Figure 17
VGGate drive voltage

6-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER

SLIS055A – NOVEMBER 1996 - REVISED SEPTEMBER 1997

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

BAT

I

CC

V

(turnon)

V

(ovsd)

V

hys(ov)

V

(uvsd)

V

hys(uv)

I

O(H)

I

O(L)

V

(stb)

V

hys(stb)

V

D(open)

V

hys(open)

I

I(open)

I

I(PU)

I

I(PD)

V

I(hys)

V

O(SH)

V

O(SL)

I

OZ(SD)

V

O(CFLT)

V

I(COMP)

V

C

V

C

Supply current, V
Supply current, V

Turn-on voltage, logic operational, V
Over-battery-voltage shutdown

Over-battery-voltage reset hysteresis
Under-battery-voltage shutdown,

(TPIC46L01, L02 only)
Under-battery-voltage reset hysteresis,

(TPIC46L01, L02 only)

Maximum current output for drive terminals,
pullup

Maximum current output for drive terminals,
pulldown

Short-to-battery/shorted-load/open-load
detection voltage

Short-to-battery hysteresis 40 100 150 mV
Open-load off-state detection drain voltage

threshold
Open-load hysteresis 40 100 150 mV
Open-load off-state detection current 30 60 80 µA
Input pullup current (CS) VCC = 5 V, VIN = 0 10 µA
Input pulldown current VCC = 5 V, VIN = 5 V 10 µA
Input voltage hysteresis VCC = 5 V 0.6 0.85 1.1 V
High-level serial output voltage IO = 1 mA 0.8 V
Low-level serial output voltage IO = 1 mA 0.1 0.4 V
3-state current serial-data output VCC = 0 to 5.5 V -10 1 10 µA
Fault-interrupt output voltage IO = 1 mA 0.1 0.5 V
Fault-external reference voltage VCOMPEN = H 1 3 V
Output clamp voltage, (TPIC46L01, L02 only) dc < 1%, tw = 100 µs 47 55 63 V
Output clamp voltage, (TPIC46L03 only) dc < 1%, tw = 100 µs 47 60 V

BAT
CC

CC

All outputs off, V
All outputs off, V
V

= 5.5 V,

BAT

Check output functionality

,

,

8 V < V

5.5 V < V
V

OUT

V

OUT

VCOMPEN = L 1.1 1.25 1.4 V

VCOMPEN = L 1.1 1.25 1.4 V

< 24, IO = 100 µA 7 13.5 V

BAT

< 8 V, IO = 100 µA 5 7 V

BAT

= GND 0.5 1.2 2.5 mA

= 7 V 0.5 1.2 2.5 mA

= 12 V 300 500 700 µA

BAT

= 5.5 V 1 2.6 4.2 mA

BAT

2.6 3.5 4.4 V
32 34 36 V

0.5 1 1.5 V

4.1 4.8 5.4 V

100 200 300 mV

CC

V

6

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