Texas Instruments TPIC44L03DBR, TPIC44L03DB, TPIC44L02DB, TPIC44L01DB Datasheet

TPIC44L01, TPIC44L02, TPIC44L03

4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER

SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

4-Channel Serial-in Parallel-in Low-Side
Pre-FET Driver

D

Devices Are Cascadable

D

Internal 55-V Inductive Load Clamp and
V

GS

Protection Clamp for External Power

FETs

D

Independent Shorted-Load/Short-to­Battery Fault Detection on All Drain
Terminals

D

Independent OFF-State Open-Load Fault
Sense

D

Over-Battery-Voltage Lockout Protection
and Fault Reporting

D

Under-Battery Voltage Lockout Protection
for the TPIC44L01 and TPIC44L02

D

Asynchronous Open-Drain Fault Flag

D

Device Output Can be Wire ORed with
Multiple Devices

D

Fault Status Returned Through Serial
Output Terminal

D

Internal Global Power-On Reset of Device
and External RESET Terminal

D

High-Impedance CMOS-Compatible Inputs
With Hysteresis

D

TPIC44L01 and TPIC44L03 Disables the
Gate Output When a Shorted-Load Fault
Occurs

D

TPIC44L02 Transitions the Gate Output to a
Low-Duty-Cycle PWM Mode When a
Shorted-Load Fault Occurs

description

The TPIC44L01, TPIC44L02, and TPIC44L03 are
low-side predrivers that provide serial and parallel
input interfaces to control four external FET power
switches such as offered in the TI TPIC family of
power arrays. These devices are designed
primarily for low-frequency switching, inductive
load applications such as solenoids and relays.
Fault status for each channel is available in a
serial-data format. Each driver channel has
independent off-state open-load detection and
on-state shorted-load/short-to-battery detection.
Battery overvoltage and undervoltage detection
and shutdown is provided on the TPIC44L01/L02.
On the TPIC44L03 driver, only over-battery-volt­age shutdown is provided Each channel also
provides inductive-voltage-transient protection
for the external FET.

These devices provide control of output channels through a serial input interface or a parallel input interface.
A command to enable the output from either interface enables the respective channels gate output to the
external FET . The serial interface is recommended when the number of signals between the control device and
the predriver must be minimized and the speed of operation is not critical. In applications where the predriver
must respond very quickly or asynchronously, the parallel input interface is recommended.

For serial operation, the control device must transition CS

from high to low to activate the serial input interface.

When this occurs, SDO is enabled, fault data is latched into the serial interface, and the fault flag is refreshed.
Data is clocked into the serial registers on low-to-high transitions of SCLK through SDI. Each string of data must

consist of at least four-bits of data. In applications where multiple devices are cascaded together, the string of
data must consist of4 bits for each device. A high data bit turns the respective output channel on and a low data

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TI is a trademark of Texas Instruments Incorporated.

Copyright  1997, Texas Instruments Incorporated

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24
23
22
21
20
19
18
17
16
15
14
13

FL T

VCOMPEN

VCOMP

IN0
IN1
IN2
IN3

CS

SDO

SDI

SCLK

V

CC

V

BAT

N/C
RESET
DRAIN0
GATE0
DRAIN1
GATE1
GATE2
DRAIN2
GATE3
DRAIN3
GND

DB PACKAGE

(TOP VIEW)

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

TPIC44L01, TPIC44L02, TPIC44L03
4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER

SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

bit turns it off. Fault data for the device is clocked out of SDO as serial input data is clocked into the device. Fault
data consists of fault flags for shorted-load and open-load flags (bits 0–3) for each of the four output channels.
A high bit in the fault data indicates a fault and a low bit indicates that no fault is present for that channel. Fault
register bits are set or cleared asynchronously to reflect the current state of the hardware. A fault must be
present when CS

is transitioned from high to low to be captured and reported in the serial fault data. New faults

cannot be captured in the serial register when CS

is low. CS must be transitioned high after all of the serial data

has been clocked into the device. A low-to-high transition of CS

transfers the last four bits of serial data to the
output buffer puts SDO in a high-impedence state and clears and re-enables the fault register. The
TPIC44L01/L02/L03 was designed to allow the serial input interfaces of multiple devices to be cascaded
together to simplify the serial interface to the controller. Serial input data flows through the device and is
transferred out SDO following the fault data in cascaded configurations.

For parallel operation, data is transferred directly from the parallel input interface IN0-IN3 to the respective
GA TE(0–3) output asynchronously. SCLK or CS

is not required for parallel control. A 1 on the parallel input turns
the respective channel on, where a 0 turns it off. Note that either the serial input interface or the parallel input
interface can enable a channel. Under parallel operation, fault data must still be collected through the serial data
interface.

The predrivers monitor the drain voltage for each channel to detect shorted-load or open-load fault conditions
in the the on and off states respectively. These devices offer the option of using an internally generated
fault-reference voltage or an externally supplied fault-reference voltage through VCOMP for fault detection. The
internal fault reference is selected by connecting VCOMPEN

to GND and the external reference is selected by

connecting VCOMPEN

to V

CC

. The drain voltage is compared to the fault reference when the channel is turned
on to detect shorted-load conditions and when the channel is off to detect open-load conditions. When a shorted
fault occurs using the TPIC44L01 or the TPIC44L03, the channel is turned off and a fault flag is sent to the control
device as well as to the serial fault register bits. If a fault occurs while using the TPIC44L02, the channel
transitions into a low-duty-cycle, pulse-width-modulated (PWM) signal as long as the fault is present.
Shorted-load fault conditions must be present for at least the shorted-load deglitch time, t

(STBDG)

, to be flagged
as a fault. A fault flag is sent to the control device as well as the serial fault register bits. More detail on fault
detection operation is presented in the device operation section of this data sheet.

These devices provide protection from over-battery voltage and under-battery voltage conditions irrespective
of the state of the output channels. When the battery voltage is greater than the overvoltage threshold or less
than the undervoltage threshold, all channels are disabled and a fault flag is generated. Battery-voltage faults
are not reported in the serial fault data. The outputs return to normal operation once the battery-voltage fault
has been corrected. When an over-battery/under-battery voltage condition occurs, the device reports the
battery fault, but disables fault reporting for open- and shorted-load conditions. Fault reporting for open- and
shorted-load conditions are re-enabled after the battery fault condition has been corrected.

These devices provide inductive transient protection on all channels. The drain voltage is clamped to protect
the FET . The clamp voltage is defined by the sum of V

C

and turn-on voltage of the external FET. The predriver

also provides a gate-to-source voltage (V

GS)

clamp to protect the gate-source terminals of the power FET from

exceeding their rated voltages. An external active low RESET

is provided to clear all registers and flags in the

device. GATE(0–3) outputs are disabled after RESET

has been pulled low.

These devices provide pulldown resistors on all inputs except CS

and RESET. A pullup resistor is used on CS

and RESET.

TPIC44L01, TPIC44L02, TPIC44L03

4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER

SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

schematic diagram

Parallel Register

PREZ

D

Q

GND

Serial Register

Fault Logic

4

SDO

FLT

4

STB and Open-Load Fault

Protection

OSC

BIAS

V

bg

S

B

A

Gate

Drive Block

DRAIN 0
DRAIN 1
DRAIN 2
DRAIN 3

GATE 0
GATE 1
GATE 2
GATE 3

OVLO

†

UVLO

2

VCOMPEN

VCOMP

SDI

SCLK

CS

IN 0
IN 1

IN 2
IN 3

V

BAT

4

V

CC

RST

RST

RST

RST

V

CC

RST

RESET

†

OVLO not on TPIC44L03

TPIC44L01, TPIC44L02, TPIC44L03
4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER

SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

I/O

DESCRIPTION

CS 8 I Chip select. A high to low transition on CS enables SDO, latches fault data into the serial interface, and

refreshes FLT

. When CS is high, the fault registers can change fault status. On the falling edge of CS, fault data
is latched into the serial output register and transferred using SDO and SCLK. On a low to high transition of
CS,

serial data is latched in to the output control register.

DRAIN0 21

I

DRAIN1 19

FET drain inputs. DRAIN0 through DRAIN3 are used for both open-load and short-circuit fault detection at the

DRAIN2 16

g

drain of the external FETs. They are also used for inductive transient protection.

DRAIN3 14
FLT 1 I Fault flag. FLT is a logic level open-drain output that provides a real-time fault flag for shorted-load/

open-load/over-battery voltage/under-battery voltage faults. The device can be ORed with FLT

terminals on

other devices for interrupt handling. FLT

requires an external pullup resistor.

GATE0 20

O

GATE1 18

Gate drive output. GATE0 through GATE3 outputs are derived from the V

supply voltage. Internal clamps

GATE2 17

g

BAT

yg

prevent voltages on these nodes from exceeding the VGS rating on most FETs.

GATE3 15
GND 13 I Ground and substrate
IN0 4

I

IN1 5

Parallel gate driver. IN0 through IN3 are real-time controls for the gate predrive circuitry. They are CMOS

IN2 6

gg gyy

compatible with hysteresis.

IN3 7
RESET 22 I Reset. A high-to-low transition of RESET clears all registers and flags. Gate outputs turn off and the FLT flag

is cleared.

SCLK 11 I Serial clock. SCLK clocks the shift register. Serial data is clocked into SDI and serial fault data is clocked out

of SDO on the falling edge of the serial clock.

SDI 10 I Serial data input. Output control data is clocked into the serial register through SDI. A 1 on SDI commands a

particular gate output on and a 0 turns it off.

SDO 9 O Serial data output. SDO is a 3-state output that transfers fault data to the controlling device. It also passes serial

input data to the next stage for cascaded operation. SDO is taken to a high-impedance state when CS

is in a

high state.

V

BAT

24 I Battery supply voltage

V

CC

12 I Logic supply voltage

VCOMPEN 2 I Fault reference voltage select. VCOMPEN selects the internally generated fault reference voltage (0) or an

external fault reference (1) to be used in the shorted- and open-load fault detection circuitry.

VCOMP 3 I Fault reference voltage. VCOMP provides an external fault reference voltage for the shorted-load and

open-load fault detection circuitry .

TPIC44L01, TPIC44L02, TPIC44L03

4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER

SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

CC

(see Note 1) –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Battery supply voltage range, V

BAT

–0.3 V to 60 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range,V

I

(at any input) –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

O

(SDO and FLT) –0.3 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Drain-to-source voltage, V

DS

–0.3 V to 60 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage, V

O

–0.3 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating case temperature range, T

C

–40°C to + 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Thermal resistance, junction to ambient, R

θJA

135°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Maximum junction temperature, T

J

150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–40°C to + 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltage values are with respect to GND.

recommended operating conditions

MIN NOM MAX UNIT

Logic supply voltage, V

CC

4.5 5 5.5 V

Battery supply voltage, V

BAT

8 24 V

High-level input voltage, V

IH

0.85 V

CC

V

CC

V

Low-level input voltage, V

IL

0 0.15 V

CC

V
Setup time, SDI high before SCLK rising edge, tsu (see Figure 5) 10 ns
Hold time, SDI high after SCLK rising edge, th (see Figure 5) 10 ns
Case temperature, T

C

–40 125 °C

TPIC44L01, TPIC44L02, TPIC44L03
4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER

SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

BAT

Supply current, V

BAT

All outputs off, V

BAT

= 12 V 300 500 700 µA

I

CC

Supply current, V

CC

All outputs off, V

BAT

= 5.5 V 1 2.6 4.2 mA

V

(turnon)

Turn-on voltage, logic operational, V

CC

V

bat

= 5.5 V,

Check output functionality

2.6 3.5 4.4 V

V

(ovsd)

Over-battery-voltage shutdown

32 34 36 V

V

hys(ov)

Over-battery-voltage reset hysteresis

Gate disabled

,

See Figure 16

0.5 1 1.5 V

V

(uvsd)

Under-battery-voltage shutdown,
(TPIC44L01/L02 only)

4.1 4.8 5.4 V

V

hys(uv)

Under-battery-voltage reset hysteresis,
(TPIC44L01/L02 only)

Gate disabled

,

See Figure 17

100 200 300 mV

8 V < V

BAT

< 24, IO = 100 µA 7 13.5 V

VGGate drive voltage

5.5 V < V

BAT

< 8 V, IO = 100 µA 5 7 V

I

O(H)

Maximum current output for drive terminals,
pullup

V

OUT

= GND 0.5 1.2 2.5 mA

I

O(L)

Maximum current output for drive terminals,
pulldown

V

OUT

= 7 V 0.5 1.2 2.5 mA

V

(stb)

Short-to-battery/shorted-load/open-load
detection voltage

VCOMPEN = L 1.1 1.25 1.4 V

V

hys(stb)

Short-to-battery hysteresis 40 100 150 mV

V

D(open)

Open-load off-state detection voltage threshold VCOMPEN = L 1.1 1.25 1.4 V

V

hys(open)

Open-load hysteresis 40 100 150 mV

I

I(open)

Open-load off-state detection current 30 60 80 µA

I

I(PU)

Input pullup current (CS) VCC = 5 V, VIN = 0 10 µA

I

I(PD)

Input pulldown current VCC = 5 V, VIN = 5 V 10 µA

V

hys

Input voltage hysteresis VCC = 5 V 0.6 0.85 1.1 V

V

O(SH)

High-level serial output voltage IO = 1 mA 0.8 V

CC

V

V

O(SL)

Low-level serial output voltage IO = 1 mA 0.1 0.4 V

I

OZ(SD)

3-state current serial-data output VCC = 0 to 5.5V -10 1 10 µA

V

O(CFLT)

Fault-interrupt output voltage IO = 1 mA 0.1 0.5 V

V

I(COMP)

Fault-external reference voltage VCOMPEN = H 1 3 V

V

C

Output clamp voltage, (TPIC44L01/L02 only) dc < 1%, tw = 100 µs 47 55 63 V

V

C

Output clamp voltage, (TPIC44L03 only) dc < 1%, tw = 100 µs 47 53.5 60 V

TPIC44L01, TPIC44L02, TPIC44L03

4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER

SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

switching characteristics, V

CC

= 5 V, V

bat

= 12 V, T

C

= 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

(STBFM)

Short-to-battery/shorted-load/open-load
fault mask time

See Figures 14 and 15 60 µs

t

(STBDG)

Short-to-battery/shorted-load deglitch time See Figure 14 8 µs

t

PLH

Propagation turn-on delay time, CS or
IN0-IN3 to GATE0-GATE3

C

(gate)

= 400 pF, See Figure 1 4 µs

t

PHL

Propagation turn-off delay time, CS or
IN0-IN3 to GATE0-GATE3

C

(gate)

= 400 pF, See Figure 2 3.5 µs

t

r1

Rise time GATE0–GATE3 C

(gate)

= 400 pF, See Figure 3 3.5 µs

t

f1

Fall time, GATE0–GATE3 C

(gate)

= 400 pF, See Figure 4 3 µs

f

(SCLK)

Serial clock frequency 10 MHz

t

rf(SB)

Refresh time, short-to-battery TPIC46L01 only, See Figure 14 10 ms

t

w

Refresh pulse width, short-to-battery TPIC46L01 only, See Figure 14 68 µs

t

d1

Setup time, CS↓ to ↑SCLK See Figure 5 10 ns

t

pd1

Propagation delay time, CS↓ to SDO valid

RL = 10 kΩ,

See Figure 6

CL = 200 pF,

40 ns

t

pd2

Propagation delay time, SCLK↓ to SDO
valid

See Figure 6 20 ns

t

pd3

Propagation delay time, CS↑ to SDO
3-state

RL = 10 kΩ,

See Figure 7

CL = 50 pF,

2 µs

t

r2

Rise time, SDO 3-state to SDO valid

RL = 10 kΩ to GND,
CL = 200 pF,

Over-battery fault,
See Figure 8

30 ns

t

f2

Fall time, SDO 3-state to SDO valid

RL = 10 kΩ to VCC,

CL = 200 pF,

No faults,
See Figure 9

20 ns

t

r3

Rise time, FLT

RL = 10 kΩ,

See Figure 10

CL = 50 pF,

1.2 µs

t

f3

Fall time, FLT

RL = 10 kΩ,

See Figure 11

CL = 50 pF,

15 ns

Figure 1

t

PLH

50%

90%

CS

or IN0–IN3

GATE0–GATE3

Figure 2

t

PHL

50%

50%

10%

CS

GATE0–GATE3

IN0–IN3

or

Figure 3

90%

10%

t

r1

GATE0–GATE3

Figure 4

GATE0–GATE3

t

f1

90%

10%

TPIC44L01, TPIC44L02, TPIC44L03
4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER

SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Figure 5

t

d1

SCLK

CS

SDI

t

h

t

su

Figure 6

t

pd2

SCLK

CS

t

pd1

3-StateSDO

Figure 7

t

pd3

CS

SDO

50%

3-State

Figure 8

3-STATE

90%
10%

t

r2

SDO

Figure 9

3-STATE

90%
10%

t

f2

SDO

Figure 10

FLT

t

r3

90%

10%

90%

10%

t

f3

Figure 11

FLT

TPIC44L01, TPIC44L02, TPIC44L03

4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER

SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

serial data operation

The TPIC44L01, TPIC44L02, and TPIC44L03 offer serial input interface to the microcontroller to transfer control
data to the predriver and fault data back to the controller. The serial input interface consists of:

• SCLK – Serial clock

• CS – Chip select

• SDI – Serial data input

• SDO – Serial data output

Serial data is shifted into the least significant bit (LSB) of the SDI shift register on the rising edge of the first SCLK
after CS

has transitioned from 1 to 0. Four clock cycles are required to shift the first bit from the LSB to the most

significant bit (MSB) of the shift register. Four clock cycles must occur before CS

transitions high for proper
control of the outputs. Less than four clock cycles result in fault data being latched into the output control buffer .
Eight bits of data can be shifted into the device, but the first 4 bits shifted out are always the fault data and the
last 4 bits shifted in are always the output control data. A low-to-high transition on CS

latches the contents of
the serial shift register into the output control register. A logic 0 input to SDI turns the corresponding parallel
output off and a logic 1 input turns the output on (see Figure 12).

GATE3 ON

GATE2 ON
GATE1 OFF
GATE0 OFF

1234

Present Output Data New Data

3-State FLT3 FLT2 FLT1 FLT0 IN3 3-State

SCLK

CS

SDI

New Data

Output Control

Register Data

SDO

(a) 4-Bit Serial Word Example

Figure 12

TPIC44L01, TPIC44L02, TPIC44L03
4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER

SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

GATE3 ON

GATE2 ON
GATE1 OFF
GATE0 OFF

1234

Present Output Data

New Data

FLT0 NA NA NA NA IN3 3-State

SCLK

CS

Output Control

Register Data

SDO

5678

Don’t Care

3-State FLT3 FLT2 FLT1

New Data

SDI

(b) 8-Bit Serial Word Example (Single Predriver)

1234

FLT4 FLT3 FLT2 FLT1 FLT0 IN7 3-State

SCLK

CS

SDO

5678

3-State FLT7 FLT6 FLT5

New Data

(c) 8-Bit Serial Word Example (Cascade: Two Predrivers)

IN 4 IN 3 IN 2 IN 1 IN 0 NA

SDI

IN 7 IN 6 IN 5

GATE7–GATE4 (2nd stage)

GATE3–GATE0 (1st stage)

Figure 12 (continued)

TPIC44L01, TPIC44L02, TPIC44L03

4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER

SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997

11

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

serial data operation (continued)

Data is shifted out of SDO on the falling edge of SCLK. The MSB of fault data is available after CS is transitioned
low. The remaining 3 bits of fault data are shifted out in the following three clock cycles. Fault data is latched
into the serial register when CS

is transitioned low. A fault must be present on the high to low transition of CS
to be captured by the device. The CS input must be transitioned to a high state after the last bit of serial data
has been clocked into the device. The rising edge of CS

inhibits SDI, puts SDO into a high-impedance state,
latches the 4 bits of serial data into the output control register, and clears and re-enable the serial fault registers
(see Figure 13). When a shorted-load condition occurs with the TPIC44L01 or TPIC44L03, then the controller
must disable and re-enable the channel to clear the fault register and FL T

. The TPIC44L02 automatically retries

the output and the fault clears after the fault condition has been corrected.

1234

3-State FLT3 FLT2 FLT1 FLT0 IN3 3-State

SCLK

CS

SDO

Figure 13

parallel input data operation

In addition to the serial interface, the TPIC44L01, TPIC44L02, and TPIC44L03 also provides a parallel interface
to the microcontroller. The output turns on when either the parallel or the serial interface commands it to turn
on. The parallel data terminals are real-time control inputs for the output drivers. SCLK and CS

are not required
to transfer parallel input data to the output buffer . Fault data must be read over the serial data bus as described
in the serial data operation section of this data sheet. The parallel input must be transitioned low and then high
to clear and re-enable a gate output after it has been disabled due to a shorted-load fault condition.

TPIC44L01, TPIC44L02, TPIC44L03
4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER

SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

chipset performance under fault conditions

The TPIC44L01, TPIC44L02, TPIC44L03, and power FET arrays are designed for normal operation over a
battery-voltage range of 8 V to 24 V with load-fault detection from 4.8 V to 34 V . The TPIC44L01, TPIC44L02,
and TPIC44L03 offer on-board fault detection to handle a variety of faults that may occur within a system. The
circuits primary function is to prevent damage to the load and the power FETs in the event that a fault occurs.
Note that unused DRAIN0-DRAIN3 inputs must be connected to V

BAT

through a pullup resistor to prevent false
reporting of open-load fault conditions. The circuitry detects the fault, shuts off the output to the FET , and reports
the fault to the microcontroller. The primary faults under consideration are:

1. Shorted-load

2. Open-load

3. Over-battery voltage shutdown

4. Under-battery voltage shutdown (TPIC44L01 and TPIC44L02 only)

NOTE:

An undervoltage fault may be detected when V

CC

and V

BAT

are applied to the device. The controller

should initialize the fault register after power up to clear any false fault reports.

shorted-load fault condition

The TPIC44L01, TPIC44L02, and TPIC44L03 monitor the drain voltage of each channel to detect shorted-load
conditions. The onboard deglitch timer starts running when the gate output to the power FET transitions from
the off state to the on state. The timer provides a 60-µs deglitch time, t

(STBFM)

, to allow the drain voltage to
stabilize after the power FET has been turned on. The deglitch time is only enabled for the first 60-µs after the
FET has been turned on. After the deglitch delay time, the drain voltage is checked to verify that it is less than
the fault reference voltage. When it is greater than the reference voltage for at least the short-to-battery deglitch
time, t

(STBDG)

, FL T flags the microcontroller that a fault condition exists and the gate output is automatically shut

off (TPIC44L01 and TPIC44L03) until the error condition has been corrected.
An overheating condition on the FET occurs when the controller continually tries to re-enable the output under

shorted-load fault conditions. When a shorted-load fault is detected using the TPIC44L02, the gate output is
transitioned into a low-duty-cycle, PWM signal to to protect the FET from overheating. The PWM rate is defined
as t

(SB)

and the pulse width is defined as tw. The gate output remains in this state until the fault has been

corrected or until the controller disables the gate output.
The microcontroller can read the serial port on the predriver to isolate which channel reported the fault condition.

Fault bits 0-3 distinguish faults for each of the output channels. When a shorted-load condition occurs with the
TPIC44L01 or TPIC44L03, the controller must disable and re-enable the channel to clear the fault register and
FL T

. The TPIC44L02 automatically retries the output and the fault clears after the fault condition has been
corrected. Figure 14 illustrates operation after a gate output has been turned on. The gate to the power FET
is turned on and the deglitch timer starts running. Under normal operation T1 turns on and the drain operates
below the reference point set at U1. The output of U1 is low and a fault condition is not flagged.

TPIC44L01, TPIC44L02, TPIC44L03

4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER

SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997

13

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

t(

STBFM)

t(

STBFM)

Glitches

Glitches

t

w

t

(SB)

GATE0–
GATE3

Input

DRAIN0–
DRAIN3

FLT

NORMAL

SHORTED-LOAD TPIC44L02

_

+

N-Channel

Load

V

BAT

T1

External TPIC44L01/L02

1.25 V

Deglitch

FLT

Input From

TPIC44L01/L02

GATE0–
GATE3

Glitches

t

(STBDG)

Input

DRAIN0–
DRAIN3

FLT

GATE0–
GATE3

Input

DRAIN0–
DRAIN3

FLT

GATE0–
GATE3

SHORTED-LOAD TPIC44L01 and TPIC44L03

U1

t

(STBDG)

t(

STBFM)

Figure 14

TPIC44L01, TPIC44L02, TPIC44L03
4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER

SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

open load

The TPIC44L01, TPIC44L02, and TPIC44L03 monitor the drain of each power FET for open circuit conditions
that may exist. The 60-µA current source is provided to monitor open load fault conditions. Open-load faults are
only detected when the power FET is turned off. When load impedance is open or substantially high, the 60-µA
current source has adequate drive to pull the drain of T1 below the fault reference threshold on the detection
circuit. Unused DRAIN0–DRAIN3 inputs must be connected to V

BAT

through a pull-up resistor to prevent false
reporting of open-load fault conditions. The on-board deglitch timer starts running when the TPIC44L01,
TPIC44L02, and TPIC44L03 gate output to the power FET transitions to the off state. The timer provides a 60-µs
deglitch time, t

(STBFM)

to allow the drain voltage to stabilize after the power FET has been turned off. The deglitch
time is only enabled for the first 60-µs after the FET has been turned off. After the deglitch delay time, the drain
is checked to verify that it is greater than the fault reference voltage. When it is less than the reference voltage,
a fault is flagged to the microcontroller through FL T

that an open-load fault condition exists. The microcontroller
can then read the serial port on the TPIC44L01, TPIC44L02, and TPIC44L03 to isolate which channel reported
the fault condition. Fault bits 0–3 distinguish faults for each of the output channels. Figure 15 illustrates the
operation of the open-load detection circuit. This feature provides useful information to the microcontroller to
isolate system failures and warn the operator that a problem exists. Examples of such applications would be
a warning that a light bulb filament may be open, solenoid coils may be open, etc.

NORMAL

_

+

N-Channel

Load

V

BAT

T1

External TPIC44L01/L02/L03

1.25 V

Deglitch

FLT

Input From

TPIC44L01/L02/L03

60 µA

U1

t

(STBFM)

Glitches

Input

DRAIN0–
DRAIN3

FLT

OPEN-LOAD

NORMAL

GATE0–
GATE3

Input

DRAIN0–
DRAIN3

FLT

GATE0–
GATE3

t

(STBFM)

Figure 15

TPIC44L01, TPIC44L02, TPIC44L03

4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER

SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997

15

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

over-battery-voltage shutdown

The TPIC44L01,TPIC44L02, and TPIC44L03 monitor the battery voltage to prevent the power FET s turning on
in the event that the battery voltage is too high. This condition may occur due to voltage transients resulting from
a loose battery connection. The TPIC44L01, TPIC44L02, and TPIC44L03 turns the power FET off when the
battery voltage is above 34 volts to prevent possible damage to the load and the FET. GA TE(0–3) output goes
back to normal operation after the overvoltage condition has been corrected. An over-battery-voltage fault is
flagged to the controller through FL T

. The over-battery-voltage fault is not reported in the serial fault word. When
an overvoltage condition occurs, the device reports the battery fault, but disables fault reporting for open and
shorted-load conditions. Fault reporting for open and shorted-load conditions are re-enabled after the battery
fault condition has been corrected. When the fault condition is removed before the CS

signal transitions low,
the fault condition is not captured in the serial fault register. The fault flag resets on a high-to-low transition of
CS

provided no other faults are present in the device. Figure 16 illustrates the operation of the

over-battery-voltage detection circuit.

_

+

V

BAT

34 V

34 V

33 V12 V

V

BAT

GATE0–GATE3

Output Disable

U1

Figure 16

TPIC44L01, TPIC44L02, TPIC44L03
4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER

SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997

16

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

under-battery-voltage shutdown (TPIC44L01 and TPIC44L02 only

)

The TPIC44L01 and TPIC44L02 monitor the battery voltage to prevent the power FETs from being turned on
in the event that the battery voltage is too low. When the battery voltage is below 4.8 volts, then GA TE0–GA TE3
may not provide sufficient gate voltage to the power FETs to minimize the on-resistance that could result in a
thermal stress on the FET . The output goes back to normal operation after the undervoltage condition has been
corrected. An under-battery-voltage fault is flagged to the controller through FL T

. The under-battery voltage fault
is not reported in the serial fault word. When an under-battery-voltage condition occurs, the device reports the
battery fault but disables fault reporting for open- and shorted-load conditions. When the fault condition is
removed before the CS

signal transitions low, the fault condition is not captured in the serial fault register. The

fault flag resets on a high-to-low transition of CS

provided no other faults are present in the device. Figure 17

illustrates the operation of the under-battery voltage-detection circuit.

_
+

V

BAT

4.8 V

4.8 V

5 V

12 V

V

BAT

GATE0–GATE3

Output Disable

U1

Figure 17

TPIC44L01, TPIC44L02, TPIC44L03

4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER

SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997

17

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

inductive voltage transients

A typical application for the predriver/power FET circuit is to switch inductive loads. When an inductive load is
switched off, a large voltage spike can occur . These spikes can exceed the maximum V

DS

rating for the external
FET and damage the device when the proper protection is not in place. The FET can be protected from these
transients through a variety of methods using external components. The TPIC44L01, TPIC44L02, and
TPIC44L03 offer that protection in the form of a zener diode stack connected between the DRAIN input and
GATE output (seeFigure 18). Zener diode Z1 turns the FET on to dissipate the transient energy. GATE diode
Z2 is provided to prevent the gate voltage from exceeding 13 volts during normal operation and transient
protection.

DRAIN

GATE

LOAD

55 V

Z1

Z2

13 V

Power FET

V

BAT

TPIC44L01/L02/L03 External

T1

Figure 18

TPIC44L01, TPIC44L02, TPIC44L03
4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER

SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997

18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PRINCIPLES OF OPERATION

external fault reference input

The TPIC44L01, TPIC44L02, and TPIC44L03 compare each channel drain voltage to a fault reference to detect
shorted-load and open-load conditions. The user has the option of using the internally generated 1.25-V fault
reference or providing an external reference voltage through VCOMP . The internal reference is selected by con­necting VCOMPEN to GND and VCOMP is selected by connecting VCOMPEN to V

CC

(see Figure 19). Proper
layout techniques should be used in the grounding network for the VCOMP circuit on the TPIC44L01,
TPIC44L02, and TPIC44L03. The ground for the predriver and VCOMP network should be connected to a Kel­vin ground if available; otherwise, they should make single-point contact back to the power ground of the FET
array. Improper grounding techniques can result in inaccuracies in detecting faults.

_

+

_

+

U1

A
M
U
X

1.25 V

DRAIN3

DRAIN0

VCOMP

VCOMPEN

Deglitch

FLT

External TPIC44L01/L02/L03

VCOMPEN

1.25 V

VCOMP

0
1

Figure 19

TPIC44L01, TPIC44L02, TPIC44L03

4-CHANNEL SERIAL AND PARALLEL LOW-SIDE PRE-FET DRIVER

SLIS062A – NOVEMBER 1996 – REVISED SEPTEMBER 1997

19

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

4040065 /C 10/95

28 TERMINAL SHOWN

Gage Plane

8,20
7,40

0,15 NOM

0,63

1,03

0,25

38

12,90

12,30

28

10,50

24

8,50

Seating Plane

9,907,90

30

10,50

9,90

0,38

5,60
5,00

15

0,22

14

A

28

1

2016

6,50

6,50

14

0,05 MIN

5,905,90

DIM

A MAX

A MIN

PINS **

2,00 MAX

6,90

7,50

0,65

M

0,15

0°–8°

0,10

3,30

8

2,70

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150

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Copyright  1998, Texas Instruments Incorporated