Texas Instruments TPIC2101N, TPIC2101D Datasheet

TPIC2101

DC BRUSH MOTOR CONTROLLER

SLIS060 – OCTOBER 1995

D

0 V to16 V, 50 mA Max PWM Gate Drive
Output

D

Dual Speed Command Input Capability

D

Effective Motor Voltage Adjustment

D

100% Duty Cycle Capability

D

Low Current (<200 µA) Sleep State

D

Built-in Soft Start

D

Over/Under V oltage Protection

D

Over Current Protection of External
FET/IGBT

D or N PACKAGE

V5P5

MAN

AUTO

SPEED

ROSC
COSC

INT

(TOP VIEW)

1

14

2

13

3

12

4

11

5

10
6
7

9
8

CCS
AREF
V

bat

GD
GND
ILS
ILR

description

The TPIC2101 is a monolithic integrated control circuit designed for direct current (dc) brush motor control that
generates a user-adjustable, fixed-frequency, variable duty cycle, pulse width modulated (PWM) signal
primarily to control rotor speed of a permanent magnet dc motor. The TPIC2101 can also be used to control
power to other loads such as solenoids and incandescent bulbs. This device drives the gate of an external, low
side NMOS power transistor to provide PWM controlled power to a motor or other loads. Inductive current from
motor or solenoid loads during PWM off-time is recirculated through an external diode.

The TPIC2101 accepts a 0% to 100% PWM signal (auto mode) or a 0 V to 2.2 V differential voltage (manual
mode), and internally engages the correct operating mode to accept the input type.

The device operates in a sleep state, a run state, or a fault state. In the sleep state the gate-drive (GD) terminal
is held low and the overall current draw is less than 200 µA. The normal operating mode of the device is in the
run state and is initiated by any speed command. When the device detects an overvoltage or current fault, it
enters the fault state.

The TPIC2101 is offered in a 14-terminal plastic DIP (N) package, and a SOIC (D) package, and is characterized
for operation over the operating free-air temperature range of –40°C to 105°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

Copyright  1995, Texas Instruments Incorporated

1

TPIC2101
DC BRUSH MOTOR CONTROLLER

SLIS060 – OCTOBER 1995

functional block diagram

V5P5

Sleep

AUTO and MAN

Logic

Sleep AREF 20 kHz

Oscillator and
Voltage Ramp

Waveform Generator

MAN

AUTO

CCS

V5P5

2

AUTO and MAN

Input Config

3

I

CCS

CCS

14

Buffer

1

V

bat

Bandgap

Buffer

Sleep

AREF

V5P5

V

bat
+
_

MDET

V

bat

+
_

V5P5

V

bat

2×

Bandgap

and IBIAS

ADET

UVSD

20 kHz

20 kHz

Source

Select

Sleep

SPEED INT

47

V7

AREF

_
+

V

trip

V

ramp

V

bat/4

AREF

PWMout

V

bat

Switched

V

bat

AREF

20 kHz

ILimit
Logic

IDET GDDIS

Sleep OVSD

V

bat/8

V5P5

GD

Logic

AREF

OVSD

IFLT

UVSD

AREF

V5P5

V5P5

UVSD

Gate

Drive

8

ILR

9

ILS

12

V

bat

11

GD

10

GND

13 5 6

AREF ROSC COSC

NOTE A: For correct operation, no terminal may be taken below GND.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

I/O

DESCRIPTION

DESCRIPTION

TPIC2101

DC BRUSH MOTOR CONTROLLER

SLIS060 – OCTOBER 1995

Terminal Functions

TERMINAL

NAME NO.

V5P5 1 O 5.5 V supply voltage. V5P5 is a regulated voltage supply from V

MAN 2 I Manual control input. MAN is an active high (greater than 5.5 V asserts the manual mode) input that serves

AUTO 3 I PWM control input. AUTO is an active low input that remains active if pulsed every 2048 counts of the

SPEED 4 O Integrator output. SPEED is an integrator output with a required minimum resistance between SPEED and

ROSC 5 O Oscillator resistor output. ROSC has an external resistor connected to ground which determines the

COSC 6 O Oscillator capacitor output. COSC has an external capacitor connected to ground which determines (with

INT 7 I Integrator input. INT is an input from an integrator that requires a 4.7 µF capacitor and a 20 k minimum

ILR 8 I Current limit reference. ILR is an input from a resistor divider off AREF.
ILS 9 I Current limit sense. ILS senses drain voltage of external FET. ILS trips within ±10 mV of ILR.
GND 10 Ground terminal
GD 11 O Gate drive output. GD, PWM output, 0-V

V

bat

AREF 13 O 5.5 V reference voltage. AREF is a 5.5 V reference voltage switched from V5P5 during the run state. AREF

CCS 14 Constant current sink. I

12 I Positive power input.

run state. This requires a 4.7 µF tantalum capacitor from V5P5 to GND for stability.

as a positive differential input (0-2.3 V full range) for the manual mode. In man mode, I

oscillator frequency. It also serves as a negative differential input for the manual mode. In auto mode, I
is approx. 13×Iccs pullup, I

INT terminals of 20 kΩ (typically 1 second RC time constant, or as required for soft start).

constant charging current of COSC. The IC forces a voltage of V

ROSC) switching frequency. f(osc) = 2/(ROSC×COSC)

resistance between the SPEED and INT terminals.

FET .

is used as a reference for ILR in current limit detection and is capable of sourcing 2 mA of current.

is approx. 20×I

auto

equals AREF/(2×R

CCS

pulldown in man mode.

ccs

voltage, provides a 0-V

bat

). Requires an external resistor.

ccs

, internally switched to AREF during the

bat

is approx. 20×I

man

/4 in run state.

bat

PWM output pre-drive for an external

bat

ccs

auto

.

recommended external components for auto and manual modes (see Figures 2 and 4)

TERMINAL

NAME NO.

V5P5 1 Capacitor – 4.7 µF tantalum
MAN 2 Capacitor – 0.1 µF
MAN 2 Resistor – 499 Ω, 1%, 100 ppm
AUTO 3 Capacitor – 0.47 µF
AUTO 3 Resistor – 499 Ω, 1%, 100 ppm
SPEED 4 Resistor – 100 kΩ, 1%, 100 ppm to INT terminal, (minimum 20 kΩ)
ROSC 5 Resistor – 45.3 kΩ
COSC 6 Capacitor – 2200 pF
INT 7 Capacitor – 4.7 µF
CCS 14 Resistor – 27.4 kΩ, 1%, 100 ppm

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

3

TPIC2101
DC BRUSH MOTOR CONTROLLER

SLIS060 – OCTOBER 1995

detailed description

The TPIC2101 is an integrated circuit that generates a fixed frequency , variable duty cycle PWM signal to control
the rotor speed of a permanent-magnet dc motor. This section provides a functional description of the device.

dual command speed input capability

The TPIC2101 is user configurable to either auto or manual mode, and can sense either configuration internal
to the IC. In automatic mode, the speed-command-signal is an open-collector PWM signal on the AUTO
terminal, and the MAN terminal is floating. In manual mode, the speed-command-signal is a variable resistance
across the AUTO and MAN terminals with the MAN terminal connected to V

sleep, run, and fault states

The TPIC2101 operates in a sleep state, a run state, or a fault state. In the auto mode, a zero-speed input
initiates the sleep state. In the manual mode, an open-circuit at the AUTO and MAN terminals initiates the sleep
state. The device will also be in the sleep state during fault conditions. In the sleep state, the gate drive terminal
(GD) is held low and the overall current draw is less than 200 µA. Any speed command initiates the run state,
which is the normal operating state of the device. The fault state is entered only when the device detects an
overvoltage or current fault. Fault state is exited either by removal of the overvoltage condition (exiting to run
state) or by resetting a current fault by entering the sleep state.

speed command adjustment

bat

.

The device adjusts the GD terminal PWM signal with changes in V

to keep the effective motor voltage

bat

constant. The effective motor voltage is defined to be the product of the GD terminal PWM rate and the voltage
of V

. Figure 1 shows motor voltage as a function of input speed command in the automatic mode for various

bat

battery voltages. PWM

is described as the duty cycle of the PWM signal at the AUTO terminal.

in

16

14

12

V

= 12

bat

10

8

6

Motor Voltage – V

4

2

0

V

= 8

bat

0204060

PWMin– Incoming Pulse Width Modulation – %

V

= 16

bat

80 100

Figure 1. Motor Voltage vs. Incoming PWM for Various Battery Voltages

over/under voltage protection

The IC enters the fault state if V
below the under-voltage shutdown (V

rises above over-voltage shutdown (V

bat

typically equals 7.5 volts) the IC enters sleep state. Hysteresis assures

UV

that the device will not toggle into and out of sleep state or fault condition.

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

typically equals 18.5 V). If V

OV

bat

falls

DC BRUSH MOTOR CONTROLLER

SLIS060 – OCTOBER 1995

current limit protection

Current through the motor is limited by lowering the GD terminal PWM when a high current situation occurs.
If the condition persists, the device shuts off the gate drive (GD terminal) until the circuit is reset externally by
entering the sleep state.

theory of operation

This section explains the normal circuit operation for the automatic and manual states.

power supply and oscillator

TPIC2101

Positive voltage is supplied to the integrated circuit on the V
steps down the V

supply to the regulated 5.5 V supply at the V5P5 terminal. AREF is shorted to V5P5 in run

bat

terminal, ground is the GND terminal. The IC

bat

state and disconnected when the IC is in sleep state. Two terminal connections (COSC and ROSC) are provided
to control an internal oscillator. The oscillator freq, f

f

(osc)

+

ROSC COSC

2

, is defined by the following equation:

(osc)

Nominal oscillator frequency is 20-kHz based on the recommended components.

automatic mode signal decoding

In automatic state, a high-to-low signal transition on the AUTO terminal (open collector) will wake the device
from the sleep state into the run state. The speed command information is contained in the duty cycle of a 100 Hz
PWM signal on the same terminal. The speed information is inverted, i.e. a signal that is 10% high commands
a faster speed than a 20% high signal. In automatic mode the MAN terminal is floating. The device is capable
of rejecting ± 2 V of ground offset V

between the open-collector switching transistor and the GND terminal

IO

without affecting the output duty cycle. Two terminals are provided for an RC integrator (SPEED and INT) to
average the incoming PWM signal for use as a PWM comparator input. Figure 2 illustrates the automatic state
connections.

No Connection

V

IO

499 Ω

499 Ω

2

3

I = 100 µA

MAN

TPIC2101

AUTO

CCS SPEED INT

14 2.75 V 4 7

20 kΩ min

27.4 kΩ

4.7 µF

Figure 2. Automatic Mode Connections

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

5

TPIC2101
DC BRUSH MOTOR CONTROLLER

SLIS060 – OCTOBER 1995

automatic mode signal decoding (continued)

The device enters the sleep state if the PWM signal on the AUTO terminal is absent (the AUTO terminal remains
high or low) for 2048 clock cycles of the 20 KHz oscillator. An internal 1 mA pull-up resistor is provided for the
AUTO terminal when in the auto mode. This pull-up resistor is not present in the manual mode or during sleep
state.

The device adjusts the output PWM duty cycle to keep the effective motor voltage constant with changing battery
voltages (V

) as per the equation:

bat

PWM

(2.88)13.12(1*Input Duty Cycle))

+

out

V

bat

100%

Figure 3 illustrates this transfer curve with various battery voltages.

100

V

= 12

90
80

70

60
50

– Output PWM – %

40

out

30

PWM

20
10

0

0 102030405060

V

= 16

bat

PWMin – Incoming Pulse Width Modulation – %

bat

V

bat

70 80 90 100

Figure 3. Output PWM vs. Incoming PWM for Various Battery Voltages

= 8

The allowable automatic mode PWM

variation is ± 7% over all operating conditions as indicated in the AC

out

characteristics Table.

manual mode speed signal decoding

In manual mode, a high input (>5.5V) on the MAN terminal changes the state of the device from sleep to run.
While in the run state the device senses the resistance between the MAN and AUTO terminals by turning on
a 2 mA current sink to each terminal. The MAN and AUTO current sinks are multiplied 20 X from the CCS current.
This 2 mA current sink creates a 1 V drop across each 0.5 kΩ resistor and a 0 to 2.2 V differential across the
0 to 1 kΩ potentiometer (and thus across the 2 terminals). The SPEED and INT terminals should be utilized as
in the proceeding section as a low-pass filter. When the connection to the MAN terminal is opened, the device
enters the sleep state. In addition, the device is capable of rejecting up to 2.2 V of source voltage offset (V
as indicated in Figure 4.

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

IO

),