TPIC1505
QUAD AND HEX POWER DMOS ARRAY
SLIS058 – JUNE 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Low r
DS(on)
:
0.25 Ω Typ (Full H-Bridge)
0.35 Ω Typ (Triple Half H-Bridge)
D
Pulsed Current:
6 A Per Channel (Full H-Bridge)
4 A Per Channel (Triple Half H-Bridge)
D
Matched Sense Transistor for Class A-B
Linear Operation
D
Fast Commutation Speed
description
The TPIC1505 is a monolithic power array that
consists of ten electrically isolated N-channel
enhancement-mode power DMOS transistors,
four of which are configured as a full H-bridge and
six as a triple half H-bridge. The lower stage of the
full H-bridge features an integrated sense FET to
allow biasing of the bridge in class A-B operation.
The TPIC1505 is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for operation
over the case temperature range of –40°C to 125°C.
schematic
Q4B
GATE1A
23
OUTPUT1
1
GATE1B
3
Q2A
15
Q2B
13
11
D1
D2
GATE3A
24
OUTPUT3
6
GATE3B
4
D3
GATE4A
Q4A
OUTPUT4
GATE4B
10
GATE2A
OUTPUT2
GATE2B
Q3B
Q3A
21 16
Q1B
Q1A
GATE5A
Q5A
17
OUTPUT5
GATE5B
18, 20
7
5, 9
GND
SOURCE
V
DD1
V
DD2
V
DD3
SENSE
14
Q2C
2
GATE2C
6 V
22
19 8
Q5B
12
NOTES: A. Pins 5 and 9 must be externally connected.
B. Pins 18 and 20 must be externally connected.
C. No output may be taken greater than 0.5 V below GND.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OUTPUT1
GATE2C
GATE1B
GATE3B
GND
OUTPUT3
SOURCE
OUTPUT5
GND
GATE4B
GATE2B
GATE5B
GATE3A
GATE1A
GATE4A
V
DD1
V
DD3
OUTPUT4
V
DD3
GATE5A
V
DD2
GATE2A
SENSE
OUTPUT2
DW PACKAGE
(TOP VIEW)
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
TPIC1505
QUAD AND HEX POWER DMOS ARRAY
SLIS058 – JUNE 1996
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings, TC = 25°C (unless otherwise noted)
†
Supply-to-GND voltage 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Source-to-GND voltage (Q3A, Q4A, Q5A) 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output-to-GND voltage 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sense-to-GND voltage 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gate-to-source voltage range, V
GS
(Q1A, Q1B, Q2A, Q2B, Q3A, Q3B,
Q4A, Q4B, Q5A, Q5B) –0.5 V to 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gate-to-source voltage, V
GS
(Q2C) –0.7 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous gate-to-source zener-diode current (Q2C) ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed gate-to-source zener-diode current (Q2C) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous drain current, each output (Q1A, Q1B, Q2A, Q2B) 1.5 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous drain current, each output (Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) 1 A. . . . . . . . . . . . . . . . . . . . . . . . .
Continuous drain current (Q2C) 5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous source-to-drain diode current (Q1A, Q1B, Q2A, Q2B) 1.5 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous source-to-drain diode current (Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) 1 A. . . . . . . . . . . . . . . . . . . . . .
Continuous source-to-drain diode current (Q2C) 5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed drain current, each output, I
max
(Q1A, Q1B, Q2A, Q2B) (see Note 1 and Figure 24) 6 A. . . . . . . . .
Pulsed drain current, each output, I
max
(Q3A, Q3B, Q4A, Q4B, Q5A, Q5B)
(see Note 1 and Figure 25) 4 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed drain current, I
max
(Q2C) (see Note 1) 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation, T
C
= 70°C (see Note 2 and Figures 24 and 25) 2.86 W. . . . . . . . . . . . .
Operating virtual junction temperature range, T
J
–40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating case temperature range, T
C
–40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Pulse duration = 10 ms, duty cycle = 2%
2. Package is mounted in intimate contact with infinite heat sink.
TPIC1505
QUAD AND HEX POWER DMOS ARRAY
SLIS058 – JUNE 1996
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, Q1A, Q1B, Q2A, Q2B, TC = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
(BR)DSX
Drain-to-source breakdown voltage ID = 250 µA, VGS = 0 20 V
V
GS(th)
Gate-to-source threshold voltage
ID = 1 mA,
See Figure 5
VDS = V
GS,
1.5 1.9 2.2 V
V
GS(th)match
Gate-to-source threshold voltage matching ID = 1 mA, VDS = V
GS
40 mV
V
(BR)
Reverse drain-to-GND breakdown voltage
Drain-to-GND current = 250 µA
(D1, D2)
20 V
V
(BR)GS
Gate-to-source breakdown voltage, Q2C IGS = 100 µA 6 V
V
(BR)SG
Source-to-gate breakdown voltage, Q2C ISG = 100 µA 0.5 V
V
(DS)on
Drain-to-source on-state voltage
ID = 1.5 A, VGS = 10 V,
See Notes 3 and 4
0.38 0.45 V
V
F
Forward on-state voltage, GND-to-V
DD1
,
GND-to-V
DD2
ID = 1.5 A (D1, D2),
See Notes 3 and 4
1.5 V
V
F(SD)
Forward on-state voltage, source-to-drain
IS = 1.5 A, VGS = 0,
See Notes 3 and 4 and Figure 19
1 1.2 V
V
= 16 V,
TC = 25°C 0.05 1
I
DSS
Zero-gate-voltage drain current
DS
,
VGS = 0
TC = 125°C 0.5 10
µ
A
I
GSSF
Forward gate current, drain short-circuited
to source
VGS = 16 V, VDS = 0 10 100 nA
Leakage current, V
-to-GND,
TC = 25°C 0.05 1
I
lkg
g,
DD1
,
V
DD2
-to-GND, gate shorted to source
V
DGND
= 16
V
TC = 125°C 0.5 10
µ
A
VGS = 10 V,
I
= 1.5 A,
TC = 25°C 0.25 0.3
r
DS(on)
Static drain-to-source on-state resistance
D
,
See Notes 3 and 4
and Figure 9
TC = 125°C 0.4 0.48
Ω
g
fs
Forward transconductance
VDS = 14 V, ID = 0.75 A,
See Notes 3 and 4
0.7 1.1 S
C
iss
Short-circuit input capacitance, common
source
100
C
oss
Short-circuit output capacitance, common
source
VDS = 14 V,
f = 1 MHz,
VGS = 0,
See Figure 17
75
pF
C
rss
Short-circuit reverse transfer capacitance,
common source
60
α
s
Sense-FET drain current ratio VDS = 6 V, I
D(Q2C)
= 40 µA 100 150 200
NOTES: 3. Technique should limit TJ – TC to 10°C maximum.
4. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
source-to-drain diode characteristics, Q1A, Q2A, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
rr
Reverse-recovery time
IS = 750 mA,
VGS = 0,
18
ns
Q
RR
Total diode charge
V
DS
= 14 V,
See Figures 1 and 23
di/dt
=
100 A/µs
,
15 nC
TPIC1505
QUAD AND HEX POWER DMOS ARRAY
SLIS058 – JUNE 1996
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
resistive-load switching characteristics, Q1A, Q1B, Q2A, Q2B, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
d(on)
Turn-on delay time 11
t
d(off)
Turn-off delay time
V
= 14 V, R
= 18.7 Ω,t
= 10 ns,
16
t
r
Rise time
DD
,
t
dis
= 10 ns,
L
,
See Figure 3
en
,
3
ns
t
f
Fall time 4
Q
g
Total gate charge
2 2.5
Q
gs(th)
Threshold gate-to-source charge
VDS = 14 V,
ID = 750 mA, VGS = 10 V,
0.35 0.4
nC
Q
gd
Gate-to-drain charge
See Figure 4
0.5 0.6
L
(drain)
Internal drain inductance 7
L
(source)
Internal source inductance 7
nH
r
(gate)
Internal gate resistance 10 Ω
electrical characteristics, Q3A, Q3B, Q4A, Q4B, Q5A, Q5B, TC = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
(BR)DSX
Drain-to-source breakdown voltage ID = 250 µA, VGS = 0 20 V
V
GS(th)
Gate-to-source threshold voltage
ID = 1 mA,
See Figure 6
VDS = V
GS,
1.5 1.9 2.2 V
V
GS(th)match
Gate-to-source threshold voltage matching ID = 1 mA, VDS = V
GS
40 mV
V
(BR)
Reverse drain-to-GND breakdown voltage Drain-to-GND current = 250 µ A (D3) 20 V
V
(DS)on
Drain-to-source on-state voltage
ID = 1 A, VGS = 10 V,
See Notes 3 and 4
0.35 0.48 V
V
F
Forward on-state voltage, GND-to-V
DD3
ID = 1 A (D3), ID = 1 A (D3),
See Notes 3 and 4
1.5 V
V
F(SD)
Forward on-state voltage, source-to-drain
IS = 1 A, VGS = 0,
See Notes 3 and 4 and Figure 20
0.9 1.2 V
V
= 16 V,
TC = 25°C 0.05 1
I
DSS
Zero-gate-voltage drain current
DS
,
VGS = 0
TC = 125°C 0.5 10
µ
A
I
GSSF
Forward gate current, drain short-circuited
to source
VGS = 16 V, VDS = 0 10 100 nA
Leakage current, V
-to-GND,
TC = 25°C 0.05 1
I
lkg
g,
DD3
,
gate shorted to source
V
DGND
=
16 V
TC = 125°C 0.5 10
µ
A
VGS = 10 V,
ID = 1 A,
TC = 25°C 0.35 0.48
r
DS(on)
Static drain-to-source on-state resistance
See Notes 3
and 4 and
Figure 10
TC = 125°C 0.55 0.75
Ω
g
fs
Forward transconductance
VDS = 14 V, ID = 500 mA,
See Notes 3 and 4
0.4 0.72 S
C
iss
Short-circuit input capacitance, common
source
70
C
oss
Short-circuit output capacitance, common
source
VDS = 14 V,
f = 1 MHz,
VGS = 0,
See Figure 18
85
pF
C
rss
Short-circuit reverse transfer capacitance,
common source
50
NOTES: 3: Technique should limit TJ – TC to 10°C maximum.
4: These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
TPIC1505
QUAD AND HEX POWER DMOS ARRAY
SLIS058 – JUNE 1996
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
source-to-drain diode characteristics, Q3A, Q4A, Q5A, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
rr
Reverse-recovery time
IS = 500 mA,
VGS = 0,
15 ns
Q
RR
Total diode charge
V
DS
= 14 V,
See Figures 2 and 23
di/dt
=
100 A/µs
,
10 nC
resistive-load switching characteristics, Q3A, Q3B, Q4A, Q4B, Q5A, Q5B, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
d(on)
Turn-on delay time 11
t
d(off)
Turn-off delay time
V
= 14 V, R
= 32 Ω,t
= 10 ns,
16
t
r
Rise time
DD
,
t
dis
= 10 ns,
L
,
See Figure 3
en
,
3
ns
t
f
Fall time 4
Q
g
Total gate charge
1.7 2.1
Q
gs(th)
Threshold gate-to-source charge
VDS = 14 V,
ID = 500 mA, VGS = 10 V,
0.35 0.45
nC
Q
gd
Gate-to-drain charge
See Figure 4
0.4 0.5
L
(drain)
Internal drain inductance 7
L
(source)
Internal source inductance 7
nH
r
(gate)
Internal gate resistance 10 Ω
thermal resistance
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
R
θJA
Junction-to-ambient thermal resistance See Notes 5 and 8 90
R
θJB
Junction-to-board thermal resistance See Notes 6 and 8 52
°C/W
R
θJP
Junction-to-pin thermal resistance See Notes 7 and 8 28
NOTES: 5. Package is mounted on a FR4 printed-circuit board with no heat sink.
6. Package is mounted on a 24 in2, 4-layer FR4 printed-circuit board.
7. Package is mounted in intimate contact with infinite heat sink.
8. All outputs have equal power.
TPIC1505
QUAD AND HEX POWER DMOS ARRAY
SLIS058 – JUNE 1996
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
†
IRM = maximum recovery current
– Source-to-Drain Diode Current – AI
SD
Time – ns
0 1020 30 405060 708090100
1
0.5
0
– 0.5
– 1
– 1.5
– 2
VDS = 14 V
VGS = 0
TJ = 25°C
Q1A, Q2A
I
RM
†
25% of I
RM
†
t
rr
Shaded Area = Q
RR
Reverse di/dt = 100 A/µs
– 2.5
– 3
Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diodes
TPIC1505
QUAD AND HEX POWER DMOS ARRAY
SLIS058 – JUNE 1996
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
†
IRM = maximum recovery current
– Source-to-Drain Diode Current – AI
SD
Time – ns
0 10 20 30 40 50 60 70 80 90 100
1
0.5
0
– 0.5
– 1
– 1.5
– 2
VDS = 14 V
VGS = 0
TJ = 25°C
Q3A, Q4A, Q5A
I
RM
†
25% of I
RM
†
t
rr
Shaded Area = Q
RR
Reverse di/dt = 100 A/µs
1.5
– 2.5
Figure 2. Reverse-Recovery-Current Waveform of Source-to-Drain Diodes
Pulse Generator
50 Ω
R
gen
50 Ω
V
GS
VDD = 14 V
DUT
V
DS
TEST CIRCUIT
V
DD
V
DS(on)
t
f
t
d(on)
t
r
t
d(off)
VOLTAGE WAVEFORMS
V
GS
V
DS
R
L
CL 30 pF
(see Note A)
t
dis
t
en
10 V
0
NOTE A: CL includes probe and jig capacitance.
Figure 3. Resistive-Switching Test Circuit and Voltage Waveforms
TPIC1505
QUAD AND HEX POWER DMOS ARRAY
SLIS058 – JUNE 1996
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
10 V
VOLTAGE WAVEFORM
Q
gd
Time
Gate Voltage
V
GS
12-V
Battery
0.2 µF
50 kΩ
0.3 µF
Current
Regulator
DUT
Same Type
as DUT
0
IG = 100 µA
IG Current-
Sampling Resistor
ID Current-
Sampling Resistor
VDD = 14 V
TEST CIRCUIT
Q
gs(th)
V
DS
Q
g
Figure 4. Gate-Charge Test Circuit and Voltage Waveform
TYPICAL CHARACTERISTICS
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
– Gate-to-Source Threshold Voltage – V
V
GS(th)
TJ – Junction Temperature – °C
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
– Gate-to-Source Threshold Voltage – V
V
GS(th)
TJ – Junction Temperature – °C
1.5
1
0.5
0
2
2.5
– 40 – 20 0 20 40 60 80 100 120 160
ID = 1 mA
ID = 100 µA
140
1.5
1
0.5
0
2
2.5
– 40 – 20 0 20 40 60 80 100 120 160
ID = 100 µA
ID = 1 mA
VDS = V
GS
Q3A, Q3B, Q4A, Q4B, Q5A, Q5B
ID = 10 mA
140
VDS = V
GS
Q1A, Q1B, Q2A, Q2B
ID = 10 mA
Figure 5 Figure 6
TPIC1505
QUAD AND HEX POWER DMOS ARRAY
SLIS058 – JUNE 1996
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
– Static Drain-to-Source
r
DS(on)
On-State Resistance – Ω
TJ – Junction Temperature – °C
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
– Static Drain-to-Source
r
DS(on)
On-State Resistance – Ω
TJ – Junction Temperature – °C
0.4
0.3
0.2
0.1
– 40 – 20 0 20 40 60 80 100 120 160
ID = 1.5 A
Q1A, Q1B, Q2A, Q2B
VGS = 10 V
0.35
0.25
0.15
VGS = 12 V
0.45
140
VGS = 15 V
0.55
0.4
0.15
– 40 – 20 0 20 40 60 80 100 120 140 160
VGS = 10 V
0.45
0.3
VGS = 12 V
0.2
0.25
0.35
0.5
0.6
0.65
VGS = 15 V
ID = 1 A
Q3A, Q3B, Q4A, Q4B, Q5A, Q5B
Figure 7 Figure 8
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
– Static Drain-to-Sourcer
DS(on)
On-State Resistance –
Ω
ID – Drain Current – A
– Static Drain-to-Sourcer
DS(on)
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
ID – Drain Current – A
0.1
1
0.01 0.1 1 10
VGS = 10 V
VGS = 12 V
TJ = 25°C
Q1A, Q1B, Q2A, Q2B
VGS = 15 V
On-State Resistance –
Ω
0.1
1
0.01 0.1 1 10
VGS = 12 V
TJ = 25°C
Q3A, Q3B, Q4A
Q4B, Q5A, Q5B
0.5
0.5
VGS = 10 V
VGS = 15 V
Figure 9 Figure 10
TPIC1505
QUAD AND HEX POWER DMOS ARRAY
SLIS058 – JUNE 1996
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
– Drain Current – A
DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
I
D
VDS – Drain-to-Source Voltage – V
– Drain Current – A
DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
I
D
VDS – Drain-to-Source Voltage – V
3.5
3
1
0.5
0
2
0123456478910
∆VGS = 1 V
(unless otherwise noted)
TJ = 25°C
Q3A, Q3B, Q4A, Q4B,
Q5A, Q5B
1.5
2.5
2
1
0
0123456
3
4
5
78910
6
∆VGS = 1 V
(unless otherwise noted)
TJ = 25°C
Q1A, Q1B, Q2A, Q2B
VGS = 6 V
VGS = 4 V
VGS = 3 V
VGS = 5 V
VGS = 4 V
VGS = 3 V
Figure 11 Figure 12
DISTRIBUTION OF
FORWARD TRANSCONDUCTANCE
Percentage of Units – %
gfs – Forward Transconductance – S
DISTRIBUTION OF
FORWARD TRANSCONDUCTANCE
Percentage of Units – %
gfs – Forward Transconductance – S
40
20
10
0
1.13
1.142
1.154
1.172
30
1.136
1.148
1.16
1.166
1.178
1.19
1.184
TJ = 25°C
ID = 750 mA
Q1A, Q1B,
Q2A, Q2B
Total Number of Units = 50
VDS =14 V
40
20
10
0
0.7
0.71
0.72
0.735
30
0.705
0.715
0.725
0.73
0.74
0.745
0.75
TJ = 25°C
ID = 500 mA
Q3A, Q3B,
Q4A, Q4B,
Q5A, Q5B
Total Number of Units = 50
VDS = 14 V
Figure 13 Figure 14
TPIC1505
QUAD AND HEX POWER DMOS ARRAY
SLIS058 – JUNE 1996
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
I
D
– Drain Current – A
VGS – Gate-to-Source Voltage – V
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
I
D
– Drain Current – A
VGS – Gate-to-Source Voltage – V
3
2
1
0
4
5
6
1234
56
0
T
J
= –40°C
TJ = 25°C
TJ = 75°C
TJ = 125°C
Q1A, Q1B, Q2A, Q2B
78
T
J
= 150°C
2
1
0.5
0
2.5
3
4
1234
56
0
T
J
= 150°C
TJ = 125°C
8
TJ = 25°C
Q3A, Q3B, Q4A, Q4B,
Q5A, Q5B
1.5
3.5
79
T
J
= 75°C
TJ = –40°C
Figure 15 Figure 16
C – Capacitance – pF
CAPACITANCE
vs
DRAIN-TO-SOURCE VOLTAGE
C – Capacitance – pF
VDS – Drain-to-Source Voltage – V
CAPACITANCE
vs
DRAIN-TO-SOURCE VOLTAGE
VDS – Drain-to-Source Voltage – V
100
80
60
40
120
140
160
02468
240
220
200
180
10 12 14 16
C
oss
C
rss
C
iss
VGS = 0
f = 1 MHz
TJ = 25°C
Q1A, Q1B,
Q2A, Q2B
80
60
40
20
100
120
140
02468
220
200
180
160
10 12 14 16
C
oss
C
rss
C
iss
VGS = 0
f = 1 MHz
TJ = 25°C
Q3A, Q3B, Q4A,
Q4B, Q5A, Q5B
Figure 17 Figure 18
TPIC1505
QUAD AND HEX POWER DMOS ARRAY
SLIS058 – JUNE 1996
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
SOURCE-TO-DRAIN DIODE CURRENT
vs
SOURCE-TO-DRAIN VOLTAGE
VSD – Source-to-Drain Voltage – V
SOURCE-TO-DRAIN DIODE CURRENT
vs
SOURCE-TO-DRAIN VOLTAGE
I
SD
– Source-to-Drain Diode Current – A
VSD – Source-to-Drain Voltage – V
I
SD
– Source-to-Drain Diode Current – A
0.1
1
0.1 10
1
TJ = –40°C
TJ = 25°C
TJ = 150°C
10
VGS = 0
Q1A, Q1B, Q2A, Q2B
0.1
1
0.1 10
1
TJ = 25°C
TJ = 150°C
10
TJ = –40°C
VGS = 0
Q3A, Q3B, Q4A, Q4B,
Q5A, Q5B
Figure 19 Figure 20
DRAIN-TO-SOURCE VOLTAGE AND
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
V
DS
– Drain-to-Source Voltage – V
Qg – Gate Charge – nC
V
GS
– Gate-to-Source Voltage – V
DRAIN-TO-SOURCE VOLTAGE AND
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
V
DS
– Drain-to-Source Voltage – V
Qg – Gate Charge – nC
V
GS
– Gate-to-Source Voltage – V
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
6
4
2
0
8
10
12
VDD = 10 V
ID = 750 mA
TJ = 25°C
Q1A, Q1B, Q2A, Q2B
See Figure 4
14
16
6
4
2
0
8
10
12
14
16
1.8 2
VDD = 12 V
VDD = 14 V
VDD = 12 V
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2
6
4
2
0
8
10
12
VDD = 12 V
VDD = 10 V
VDD = 14 V
ID = 500 mA
TJ = 25°C
Q3A, Q3B,
Q4A, Q4B,
Q5A, Q5B
See Figure 4
14
16
6
4
2
0
8
10
12
14
16
VDD = 12 V
2.25 2.5
VDD = 14 V
VDD = 10 V
Figure 21 Figure 22
TPIC1505
QUAD AND HEX POWER DMOS ARRAY
SLIS058 – JUNE 1996
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
– Reverse Recovery Time – ns
REVERSE RECOVERY TIME
vs
REVERSE di/dt
t
rr
Reverse di/dt – A/µs
TJ = 25°C
See Figures 1 and 2
IS = 500 mA
Q3A, Q4A, Q5A
20
15
5
0
0 20 40 60 80 100 120
25
35
40
140 160 180 200
10
30
IS = 750 mA
Q1A, Q2A
Figure 23
TPIC1505
QUAD AND HEX POWER DMOS ARRAY
SLIS058 – JUNE 1996
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THERMAL INFORMATION
VDS – Drain-to-Source Voltage – V
– Maximum Drain Current – A
I
D
MAXIMUM DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
10
1
0.1
0.1 1 10 100
10 ms
†
1 µs
†
DC Conditions
TC = 25°C
Q1A, Q1B,
Q2A, Q2B
0.5 ms
†
1ms
†
θ
JC
§
θ
JA
‡
Figure 24
VDS – Drain-to-Source Voltage – V
– Maximum Drain Current – A
I
D
MAXIMUM DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
10 ms
†
10
1
0.1
0.1 1 10 100
TC = 25°C
Q3A, Q3B, Q4A,
Q4B, Q5A, Q5B
DC Conditions
1 µs
†
0.5 ms
†
1 ms
†
θ
JC
§
θ
JA
‡
Figure 25
†
Less than 10% duty cycle
‡
Device is mounted on a 24 in2, 4 layer FR4 printed-circuit board.
§
Device is mounted in intimate contact with infinite heat sink.
TPIC1505
QUAD AND HEX POWER DMOS ARRAY
SLIS058 – JUNE 1996
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THERMAL INFORMATION
†
Device is mounted on 24 in2, 4-layer FR4 printed circuit board with no heat sink.
tw – Pulse Duration – s
JBθ
C/W
°
DW PACKAGE
†
JUNCTION-TO-BOARD THERMAL RESISTANCE
vs
PULSE DURATION
– Junction-to-Board Thermal Resistance –
R
NOTE A: ZθB(t) = r(t) R
θJB
tw = pulse duration
tc = cycle time
d = duty cycle = tw/t
c
100
0.0001 0.001
10
1
0.1
0.01 0.1 1 10
t
w
t
c
I
D
0
d = 0.5
d = 0.1
d = 0.02
Single Pulse
d = 0.05
DC Conditions
d = 0.01
d = 0.2
100
Figure 26
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