TPIC1504
QUAD AND HEX POWER DMOS ARRAY
SLIS057 – OCTOBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Low r
DS(on)
:
0.25 Ω Typ (Full H-Bridge)
0.15 Ω Typ (Triple Half H-Bridge)
D
Pulsed Current:
6 A Per Channel (Full H-Bridge)
8 A Per Channel (Triple Half H-Bridge)
D
Matched Sense Transistor for Class A-B
Linear Operation
D
Fast Commutation Speed
description
The TPIC1504 is a monolithic power DMOS array
that consists of ten electrically isolated N-channel
enhancement-mode power DMOS transistors,
four of which are configured as a full H-bridge and six as a triple half H-bridge. The lower stage of the full H-bridge
is provided with an integrated sense-FET to allow biasing of the bridge in class A-B operation.
The TPIC1504 is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for operation
over the case temperature range of –40°C to 125°C.
schematic
12
17
Q4B
GATE1A
23
OUTPUT1
1
GATE1B
3
Q2A
15
Q2B
13
11
D1
D2
GATE3A
24
OUTPUT3
6
GATE3B
4
D3
GATE4A
Q4A
OUTPUT4
GATE4B
10
GATE2A
OUTPUT2
GATE2B
Q3B
Q3A
21 16
Q1B
Q1A
GATE5A
Q5A
OUTPUT5
GATE5B
18, 20
7
5, 9
GND
SOURCE
V
DD1
V
DD2
V
DD3
SENSE
14
Q2C
2
GATE2C
6 V
22
19 8
Q5B
NOTES: A. Terminals 5 and 9 must be externally connected.
B. Terminals 18 and 20 must bef externally connected.
C. No output may be taken greater than 0.5 V below GND.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OUTPUT1
GATE2C
GATE1B
GATE3B
GND
OUTPUT3
SOURCE
OUTPUT5
GND
GATE4B
GATE2B
GATE5B
GATE3A
GATE1A
GATE4A
V
DD1
V
DD3
OUTPUT4
V
DD3
GATE5A
V
DD2
GATE2A
SENSE
OUTPUT2
DW PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1996, Texas Instruments Incorporated
TPIC1504
QUAD AND HEX POWER DMOS ARRAY
SLIS057 – OCTOBER 1996
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings, TC = 25°C (unless otherwise noted)
†
Supply-to-GND voltage 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Source-to-GND voltage (Q3A, Q4A, Q5A) 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output-to-GND voltage 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sense-to-GND voltage 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gate-to-source voltage range, V
GS
(Q1A, Q1B, Q2A, Q2B, Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) ±20 V. . . . .
Gate-to-source voltage, V
GS
(Q2C) –0.7 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous gate-to-source zener-diode current (Q2C) ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed gate-to-source zener-diode current (Q2C) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous drain current, each output (Q1A, Q1B, Q2A, Q2B) 1.5 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous drain current, each output (Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) 2 A. . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous drain current (Q2C) 5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous source-to-drain diode current (Q1A, Q1B, Q2A, Q2B) 1.5 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous source-to-drain diode current (Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) 2 A. . . . . . . . . . . . . . . . . . . . . . .
Continuous source-to-drain diode current (Q2C) 5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed drain current, each output, I
max
(Q1A, Q1B, Q2A, Q2B) (see Note 1 and Figure 24) 6 A. . . . . . . . . .
Pulsed drain current, each output, I
max
(Q3A, Q3B, Q4A, Q4B, Q5A, Q5B)
(see Note 1 and Figure 25) 8 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed drain current, each output, I
max
(Q2C) (see Note 1) 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation, T
C
= 70°C (see Note 2 and Figures 24 and 25) 2.86 W. . . . . . . . . . . . . .
Operating virtual junction temperature range, T
J
–40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating case temperature range, T
C
–40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Pulse duration = 10 ms, duty cycle = 2%
2. Package mounted in intimate contact with infinite heatsink.
TPIC1504
QUAD AND HEX POWER DMOS ARRAY
SLIS057 – OCTOBER 1996
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, Q1A, Q1B, Q2A, Q2B, TC = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
(BR)DSX
Drain-to-source breakdown voltage ID = 250 µA, VGS = 0 20 V
V
GS(th)
Gate-to-source threshold voltage
ID = 1 mA,
See Figure 5
VDS = V
GS,
1.5 1.9 2.2 V
V
GS(th)match
Gate-to-source threshold voltage matching ID = 1 mA, VDS = V
GS
40 mV
V
(BR)
Reverse drain-to-GND breakdown voltage
Drain-to-GND current = 250 µA
(D1, D2)
20 V
V
(BR)GS
Gate-to-source threshold breakdown voltage,
Q2C
IGS = 100 µA 6 V
V
(BR)SG
Source-to-gate breakdown voltage, Q2C ISG = 100 µA 0.5 V
V
(DS)on
Drain-to-source on-state voltage
ID = 1.5 A, VGS = 10 V,
See Notes 3 and 4
0.375 0.45 V
V
F
Forward on-state voltage, GND-to-V
DD1
,
GND-to-V
DD2
ID = 1.5 A (D1, D2)
See Notes 3 and 4
1.7 V
V
F(SD)
Forward on-state voltage, source-to-drain
IS = 1.5 A, VGS = 0,
See Notes 3 and 4 and Figure 19
0.85 1.2 V
V
= 16 V,
TC = 25°C 0.05 1
I
DSS
Zero-gate-voltage drain current
DS
,
VGS = 0
TC = 125°C 0.5 10
µ
A
I
GSSF
Forward gate current, drain short-circuited
to source
VGS = 16 V, VDS = 0 10 100 nA
I
GSSR
Reverse gate current, drain short-circuited
to source
VSG = 0.5 V, VDS = 0 10 100 nA
Leakage current, V
-to-GND, V
-to-GND,
TC = 25°C 0.05 1
I
lkg
g,
DD1
,
DD2
,
gate shorted to source
V
DGND
= 16
V
TC = 125°C 0.5 10
µ
A
VGS = 10 V,
I
= 1.5 A,
TC = 25°C 0.25 0.3
r
DS(on)
Static drain-to-source on-state resistance
D
,
See Notes 3 and 4
and Figure 9
TC = 125°C 0.4 0.475
Ω
g
fs
Forward transconductance
VDS = 14 V, ID = 750 mA,
See Notes 3 and 4 and Figure 13
0.8 1.2 S
C
iss
Short-circuit input capacitance, common source 99
C
oss
Short-circuit output capacitance, common source
VDS = 14 V, VGS = 0,
81
p
C
rss
Short-circuit reverse transfer capacitance,
common source
f = 1 MHz, See Figure 17
59
F
α
s
Sense-FET drain current ratio
VDS = 6 V,
I
D(Q2C)
= 40 µA
100 150 200
NOTES: 3. Technique should limit TJ – TC to 10°C maximum.
4. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
source-to-drain diode characteristics, Q1A, Q2A, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
rr
Reverse-recovery time
IS = 750 mA,
VGS = 0,
18 ns
Q
RR
Total diode charge
V
DS
= 14 V,
See Figures 1 and 23
di/dt
=
100 A/µs
,
13 nC
TPIC1504
QUAD AND HEX POWER DMOS ARRAY
SLIS057 – OCTOBER 1996
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
resistive-load switching characteristics, Q1A, Q1B, Q2A, Q2B, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
d(on)
Turn-on delay time 11
t
d(off)
Turn-off delay time
V
= 14 V , R
= 18.7 Ω,t
= 10 ns,
16
t
r
Rise time
DD
,
t
dis
= 10 ns,
L
,
See Figure 3
en
,
3
ns
t
f
Fall time 4
Q
g
Total gate charge
=
=
=
1.8 2.5
Q
gs(th)
Threshold gate-to-source charge
V
DS
= 14 V,
I
D
=
750 mA
,
See Figure 4 and Figure 21
V
GS
= 10 V,
0.3 0.4
nC
Q
gd
Gate-to-drain charge 0.5 0.6
L
D
Internal drain inductance 7
L
S
Internal source inductance 7
nH
R
g
Internal gate resistance 10 Ω
electrical characteristics, Q3A, Q3B, Q4A, Q4B, Q5A, Q5B, TC = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
(BR)DSX
Drain-to-source breakdown voltage ID = 250 µA, VGS = 0 20 V
V
GS(th)
Gate-to-source threshold voltage
ID = 1 mA,
See Figure 6
VDS = V
GS,
1.5 1.9 2.2 V
V
(BR)
Reverse drain-to-GND breakdown voltage Drain-to-GND current = 250 µA (D3) 20 V
V
(DS)on
Drain-to-source on-state voltage
ID = 2 A, VGS = 10 V,
See Notes 3 and 4
0.3 0.35 V
V
F
Forward on-state voltage, GND-to-V
DD3
ID = 2 A (D3), See Notes 3 and 4 1.5 V
V
F(SD)
Forward on-state voltage, source-to-drain
IS = 2 A, VGS = 0
See Notes 3 and 4 and Figure 20
0.85 1.2 V
V
= 16 V,
TC = 25°C 0.05 1
I
DSS
Zero-gate-voltage drain current
DS
,
VGS = 0
TC = 125°C 0.5 10
µ
A
I
GSSF
Forward gate current, drain short-circuited
to source
VGS = 16 V, VDS = 0 10 100 nA
I
GSSR
Reverse gate current, drain short-circuited
to source
VSG = 16 V, VDS = 0 10 100 nA
Leakage current, V
-to-GND,
TC = 25°C 0.05 1
I
lkg
g,
DD3
,
gate shorted to source
V
DGND
=
16 V
TC = 125°C 0.5 10
µ
A
VGS = 10 V,
ID = 2 A,
TC = 25°C 0.15 0.175
r
DS(on)
Static drain-to-source on-state resistance
See Notes 3
and 4 and
Figure 10
TC = 125°C 0.24 0.275
Ω
g
fs
Forward transconductance
VDS = 14 V, ID = 1 A,
See Notes 3 and 4 and Figure 14
1 1.7 S
C
iss
Short-circuit input capacitance, common source 160
C
oss
Short-circuit output capacitance, common
source
VDS = 14 V,
VGS = 0,
220
pF
C
rss
Short-circuit reverse transfer capacitance,
common source
f = 1 MHz
,
See Figure 18
110
NOTES: 3: Technique should limit TJ – TC to 10°C maximum.
4: These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
TPIC1504
QUAD AND HEX POWER DMOS ARRAY
SLIS057 – OCTOBER 1996
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
source-to-drain diode characteristics, Q3A, Q4A, Q5A, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
rr
Reverse-recovery time
IS = 1 A,
VGS = 0,
34 ns
Q
RR
Total diode charge
V
DS
= 14 V,
See Figures 2 and 23
di/dt
=
100 A/µs
,
30 nC
resistive-load switching characteristics, Q3A, Q3B, Q4A, Q4B, Q5A, Q5B, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
d(on)
Turn-on delay time 30
t
d(off)
Turn-off delay time
V
= 14 V, R
= 14 Ω,t
= 10 ns,
34
t
r
Rise time
DD
,
t
dis
= 10 ns,
L
,
See Figure 3
en
,
15
ns
t
f
Fall time 21
Q
g
Total gate charge
3.2 4.5
Q
gs(th)
Threshold gate-to-source charge
VDS = 14 V, ID = 1 A,
VGS = 10 V,
0.5 0.6
nC
Q
gd
Gate-to-drain charge
See Figure 4 and Figure 22
0.9 1.1
L
D
Internal drain inductance 7
L
S
Internal source inductance 7
nH
R
g
Internal gate resistance 10 Ω
thermal resistance
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
R
θJA
Junction-to-ambient thermal resistance See Notes 5 and 8 90
R
θJB
Junction-to-board thermal resistance See Notes 6 and 8 52
°C/W
R
θJP
Junction-to-pin thermal resistance See Notes 7 and 8 28
NOTES: 5. Package mounted on a FR4 printed-circuit board with no heatsink.
6. Package mounted on a 24 in2, 4-layer FR4 printed-circuit board.
7. Package mounted in intimate contact with infinite heatsink.
8. All outputs with equal power
TPIC1504
QUAD AND HEX POWER DMOS ARRAY
SLIS057 – OCTOBER 1996
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
†
IRM = maximum recovery current
– Source-to-Drain Diode Current – AI
S
0.5
0
– 0.5
– 1
– 1.5
– 2
Time – ns
0 20 40 60 80 100
1
Reverse di/dt = 100 A/µs
25% of I
RM
†
Shaded Area = Q
RR
t
rr(SD)
I
RM
†
VDS = 14 V
VGS = 0
TJ = 25°C
Q1A and Q2A
10 30 50 70 90
– 2.5
– 3
Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diodes
TPIC1504
QUAD AND HEX POWER DMOS ARRAY
SLIS057 – OCTOBER 1996
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
†
IRM = maximum recovery current
Reverse di/dt = 100 A/µs
I
RM
†
t
rr(SD)
Time – ns
0 20 40 60 80 10010 30 50 70 90
Shaded Area = Q
RR
– Source-to-Drain Diode Current – AI
S
1
0.5
0
– 0.5
– 1
– 1.5
– 2
1.5
2
VDS = 14 V
VGS = 0
TJ = 25°C
Q3A, Q4A, and Q5A
Figure 2. Reverse-Recovery-Current Waveform of Source-to-Drain Diodes
Pulse Generator
50 Ω
R
gen
50 Ω
V
GS
VDD = 14 V
DUT
V
DS
TEST CIRCUIT
V
DD
V
DS(on)
t
f
t
d(on)
t
r
t
d(off)
VOLTAGE WAVEFORMS
V
GS
V
DS
R
L
CL 30 pF
(see Note A)
t
dis
t
en
10 V
0 V
NOTE A: CL includes probe and jig capacitance.
Figure 3. Resistive-Switching Test Circuit and Voltage Waveforms
TPIC1504
QUAD AND HEX POWER DMOS ARRAY
SLIS057 – OCTOBER 1996
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
10 V
VOLTAGE WAVEFORM
Q
gd
Time
Gate Voltage
V
GS
12-V
Battery
0.2 µF
50 kΩ
0.3 µF
Current
Regulator
DUT
Same Type
as DUT
0
IG = 10 µA
IG Current-
Sampling Resistor
ID Current-
Sampling Resistor
VDD = 14 V
TEST CIRCUIT
Q
gs(th)
V
DS
Q
g
Figure 4. Gate-Charge Test Circuit and Voltage Waveform
TYPICAL CHARACTERISTICS
Figure 5
1.5
1
0.5
0
2
2.5
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
– Gate-to-Source Threshold Voltage – V
V
GS(th)
TJ – Junction Temperature – °C
– 40 – 20 0 20 40 60 80 100 120 140 160
ID = 10 mA
ID = 100 µA
ID = 1 mA
VDS = V
GS
Q1A, Q1B, Q2A, Q2B
Figure 6
1.5
1
0.5
0
2
2.5
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
– Gate-to-Source Threshold Voltage – V
V
GS(th)
TJ – Junction Temperature – °C
– 40 – 20 0 20 40 60 80 100 120 140 160
ID = 10 mA
ID = 100 µA
ID = 1 mA
VDS = V
GS
Q3A, Q3B, Q4A, Q4B, Q5A, Q5B
TPIC1504
QUAD AND HEX POWER DMOS ARRAY
SLIS057 – OCTOBER 1996
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
– Static Drain-to-Source
r
DS(on)
On-State Resistance – Ω
TJ – Junction Temperature – °C
0.345
0.138
0
– 40 – 20 0 20 40 60 80 100 120
0.276
0.207
0.069
0.483
160
Figure 7
VGS = 10 V
VGS = 15 V
VGS = 12 V
ID =1.5 A
Q1A, Q1B, Q2A, Q2B
140
0.414
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
– Static Drain-to-Sourcer
DS(on)
On-State Resistance – Ω
TJ – Junction Temperature – °C
0.275
0.166
0.083
0
– 40 – 20 0 20 40 60 80 100 120 160
0.221
0.138
0.028
0.193
0.110
0.055
Figure 8
ID = 2 A
Q3A, Q3B, Q4A, Q4B, Q5A, Q5B
VGS = 10 V
VGS = 15 V
VGS = 12 V
140
0.248
TPIC1504
QUAD AND HEX POWER DMOS ARRAY
SLIS057 – OCTOBER 1996
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 9
1
0.1
0.01
0.01 0.1 1 10
– Static Drain-to-Sourcer
DS(on)
On-State Resistance –
Ω
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
ID – Drain Current – A
VGS = 10 V
VGS = 12 V
VGS = 15 V
TJ = 25°C
Q1A, Q1B, Q2A, Q2B
Figure 10
0.01
1
0.01 0.1 1 100
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
– Static Drain-to-Sourcer
DS(on)
On-State Resistance –
Ω
ID – Drain Current – A
0.1
TJ = 25°C
Q3A, Q3B, Q4A
Q4B, Q5A, Q5B
VGS = 12 V
VGS = 10 V
VGS = 15 V
10
Figure 11
2
1
0
0123456
– Drain Current – A
3
4
DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
5
78910
I
D
VDS – Drain-to-Source Voltage – V
6
∆VGS = 1 V
(unless otherwise noted)
TJ = 25°C
Q1A, Q1B, Q2A, Q2B
VGS = 5 V
VGS = 3 V
Figure 12
7
6
3
1
0
5
0123456
– Drain Current – A
8
DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
78910
I
D
VDS – Drain-to-Source Voltage – V
VGS = 3 V
VGS = 4 V
∆VGS = 1 V
(unless otherwise noted)
TJ = 25°C
Q3A, Q3B, Q4A, Q4B,
Q5A, Q5B
VGS = 5 V
4
2
TPIC1504
QUAD AND HEX POWER DMOS ARRAY
SLIS057 – OCTOBER 1996
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 13
DISTRIBUTION OF
FORWARD TRANSCONDUCTANCE
Percentage of Units – %
gfs – Forward Transconductance – S
40
20
10
0
1.14
1.15
1.16
1.175
30
1.145
1.155
1.165
1.17
1.18
1.19
1.185
1.195
TJ = 25°C
ID = 750 mA
Q1A, Q1B, Q2A, Q2B
Total Number of Units = 100
VDS = 14 V
Figure 14
DISTRIBUTION OF
FORWARD TRANSCONDUCTANCE
Percentage of Units – %
gfs – Forward Transconductance – S
50
20
10
0
1.68
1.7
1.72
1.75
30
1.69
1.17
1.73
1.74
1.76
TJ = 25°C
ID = 1 A
Q3A, Q3B, Q4A,
Q4B, Q5A, Q5B
Total Number of Units = 100
VDS = 14 V
40
Figure 15
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
3
2
1
0
4
5
6
123456
0
I
D
– Drain Current – A
VGS – Gate-to-Source Voltage – V
TJ = –40°C
TJ = 25°C
TJ = 75°C
TJ = 125°C
Q1A, Q1B, Q2A, Q2B
78
Figure 16
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
5
3
1
0
6
7
8
123456
0
I
D
– Drain Current – A
VGS – Gate-to-Source Voltage – V
7
TJ = 150°C
TJ = 125°C
TJ = 75°C
TJ = 25°C
TJ = –40°C
Q3A, Q3B, Q4A, Q4B,
Q5A, Q5B
4
2
TPIC1504
QUAD AND HEX POWER DMOS ARRAY
SLIS057 – OCTOBER 1996
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 17
CAPACITANCE
vs
DRAIN-TO-SOURCE VOLTAGE
Capacitance – pF
VDS – Drain-to-Source Voltage – V
100
80
60
40
120
140
160
02468
240
220
200
180
10 12 14 16
C
iss
C
oss
C
rss
VGS = 0
f = 1 MHz
TJ = 25°C
Q1A, Q1B,
Q2A, Q2B
18 20
Figure 18
CAPACITANCE
vs
DRAIN-TO-SOURCE VOLTAGE
Capacitance – pF
VDS – Drain-to-Source Voltage – V
200
150
100
50
250
300
350
02468
550
500
450
400
10 12 14 16
C
oss
C
iss
C
rss
VGS = 0
f = 1 MHz
TJ = 25°C
Q3A, Q3B, Q4A,
Q4B, Q5A, Q5B
18 20
Figure 19
SOURCE-TO-DRAIN DIODE CURRENT
vs
SOURCE-TO-DRAIN VOLTAGE
I
SD
– Source-to-Drain Diode Current – A
VSD – Source-to-Drain Voltage – V
0.1
1
0.1 10
1
10
VGS = 0
Q1A, Q1B, Q2A, Q2B
TJ = 150°C
TJ = –40°C
TJ = 25°C
Figure 20
SOURCE-TO-DRAIN DIODE CURRENT
vs
SOURCE-TO-DRAIN VOLTAGE
I
SD
– Source-to-Drain Diode Current – A
VSD – Source-to-Drain Voltage – V
0.1
1
0.1 10
1
10
VGS = 0
Q3A, Q3B, Q4A, Q4B,
Q5A, Q5B
TJ = 150°C
TJ = –40°C
TJ = 25°C
TPIC1504
QUAD AND HEX POWER DMOS ARRAY
SLIS057 – OCTOBER 1996
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 21
DRAIN-TO-SOURCE VOLTAGE AND
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
V
DS
– Drain-to-Source Voltage – V
Qg – Gate Charge – nC
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2
6
4
2
0
8
10
12
V
GS
– Gate-to-Source Voltage – V
14
16
6
4
2
0
8
10
12
14
16
2.25 2.5
ID = 0.75 A
TJ = 25°C
Q1A, Q1B, Q2A, Q2B
See Figure 4
VDD = 10 V
VDD = 12 V
VDD = 14 V
VDD = 12 V
Figure 22
DRAIN-TO-SOURCE VOLTAGE AND
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
V
DS
– Drain-to-Source Voltage – V
Qg – Gate Charge – nC
0 0.5 1 1.5 2 2.5 3 3.5 4
6
4
2
0
8
10
12
V
GS
– Gate-to-Source Voltage – V
14
16
6
4
2
0
8
10
12
14
16
4.5 5
ID = 1 A
TJ = 25°C
See Figure 4
Q3A, Q3B,
Q4A, Q4B,
Q5A, Q5B
VDD = 10 V
VDD = 12 V
VDD = 14 V
VDD = 10 V
VDD = 14 V
VDD = 12 V
0
50
0 50 100 150
30
20
40
60
200 250
t
rr
– Reverse Recovery Time – ns
Reverse di/dt – A/µs
REVERSE RECOVERY TIME
vs
REVERSE di/dt
TJ = 25°C
See Figures 1 and 2
IS = 1 A
Q3A, Q4A, Q5A
IS = 750 mA
Q1A, Q2A
10
Figure 23
TPIC1504
QUAD AND HEX POWER DMOS ARRAY
SLIS057 – OCTOBER 1996
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THERMAL INFORMATION
10
1
0.1
0.1 1 10 100
VDS – Drain-to-Source Voltage – V
– Maximum Drain Current – A
I
D
MAXIMUM DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
500 µs
†
1 ms
†
10 ms
¶
θ
JC
§
θ
JA
‡
DC Conditions
TC = 25°C
Q1A, Q1B,
Q2A, Q2B
Figure 24
10
1
0.1
0.1 1 10 100
VDS – Drain-to-Source Voltage – V
– Maximum Drain Current – A
I
D
MAXIMUM DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
TC = 25°C
Q3A, Q3B,
Q4A, Q4B,
Q5A, Q5B
θ
JA
‡
θ
JC
§
10 ms
¶
500 µs
†
1 ms
†
DC Conditions
Figure 25
†
Less than 10% duty cycle
‡
Device mounted on a 24-in2, 4-layer FR4 printed-circuit board.
§
Device mounted in intimate contact with infinite heat sink.
¶
Less than 2% duty cycle
TPIC1504
QUAD AND HEX POWER DMOS ARRAY
SLIS057 – OCTOBER 1996
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THERMAL INFORMATION
†
Device is mounted on 24-in2, 4-layer FR4 printed circuit board with no heat sink.
tw – Pulse Duration – s
JBθ
C/W
°
DW PACKAGE
†
JUNCTION-TO-BOARD THERMAL RESISTANCE
vs
PULSE DURATION
– Junction-to-Board Thermal Resistance –
R
NOTE A: ZθB(t) = r(t) R
θJB
tw = pulse duration
tc = cycle time
d = duty cycle = tw/t
c
100
0.0001 0.001
10
1
0.1
0.01 0.1 1 10
t
w
t
c
I
D
0
d = 0.5
d = 0.1
d = 0.02
Single Pulse
d = 0.05
DC Conditions
d = 0.01
d = 0.2
100
Figure 26
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