Texas Instruments TPIC1502DWR, TPIC1502DW Datasheet

TPIC1502

QUAD AND HEX POWER DMOS ARRAY

SLIS054 – OCTOBER 1996

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Low r

DS(on)

:

0.25 Ω Typ (Full H-Bridge)

0.4 Ω Typ (Triple Half H-Bridge)

D

Pulsed Current...4 A Per Channel

D

Matched Sense Transistors for Class A-B
Linear Operation

D

Fast Commutation Speed

description

The TPIC1502 is a monolithic power DMOS array
that consists of ten electrically isolated N-channel
enhancement-mode power DMOS transistors,
four of which are configured as a full H-bridge and
six as a triple half H-bridge. The lower stage of the
full H-bridge is provided with an integrated
sense-FET to allow biasing of the bridge in class
A-B operation.

The TPIC1502 is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for operation
over the case temperature range of –40°C to 125°C.

schematic

Q4B

GATE1A

17

OUTPUT1

19

GATE1B

21

Q2A

9

Q2B

7

5

D1

D2

GATE3A

22

OUTPUT3

1

GATE3B

4

D3

GATE4A

Q4A

OUTPUT4

GATE4B

8

GATE2A

OUTPUT2

GATE2B

Q3B

Q3A

15 11

Q1B

Q1A

GATE5A

Q5A

16

OUTPUT5

GATE5B

24

2, 12

3, 23

GND

SOURCE

V

DD1

V

DD2

V

DD3

SENSE

20

Q2C

6

GATE2C

6 V

18

14 13

Q5B

10

NOTES: A. Terminals 3 and 23 must be externally connected.

B. Terminals 2 and 12 must be externally connected.
C. No output may be taken greater than 0.5 V below GND.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

1
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

OUTPUT3

SOURCE

GND
GATE3B
GATE2B
GATE2C

OUTPUT2

GATE4B
GATE2A
GATE5B

V

DD2

SOURCE

V

DD3

GND
GATE3A
GATE1B
SENSE
OUTPUT1
GATE4A
GATE1A
GATE5A
V

DD1

OUTPUT4
OUTPUT5

DW PACKAGE

(TOP VIEW)

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  1996, Texas Instruments Incorporated

TPIC1502
QUAD AND HEX POWER DMOS ARRAY

SLIS054 – OCTOBER 1996

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings, TC = 25°C (unless otherwise noted)

†

Supply-to-GND voltage 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Source-to-GND voltage (Q3A, Q4A, Q5A) 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output-to-GND voltage 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Sense-to-GND voltage 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Gate-to-source voltage range, V

GS

(Q1A, Q1B, Q2A, Q2B, Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) ±20 V. . . . .

Gate-to-source voltage, V

GS

(Q2C) –0.7 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous gate-to-source zener-diode current (Q2C) ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pulsed gate-to-source zener-diode current (Q2C) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous drain current, each output (Q1A, Q1B, Q2A, Q2B) 1.5 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous drain current, each output (Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) 1.5 A. . . . . . . . . . . . . . . . . . . . . . . .

Continuous drain current (Q2C) 5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous source-to-drain diode current (Q1A, Q1B, Q2A, Q2B) 1.5 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous source-to-drain diode current (Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) 1.5 A. . . . . . . . . . . . . . . . . . . . .

Continuous source-to-drain diode current (Q2C) 5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pulsed drain current, each output, I

max

(Q1A, Q1B, Q2A, Q2B) (see Note 1 and Figure 24) 4 A. . . . . . . . . .

Pulsed drain current, each output, I

max

(Q3A, Q3B, Q4A, Q4B, Q5A, Q5B)

(see Note 1 and Figure 25) 4 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Pulsed drain current, each output, I

max

(Q2C) (see Note 1) 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total power dissipation, T

C

= 70°C (see Note 2 and Figures 24 and 25) 2.86 W. . . . . . . . . . . . . .

Operating virtual junction temperature range, T

J

–40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating case temperature range, T

C

–40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. Pulse duration = 10 ms, duty cycle = 2%

2. Package mounted in intimate contact with infinite heat sink.

TPIC1502

QUAD AND HEX POWER DMOS ARRAY

SLIS054 – OCTOBER 1996

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics, Q1A, Q1B, Q2A, Q2B, TC = 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

(BR)DSX

Drain-to-source breakdown voltage ID = 250 µA, VGS = 0 20 V

V

GS(th)

Gate-to-source threshold voltage

ID = 1 mA,
See Figure 5

VDS = V

GS,

1.5 1.85 2.2 V

V

GS(th)match

Gate-to-source threshold voltage matching ID = 1 mA, VDS = V

GS

40 mV

V

(BR)

Reverse drain-to-GND breakdown voltage

Drain-to-GND current = 250 µA
(D1, D2)

20 V

V

(BR)GS

Gate-to-source breakdown voltage, Q2C IGS = 100 µA 6 V

V

(BR)SG

Source-to-gate breakdown voltage, Q2C IGS = 100 µA 0.7 V

V

(DS)on

Drain-to-source on-state voltage

ID = 1.5 A, VGS = 10 V,
See Notes 3 and 4

0.375 0.45 V

V

F

Forward on-state voltage, GND-to-V

DD1

,

GND-to-V

DD2

ID = 1.5 A (D1, D2)
See Notes 3 and 4

1.5 V

V

F(SD)

Forward on-state voltage, source-to-drain

IS = 1.5 A, VGS = 0,
See Notes 3 and 4 and Figure 19

0.93 1.2 V

V

= 16 V,

TC = 25°C 0.05 1

I

DSS

Zero-gate-voltage drain current

DS

,

VGS = 0

TC = 125°C 0.5 10

µ

A

I

GSSF

Forward gate current, drain short-circuited
to source

VGS = 16 V, VDS = 0 10 100 nA

I

GSSR

Reverse gate current, drain short-circuited
to source

VSG = 16 V, VDS = 0 10 100 nA

Leakage current, V

-to-GND,

TC = 25°C 0.05 1

I

lkg

g,

DD1

,

V

DD2

-to-GND, gate shorted to source

V

DGND

= 16

V

TC = 125°C 0.5 10

µ

A

VGS = 10 V,
I

= 1.5 A,

TC = 25°C 0.25 0.3

r

DS(on)

Static drain-to-source on-state resistance

D

,

See Notes 3 and 4
and Figure 9

TC = 125°C 0.38 0.51

Ω

g

fs

Forward transconductance

VDS = 14 V, ID = 750 mA,
See Notes 3 and 4 and Figure 13

0.75 1.2 S

C

iss

Short-circuit input capacitance, common
source

98

C

oss

Short-circuit output capacitance, common
source

VDS = 14 V,
f = 1 MHz,

VGS = 0,
See Figure 17

70

pF

C

rss

Short-circuit reverse transfer capacitance,
common source

54

α

s

Sense-FET drain current ratio VDS = 6 V, I

D(Q2B)

= 1.5 mA 100 150 200

NOTES: 3. Technique should limit TJ – TC to 10°C maximum.

4. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.

source-to-drain diode characteristics, Q1A, Q2A, TC = 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

rr

Reverse-recovery time

IS = 750 mA, VGS = 0,

18 ns

Q

RR

Total diode charge

V

DS

= 14 V,

di/dt

=

100 A/µs

,

See Figures 1 and 23

14 nC

TPIC1502
QUAD AND HEX POWER DMOS ARRAY

SLIS054 – OCTOBER 1996

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

resistive-load switching characteristics, Q1A, Q1B, Q2A, Q2B, TC = 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

d(on)

Turn-on delay time 12

t

d(off)

Turn-off delay time

V

= 14 V, R

= 18.7 Ω,t

= 10 ns,

13

t

r

Rise time

DD

,

t

dis

= 10 ns,

L

,

See Figure 3

en

,

2.2

ns

t

f

Fall time 6

Q

g

Total gate charge

1.7 2.1

Q

gs(th)

Threshold gate-to-source charge

VDS = 14 V, ID = 750 mA,

VGS = 10 V,

0.3 0.4

nC

Q

gd

Gate-to-drain charge

See Figure 4 and Figure 21

0.4 0.5

L

D

Internal drain inductance 7

L

S

Internal source inductance 7

nH

R

g

Internal gate resistance 0.25 Ω

electrical characteristics, Q3A, Q3B, Q4A, Q4B, Q5A, Q5B, TC = 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

(BR)DSX

Drain-to-source breakdown voltage ID = 250 µA, VGS = 0 20 V

V

GS(th)

Gate-to-source threshold voltage

ID = 1 mA,
See Figure 6

VDS = V

GS,

1.5 1.85 2.2 V

V

(BR)

Reverse drain-to-GND breakdown voltage Drain-to-GND current = 250 µA (D3) 20 V

V

(DS)on

Drain-to-source on-state voltage

ID = 1.5 A, VGS = 10 V,
See Notes 3 and 4

0.6 0.75 V

V

F

Forward on-state voltage, GND-to-V

DD3

ID = 1.5 A (D3), See Notes 3 and
4

1.5 V

V

F(SD)

Forward on-state voltage, source-to-drain

IS = 1.5 A, VGS = 0
See Notes 3 and 4 and Figure 20

1 1.2 V

V

= 16 V,

TC = 25°C 0.05 1

I

DSS

Zero-gate-voltage drain current

DS

,

VGS = 0

TC = 125°C 0.5 10

µ

A

I

GSSF

Forward gate current, drain short-circuited to
source

VGS = 16 V, VDS = 0 10 100 nA

I

GSSR

Reverse gate current, drain short-circuited to
source

VSG = 16 V, VDS = 0 10 100 nA

Leakage current, V

-to-GND, gate shorted to

TC = 25°C 0.05 1

I

lkg

g,

DD3

,g

source

V

DGND

=

16 V

TC = 125°C 0.5 10

µ

A

VGS = 10 V,
ID = 1.5 A,

TC = 25°C 0.4 0.5

r

DS(on)

Static drain-to-source on-state resistance

See Notes 3

and 4 and
Figure 10

TC = 125°C 0.61 0.85

Ω

g

fs

Forward transconductance

VDS = 14 V, ID = 750 mA,
See Notes 3 and 4 and Figure 14

0.4 0.74 S

C

iss

Short-circuit input capacitance, common source 73

C

oss

Short-circuit output capacitance, common source

VDS = 14 V, VGS = 0,

65

p

C

rss

Short-circuit reverse transfer capacitance,
common source

f = 1 MHz, See Figure 18

43

F

NOTES: 3: Technique should limit TJ – TC to 10°C maximum.

4: These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.

TPIC1502

QUAD AND HEX POWER DMOS ARRAY

SLIS054 – OCTOBER 1996

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

source-to-drain diode characteristics, Q3A, Q4A, Q5A, TC = 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

rr

Reverse-recovery time

IS = 750 mA,

VGS = 0,

26 ns

Q

RR

Total diode charge

V

DS

= 14 V,

See Figures 2 and 23

di/dt

=

100 A/

µs,

17 nC

resistive-load switching characteristics, Q3A, Q3B, Q4A, Q4B, Q5A, Q5B, TC = 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

d(on)

Turn-on delay time 13

t

d(off)

Turn-off delay time

V

= 14 V, R

= 18.7 Ω,t

= 10 ns,

13

t

r

Rise time

DD

,

t

dis

= 10 ns,

L

,

See Figure 3

en

,

3

ns

t

f

Fall time 7

Q

g

Total gate charge

1 1.3

Q

gs(th)

Threshold gate-to-source charge

VDS = 14 V, ID = 750 mA,

VGS = 10 V,

0.2 0.25

nC

Q

gd

Gate-to-drain charge

See Figure 4 and Figure 22

0.2 0.25

L

D

Internal drain inductance 7

L

S

Internal source inductance 7

nH

R

g

Internal gate resistance 0.25 Ω

thermal resistance

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

R

θJA

Junction-to-ambient thermal resistance See Notes 5 and 8 90

R

θJB

Junction-to-board thermal resistance See Notes 6 and 8 52

°C/W

R

θJP

Junction-to-pin thermal resistance See Notes 7 and 8 28

NOTES: 5. Package mounted on a FR4 printed-circuit board with no heatsink.

6. Package mounted on a 24 in2, 4-layer FR4 printed-circuit board.

7. Package mounted in intimate contact with infinite heatsink.

8. All outputs with equal power