TPIC1502
QUAD AND HEX POWER DMOS ARRAY
SLIS054 – OCTOBER 1996
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Low r
DS(on)
:
0.25 Ω Typ (Full H-Bridge)
0.4 Ω Typ (Triple Half H-Bridge)
D
Pulsed Current...4 A Per Channel
D
Matched Sense Transistors for Class A-B
Linear Operation
D
Fast Commutation Speed
description
The TPIC1502 is a monolithic power DMOS array
that consists of ten electrically isolated N-channel
enhancement-mode power DMOS transistors,
four of which are configured as a full H-bridge and
six as a triple half H-bridge. The lower stage of the
full H-bridge is provided with an integrated
sense-FET to allow biasing of the bridge in class
A-B operation.
The TPIC1502 is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for operation
over the case temperature range of –40°C to 125°C.
schematic
Q4B
GATE1A
17
OUTPUT1
19
GATE1B
21
Q2A
9
Q2B
7
5
D1
D2
GATE3A
22
OUTPUT3
1
GATE3B
4
D3
GATE4A
Q4A
OUTPUT4
GATE4B
8
GATE2A
OUTPUT2
GATE2B
Q3B
Q3A
15 11
Q1B
Q1A
GATE5A
Q5A
16
OUTPUT5
GATE5B
24
2, 12
3, 23
GND
SOURCE
V
DD1
V
DD2
V
DD3
SENSE
20
Q2C
6
GATE2C
6 V
18
14 13
Q5B
10
NOTES: A. Terminals 3 and 23 must be externally connected.
B. Terminals 2 and 12 must be externally connected.
C. No output may be taken greater than 0.5 V below GND.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OUTPUT3
SOURCE
GND
GATE3B
GATE2B
GATE2C
OUTPUT2
GATE4B
GATE2A
GATE5B
V
DD2
SOURCE
V
DD3
GND
GATE3A
GATE1B
SENSE
OUTPUT1
GATE4A
GATE1A
GATE5A
V
DD1
OUTPUT4
OUTPUT5
DW PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1996, Texas Instruments Incorporated
TPIC1502
QUAD AND HEX POWER DMOS ARRAY
SLIS054 – OCTOBER 1996
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings, TC = 25°C (unless otherwise noted)
†
Supply-to-GND voltage 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Source-to-GND voltage (Q3A, Q4A, Q5A) 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output-to-GND voltage 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Sense-to-GND voltage 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Gate-to-source voltage range, V
GS
(Q1A, Q1B, Q2A, Q2B, Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) ±20 V. . . . .
Gate-to-source voltage, V
GS
(Q2C) –0.7 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous gate-to-source zener-diode current (Q2C) ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed gate-to-source zener-diode current (Q2C) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous drain current, each output (Q1A, Q1B, Q2A, Q2B) 1.5 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous drain current, each output (Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) 1.5 A. . . . . . . . . . . . . . . . . . . . . . . .
Continuous drain current (Q2C) 5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous source-to-drain diode current (Q1A, Q1B, Q2A, Q2B) 1.5 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous source-to-drain diode current (Q3A, Q3B, Q4A, Q4B, Q5A, Q5B) 1.5 A. . . . . . . . . . . . . . . . . . . . .
Continuous source-to-drain diode current (Q2C) 5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed drain current, each output, I
max
(Q1A, Q1B, Q2A, Q2B) (see Note 1 and Figure 24) 4 A. . . . . . . . . .
Pulsed drain current, each output, I
max
(Q3A, Q3B, Q4A, Q4B, Q5A, Q5B)
(see Note 1 and Figure 25) 4 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pulsed drain current, each output, I
max
(Q2C) (see Note 1) 20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation, T
C
= 70°C (see Note 2 and Figures 24 and 25) 2.86 W. . . . . . . . . . . . . .
Operating virtual junction temperature range, T
J
–40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating case temperature range, T
C
–40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. Pulse duration = 10 ms, duty cycle = 2%
2. Package mounted in intimate contact with infinite heat sink.
TPIC1502
QUAD AND HEX POWER DMOS ARRAY
SLIS054 – OCTOBER 1996
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics, Q1A, Q1B, Q2A, Q2B, TC = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
(BR)DSX
Drain-to-source breakdown voltage ID = 250 µA, VGS = 0 20 V
V
GS(th)
Gate-to-source threshold voltage
ID = 1 mA,
See Figure 5
VDS = V
GS,
1.5 1.85 2.2 V
V
GS(th)match
Gate-to-source threshold voltage matching ID = 1 mA, VDS = V
GS
40 mV
V
(BR)
Reverse drain-to-GND breakdown voltage
Drain-to-GND current = 250 µA
(D1, D2)
20 V
V
(BR)GS
Gate-to-source breakdown voltage, Q2C IGS = 100 µA 6 V
V
(BR)SG
Source-to-gate breakdown voltage, Q2C IGS = 100 µA 0.7 V
V
(DS)on
Drain-to-source on-state voltage
ID = 1.5 A, VGS = 10 V,
See Notes 3 and 4
0.375 0.45 V
V
F
Forward on-state voltage, GND-to-V
DD1
,
GND-to-V
DD2
ID = 1.5 A (D1, D2)
See Notes 3 and 4
1.5 V
V
F(SD)
Forward on-state voltage, source-to-drain
IS = 1.5 A, VGS = 0,
See Notes 3 and 4 and Figure 19
0.93 1.2 V
V
= 16 V,
TC = 25°C 0.05 1
I
DSS
Zero-gate-voltage drain current
DS
,
VGS = 0
TC = 125°C 0.5 10
µ
A
I
GSSF
Forward gate current, drain short-circuited
to source
VGS = 16 V, VDS = 0 10 100 nA
I
GSSR
Reverse gate current, drain short-circuited
to source
VSG = 16 V, VDS = 0 10 100 nA
Leakage current, V
-to-GND,
TC = 25°C 0.05 1
I
lkg
g,
DD1
,
V
DD2
-to-GND, gate shorted to source
V
DGND
= 16
V
TC = 125°C 0.5 10
µ
A
VGS = 10 V,
I
= 1.5 A,
TC = 25°C 0.25 0.3
r
DS(on)
Static drain-to-source on-state resistance
D
,
See Notes 3 and 4
and Figure 9
TC = 125°C 0.38 0.51
Ω
g
fs
Forward transconductance
VDS = 14 V, ID = 750 mA,
See Notes 3 and 4 and Figure 13
0.75 1.2 S
C
iss
Short-circuit input capacitance, common
source
98
C
oss
Short-circuit output capacitance, common
source
VDS = 14 V,
f = 1 MHz,
VGS = 0,
See Figure 17
70
pF
C
rss
Short-circuit reverse transfer capacitance,
common source
54
α
s
Sense-FET drain current ratio VDS = 6 V, I
D(Q2B)
= 1.5 mA 100 150 200
NOTES: 3. Technique should limit TJ – TC to 10°C maximum.
4. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
source-to-drain diode characteristics, Q1A, Q2A, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
rr
Reverse-recovery time
IS = 750 mA, VGS = 0,
18 ns
Q
RR
Total diode charge
V
DS
= 14 V,
di/dt
=
100 A/µs
,
See Figures 1 and 23
14 nC
TPIC1502
QUAD AND HEX POWER DMOS ARRAY
SLIS054 – OCTOBER 1996
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
resistive-load switching characteristics, Q1A, Q1B, Q2A, Q2B, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
d(on)
Turn-on delay time 12
t
d(off)
Turn-off delay time
V
= 14 V, R
= 18.7 Ω,t
= 10 ns,
13
t
r
Rise time
DD
,
t
dis
= 10 ns,
L
,
See Figure 3
en
,
2.2
ns
t
f
Fall time 6
Q
g
Total gate charge
1.7 2.1
Q
gs(th)
Threshold gate-to-source charge
VDS = 14 V, ID = 750 mA,
VGS = 10 V,
0.3 0.4
nC
Q
gd
Gate-to-drain charge
See Figure 4 and Figure 21
0.4 0.5
L
D
Internal drain inductance 7
L
S
Internal source inductance 7
nH
R
g
Internal gate resistance 0.25 Ω
electrical characteristics, Q3A, Q3B, Q4A, Q4B, Q5A, Q5B, TC = 25°C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V
(BR)DSX
Drain-to-source breakdown voltage ID = 250 µA, VGS = 0 20 V
V
GS(th)
Gate-to-source threshold voltage
ID = 1 mA,
See Figure 6
VDS = V
GS,
1.5 1.85 2.2 V
V
(BR)
Reverse drain-to-GND breakdown voltage Drain-to-GND current = 250 µA (D3) 20 V
V
(DS)on
Drain-to-source on-state voltage
ID = 1.5 A, VGS = 10 V,
See Notes 3 and 4
0.6 0.75 V
V
F
Forward on-state voltage, GND-to-V
DD3
ID = 1.5 A (D3), See Notes 3 and
4
1.5 V
V
F(SD)
Forward on-state voltage, source-to-drain
IS = 1.5 A, VGS = 0
See Notes 3 and 4 and Figure 20
1 1.2 V
V
= 16 V,
TC = 25°C 0.05 1
I
DSS
Zero-gate-voltage drain current
DS
,
VGS = 0
TC = 125°C 0.5 10
µ
A
I
GSSF
Forward gate current, drain short-circuited to
source
VGS = 16 V, VDS = 0 10 100 nA
I
GSSR
Reverse gate current, drain short-circuited to
source
VSG = 16 V, VDS = 0 10 100 nA
Leakage current, V
-to-GND, gate shorted to
TC = 25°C 0.05 1
I
lkg
g,
DD3
,g
source
V
DGND
=
16 V
TC = 125°C 0.5 10
µ
A
VGS = 10 V,
ID = 1.5 A,
TC = 25°C 0.4 0.5
r
DS(on)
Static drain-to-source on-state resistance
See Notes 3
and 4 and
Figure 10
TC = 125°C 0.61 0.85
Ω
g
fs
Forward transconductance
VDS = 14 V, ID = 750 mA,
See Notes 3 and 4 and Figure 14
0.4 0.74 S
C
iss
Short-circuit input capacitance, common source 73
C
oss
Short-circuit output capacitance, common source
VDS = 14 V, VGS = 0,
65
p
C
rss
Short-circuit reverse transfer capacitance,
common source
f = 1 MHz, See Figure 18
43
F
NOTES: 3: Technique should limit TJ – TC to 10°C maximum.
4: These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.
TPIC1502
QUAD AND HEX POWER DMOS ARRAY
SLIS054 – OCTOBER 1996
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
source-to-drain diode characteristics, Q3A, Q4A, Q5A, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
rr
Reverse-recovery time
IS = 750 mA,
VGS = 0,
26 ns
Q
RR
Total diode charge
V
DS
= 14 V,
See Figures 2 and 23
di/dt
=
100 A/
µs,
17 nC
resistive-load switching characteristics, Q3A, Q3B, Q4A, Q4B, Q5A, Q5B, TC = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
d(on)
Turn-on delay time 13
t
d(off)
Turn-off delay time
V
= 14 V, R
= 18.7 Ω,t
= 10 ns,
13
t
r
Rise time
DD
,
t
dis
= 10 ns,
L
,
See Figure 3
en
,
3
ns
t
f
Fall time 7
Q
g
Total gate charge
1 1.3
Q
gs(th)
Threshold gate-to-source charge
VDS = 14 V, ID = 750 mA,
VGS = 10 V,
0.2 0.25
nC
Q
gd
Gate-to-drain charge
See Figure 4 and Figure 22
0.2 0.25
L
D
Internal drain inductance 7
L
S
Internal source inductance 7
nH
R
g
Internal gate resistance 0.25 Ω
thermal resistance
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
R
θJA
Junction-to-ambient thermal resistance See Notes 5 and 8 90
R
θJB
Junction-to-board thermal resistance See Notes 6 and 8 52
°C/W
R
θJP
Junction-to-pin thermal resistance See Notes 7 and 8 28
NOTES: 5. Package mounted on a FR4 printed-circuit board with no heatsink.
6. Package mounted on a 24 in2, 4-layer FR4 printed-circuit board.
7. Package mounted in intimate contact with infinite heatsink.
8. All outputs with equal power
TPIC1502
QUAD AND HEX POWER DMOS ARRAY
SLIS054 – OCTOBER 1996
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VDS = 14 V
VGS =0
TJ = 25°C
Q1A and Q2A
†
IRM = maximum recovery current
Shaded Area = Q
RR
I
RM
†
t
rr(SD)
25% of I
RM
†
– Source-to-Drain Diode Current – AI
S
1
0.5
0
– 0.5
– 1
– 1.5
– 2
Time – ns
0 20 40 60 80 100
1.5
2
10 30 50 70 90
Reverse di/dt = 100 A/µs
Figure 1. Reverse-Recovery-Current Waveform of Source-to-Drain Diodes
TPIC1502
QUAD AND HEX POWER DMOS ARRAY
SLIS054 – OCTOBER 1996
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
†
IRM = maximum recovery current
Shaded Area = Q
RR
Reverse di/dt = 100 A/µs
t
rr(SD)
25% of I
RM
†
– Source-to-Drain Diode Current – AI
S
1
0.5
0
– 0.5
– 1
– 1.5
– 2
Time – ns
0 20 40 60 80 100
1.5
10 30 50 70 90
I
RM
†
VDS = 14 V
VGS =0
TJ = 25°C
Q3A, Q4A, and Q5A
2
Figure 2. Reverse-Recovery-Current Waveform of Source-to-Drain Diodes
Pulse Generator
50 Ω
R
gen
50 Ω
V
GS
VDD = 14 V
DUT
V
DS
TEST CIRCUIT
V
DD
V
DS(on)
t
f
t
d(on)
t
r
t
d(off)
VOLTAGE WAVEFORMS
V
GS
V
DS
R
L
CL 30 pF
(see Note A)
t
dis
t
en
10 V
0 V
NOTE A: CL includes probe and jig capacitance.
Figure 3. Resistive-Switching Test Circuit and Voltage Waveforms
TPIC1502
QUAD AND HEX POWER DMOS ARRAY
SLIS054 – OCTOBER 1996
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
10 V
VOLTAGE WAVEFORM
Q
gd
Time
Gate Voltage
V
GS
12-V
Battery
0.2 µF
50 kΩ
0.3 µF
Current
Regulator
DUT
Same Type
as DUT
0
IG = 100 µA
IG Current-
Sampling Resistor
ID Current-
Sampling Resistor
VDD = 14 V
TEST CIRCUIT
Q
gs(th)
V
DS
Q
g
Figure 4. Gate-Charge Test Circuit and Voltage Waveform
TYPICAL CHARACTERISTICS
Figure 5
1.5
1
0.5
0
2
2.5
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
– Gate-to-Source Threshold Voltage – V
V
GS(th)
TJ – Junction Temperature – °C
– 40 – 20 0 20 40 60 80 100 120 140 160
VDS = V
GS
Q1A, Q1B, Q2A, Q2B
ID = 10 mA
ID = 1 mA
ID = 100 µA
Figure 6
1.5
1
0.5
0
2
2.5
GATE-TO-SOURCE THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
– Gate-to-Source Threshold Voltage – V
V
GS(th)
TJ – Junction Temperature – °C
– 40 – 20 0 20 40 60 80 100 120 140 160
VDS = V
GS
Q3A, Q3B, Q4A, Q4B, Q5A, Q5B
ID = 1 mA
ID = 100 µA
ID = 10 mA
TPIC1502
QUAD AND HEX POWER DMOS ARRAY
SLIS054 – OCTOBER 1996
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 7
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
–
S
tatic Drain-to-
S
ource
r
DS(on)
On-State Resistance – Ω
TJ – Junction Temperature – °C
0.350
0.250
0.150
0
– 40 – 20 0 20 40 60 80 100 120 140 160
0.300
0.200
0.100
0.400
ID = 1.5 A
Q1A, Q1B, Q2A, Q2B
VGS = 10 V
VGS = 15 V
VGS = 12 V
0.050
Figure 8
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
JUNCTION TEMPERATURE
– Static Drain-to-Source
r
DS(on)
On-State Resistance – Ω
TJ – Junction Temperature – °C
0.60
0.40
0.20
0
– 40 – 20 0 20 40 60 80 100 120 140 160
0.50
0.30
0.10
ID = 1.5 A
Q3A, Q3B, Q4A, Q4B, Q5A, Q5B
VGS = 10 V
VGS = 15 V
VGS = 12 V
Figure 9
1
0.1
0.1 1 10
– Static Drain-to-Sourcer
DS(on)
On-State Resistance –
Ω
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
ID – Drain Current – A
TJ = 25°C
Q1A, Q1B, Q2A, Q2B
VGS = 10 V
VGS = 15 V
VGS = 12 V
Figure 10
0.1
1
0.1 1 10
STATIC DRAIN-TO-SOURCE ON-STATE RESISTANCE
vs
DRAIN CURRENT
– Static Drain-to-Sourcer
DS(on)
On-State Resistance –
Ω
ID – Drain Current – A
TJ = 25°C
Q3A, Q3B, Q4A
Q4B, Q5A, Q5B
VGS = 10 V
VGS = 15 V
VGS = 12 V
TPIC1502
QUAD AND HEX POWER DMOS ARRAY
SLIS054 – OCTOBER 1996
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 11
2
1.5
0
0123456
– Drain Current – A
2.5
3
DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
3.5
78910
I
D
VDS – Drain-to-Source Voltage – V
4
∆VGS = 1 V
(unless otherwise noted)
TJ = 25°C
Q1A, Q1B, Q2A, Q2B
VGS = 4 V
VGS = 3 V
1
0.5
Figure 12
3.5
3
2
1.5
0
2.5
0123456
– Drain Current – A
4
DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
78910
I
D
VDS – Drain-to-Source Voltage – V
VGS = 7 V
∆VGS = 1 V
(unless otherwise noted)
TJ = 25°C
Q3A, Q3B, Q4A, Q4B,
Q5A, Q5B
VGS = 5 V
VGS = 3 V
1
0.5
Figure 13
Percentage of Units – %
gfs – Forward Transconductance – S
DISTRIBUTION OF
FORWARD TRANSCONDUCTANCE
40
20
10
0
1.13
1.15
1.17
1.2
30
1.14
1.16
1.18
1.19
1.21
1.23
1.22
1.24
TJ = 25°C
ID = 750 mA
Q1A, Q1B, Q2A, Q2B
Total Number of Units = 30
VDS = 14V
Figure 14
Percentage of Units – %
gfs – Forward Transconductance – S
DISTRIBUTION OF
FORWARD TRANSCONDUCTANCE
40
20
10
0
0.7
0.72
0.74
0.77
30
0.71
0.73
0.75
0.76
0.78
TJ = 25°C
ID = 750 mA
Q3A, Q3B, Q4A,
Q4B, Q5A, Q5B
Total Number of Units = 30
VDS = 14V
0.79
TPIC1502
QUAD AND HEX POWER DMOS ARRAY
SLIS054 – OCTOBER 1996
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 15
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
1
0
2
1234560
I
D
– Drain Current – A
VGS – Gate-to-Source Voltage – V
3
4
TJ = –40°C
TJ = 125°C
TJ = 25°C
Q1A, Q1B, Q2A, Q2B
789
Figure 16
DRAIN CURRENT
vs
GATE-TO-SOURCE VOLTAGE
3
2
1
0
4
2 4 6 8 10 12
0
I
D
– Drain Current – A
VGS – Gate-to-Source Voltage – V
14
TJ = –40°C
TJ = 25°C
TJ = 125°C
Q3A, Q3B, Q4A, Q4B,
Q5A, Q5B
Figure 17
CAPACITANCE
vs
DRAIN-TO-SOURCE VOLTAGE
C
apac
it
ance – p
F
VDS – Drain-to-Source Voltage – V
66
59
52
45
73
80
87
02468
115
108
101
94
10 12 14 16
VGS = 0
f = 1 MHz
TJ = 25°C
Q1A, Q1B,
Q2A, Q2B
C
iss
C
oss
C
rss
Figure 18
CAPACITANCE
vs
DRAIN-TO-SOURCE VOLTAGE
Capacitance – pF
VDS – Drain-to-Source Voltage – V
49
44
39
34
54
59
64
02468
84
79
74
69
10 12 14 16
C
iss
C
oss
C
rss
VGS = 0
f = 1 MHz
TJ = 25°C
Q3A, Q3B, Q4A,
Q4B, Q5A, Q5B
TPIC1502
QUAD AND HEX POWER DMOS ARRAY
SLIS054 – OCTOBER 1996
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 19
SOURCE-TO-DRAIN DIODE CURRENT
vs
SOURCE-TO-DRAIN VOLTAGE
VSD – Source-to-Drain Voltage – V
I
SD
– Source-to-Drain Diode Current – A
0.1
1
0.1 10
1
TJ = –40°C
TJ = 25°C
TJ = 150°C
10
VGS = 0
Q1A, Q1B, Q2A, Q2B
Figure 20
SOURCE-TO-DRAIN DIODE CURRENT
vs
SOURCE-TO-DRAIN VOLTAGE
I
SD
– Source-to-Drain Diode Current – A
VSD – Source-to-Drain Voltage – V
0.1
1
0.1 10
1
TJ = 25°C
TJ = 150°C
10
TJ = –40°C
VGS = 0
Q3A, Q3B, Q4A, Q4B,
Q5A, Q5B
Figure 21
DRAIN-TO-SOURCE VOLTAGE AND
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
V
DS
– Drain-to-Source Voltage – V
Qg – Gate Charge – nC
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6
6
4
2
0
8
10
12
V
GS
– Gate-to-Source Voltage – V
14
16
6
4
2
0
8
10
12
14
16
1.8 2
ID = 0.75 A
TJ = 25°C
Q1A, Q1B, Q2A, Q2B
See Figure 4
VDD = 10 V
VDD = 12 V
VDD = 14 V
VDD = 12 V
Figure 22
DRAIN-TO-SOURCE VOLTAGE AND
GATE-TO-SOURCE VOLTAGE
vs
GATE CHARGE
V
DS
– Drain-to-Source Voltage – V
Qg – Gate Charge – nC
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
6
4
2
0
8
10
12
V
GS
– Gate-to-Source Voltage – V
14
16
6
4
2
0
8
10
12
14
16
0.9 1
ID = 0.75 A
TJ = 25°C
See Figure 4
Q3A, Q3B,
Q4A, Q4B,
Q5A, Q5B
VDD = 10 V
VDD = 12 V
VDD = 14 V
VDD = 10 V
VDD = 14 V
VDD = 12 V
TPIC1502
QUAD AND HEX POWER DMOS ARRAY
SLIS054 – OCTOBER 1996
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
40
30
20
0
0 20 40 60 80 100 120
50
60
70
140 160 180 200
10
t
rr
– Reverse Recovery Time – ns
Reverse di/dt – A/µs
REVERSE RECOVERY TIME
vs
REVERSE di/dt
TJ = 25°C
See Figures 1 and 2
IS = 750 mA
Q1A, Q1B
IS = 750 mA
Q3A, Q4A, Q5A
Figure 23
TPIC1502
QUAD AND HEX POWER DMOS ARRAY
SLIS054 – OCTOBER 1996
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THERMAL INFORMATION
1
0.1
100
0.1 1 10 100
VDS – Drain-to-Source Voltage – V
– Maximum Drain Current – A
I
D
MAXIMUM DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
θ
JA
‡
θ
JC
§
10 ms
¶
1 ms
†
500 µs
†
DC Conditions
TC = 25°C
Q1A, Q1B, Q2A, Q2B
Figure 24
1
0.1
100
0.1 1 10 100
VDS – Drain-to-Source Voltage – V
– Maximum Drain Current – A
I
D
MAXIMUM DRAIN CURRENT
vs
DRAIN-TO-SOURCE VOLTAGE
TC = 25°C
Q3A, Q3B, Q4A, Q4B, Q5A, Q5B
DC Conditions
θ
JC
§
θ
JA
‡
500 µs
†
10 ms
¶
1 ms
†
Figure 25
†
Less than 10% duty cycle
‡
Device is mounted on a 24 in2, 4 layer FR4 printed-circuit board.
§
Device is mounted in intimate contact with infinite heatsink.
¶
Less than 2% duty cycle
TPIC1502
QUAD AND HEX POWER DMOS ARRAY
SLIS054 – OCTOBER 1996
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
THERMAL INFORMATION
†
Device is mounted on 24 in2, 4-layer FR4 printed circuit board with no heat sink.
tw – Pulse Duration – s
JBθ
C/W
°
DW PACKAGE
†
JUNCTION-TO-BOARD THERMAL RESISTANCE
vs
PULSE DURATION
– Junction-to-Board Thermal Resistance –
R
NOTE A: ZθB(t) = r(t) R
θJB
tw = pulse duration
tc = cycle time
d = duty cycle = tw/t
c
100
0.0001 0.001
10
1
0.1
0.01 0.1 1 10
t
w
t
c
I
D
0
d = 0.5
d = 0.1
d = 0.02
Single Pulse
d = 0.05
DC Conditions
d = 0.01
d = 0.2
100
Figure 26
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