Texas Instruments TPIC1310KTS, TPIC1310KTR Datasheet

TPIC1310

3-HALF H-BRIDGE GATE PROTECTED

POWER DMOS ARRAY

SLIS071 – DECEMBER 1997

D

Configured for 3-Phase Brushless Motor
Drive

D

Low r

DS(on)

D

High Voltage Output...30 V

D

Pulsed Current...12 A Per Channel

D

Input Transient and ESD Protection

D

Compatible With High-Side and Low-Side
Current Sense Resistors

. . . 0.25 Ω Typ

description

The TPIC1310 is a monolithic gate-protected
power DMOS array that consists of six electrically
isolated N-channel enhancement-mode DMOS
transistors configured as a three-half H-bridge.

When suitably heat sunk, the TPIC1310 can drive
motors requiring 2.5 A of phase current. The
DMOS transistors are immune to second break­down effects and current crowding, problems
often associated with bipolar transistors.

The TPIC1310 is offered in 15-pin through-hole
(KTS) and surface-mount (KTR) PowerFLEX
packages and is characterized for operation over
the case temperature range of –40°C to 125°C.

KTR or KTS PACKAGE

(TOP VIEW)

V

DD

OUTA

UGA

LGA

UGB

SUB/GND

SOURCE

OUTB

SOURCE

SUB/GND

LGB

LGC

UGC

OUTC

V

DD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

Tab is SUB/GND



schematic

V

DD

1, 15

Q1

UGA

3

2

OUTA

Q4

NOTES: A. Terminals 1 and 15 must be externally connected.

B. Terminals 6 and 10 must be connected to GND.
C. Terminals 7 and 9 must be connected to the sense resistor or GND.
D. No terminal may be taken greater than 0.5 V below GND.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

LGA

4

13 k 13 k 13 k

8

7, 9

SOURCE

Q2

Q5

OUTB

UGB

LGB

KTR PACKAGE KTS PACKAGE

Q3

OUTC

UG

13

C

LGC

12

SUB/TAB/GND

6, 10

5

14

Q6

11

PowerFLEX is a trademark of Texas Instruments Inc.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1997, Texas Instruments Incorporated

1

TPIC1310
3-HALF H-BRIDGE GATE PROTECTED
POWER DMOS ARRAY

SLIS071 – DECEMBER 1997

absolute maximum ratings over operating case temperature range (unless otherwise noted)

Drain-to-source voltage, V

30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DS

†

Output-to-GND voltage 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SOURCE-to-SUB/GND voltage –0.3 V to 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Gate-to-source voltage range, V
Continuous output current, each output, all outputs on, T
Continuous source-to-drain diode current, T
Pulsed output current, each output, I
Continuous V
Pulsed V

DD

and SOURCE current, TC = 25°C 3 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DD

and SOURCE current, TC = 25°C (see Note 1) 12 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total dissipation, T
Operating virtual junction temperature range, T
Operating case temperature range, T

–0.3 V to 20 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GS

= 25°C 3 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C

, TC = 25°C (see Note 1 and Figure 14) 12 A. . . . . . . . . . . . . . . . . . .

max

= 25°C (see Note 2 and Figure 14) 13.9 W. . . . . . . . . . . . . . . . . . . . . . . . . . . .

C

–40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C

–40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

J

= 25°C 3 A. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions is not implied. Exposure to absolute-maximum-rated conditions for extended
periods may affect device reliability.

NOTES: 1. Pulse duration = 10 µs, duty cycle ≤ 2%

2. Package is mounted in intimate contact with an infinite heat sink.

2

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V

Source-to-gate breakdown voltage

V

I

Drain current-gate shorted to source

DS

,

A

GSSF

circuited to source

I

g, g

V

V

A

D

,

r

Static drain-to-source on-state resistance

Ω

D

,

V

V

f = 1 MHz

See Figure 10

High-side

V

0

di/dt

100 A/

Low-side

GS

µ

3-HALF H-BRIDGE GATE PROTECTED

electrical characteristics, TC = 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

V

(BR)DSX

V

GS(th)

V

(BR)GS

(BR)SG

V

DS(on)

V

F(SD)

DSS

I

I

GSSR

lkg

DS(on)

g

fs

C

iss

C

oss

C

rss

†

Engineering estimate

NOTES: 3. Technique should limit TJ – TC to 10°C maximum.

Drain-to-source breakdown voltage ID = 250 µA, VGS = 0 30 V
Gate-to-source threshold voltage
Gate-to-source breakdown voltage Low-side IGS = 250 µA 20 V

Low-side ISG = 250 µA 0.3
High-side ISG = 250 µA 20

Drain-to-source on-state voltage

Forward on-state voltage, source-to-drain

Forward-gate current, drain short

Reverse-gate current, drain short circuited to source VSG = 0.3 V, VDS = 0 20 200 nA
Leakage current, drain-to-GND gate shorted to

source

Forward transconductance
Short-circuit input capacitance, low-side

Short-circuit output capacitance, low-side
Short-circuit reverse transfer capacitance, low-side

4. These parameters are measured with voltage-sensing contacts separate from the current-carrying contacts.

Low-side
High-side VSG = 16 V, VDS = 0 20 200 nA

ID = 1 mA,
See Figure 4

ID = 3 A,
See Notes 3 and 4

IS = 3 A, VGS = 0,
See Notes 3 and 4 and Figure 11

V

= 28 V,

VGS = 0
VSG = 16 V, VDS = 0,

Internal 13 kΩ from gate to source

= 28

DGND

VGS = 10 V,
I

= 3 A,
See Notes 3 and 4
and Figures 5 and 6

VGS = 14 V,
I

= 3 A,
See Notes 3 and 4
and Figures 5 and 6

VDS = 10 V, ID = 3 A,
See Notes 3 and 4 and Figure 8

= 25 V,

DS

,

=

TPIC1310

POWER DMOS ARRAY

SLIS071 – DECEMBER 1997

VDS = V

VGS = 14 V,

TC = 25°C 0.05 1
TC = 125°C 0.5 10

TC = 25°C 0.05 1
TC = 125°C 0.5 10

TC = 25°C 0.27 0.37

TC = 125°C 0.45 0.55

TC = 25°C 0.22 0.32

TC = 125°C 0.32 0.47

GS

= 0,

GS,

0.9 1.2 1.7 V

0.66 0.9 V

1.1 1.4 V

2 4 mA

0.5 0.85 S
110

120

60

µ

µ

pF

source-to-drain and GND-to-drain diode characteristics, TC = 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

Reverse-recovery time

rr

Q

Total diode charge

RR

t

Reverse-recovery time

rr

Q

Total diode charge

RR

IS = 3 A,

See Figures 1 and 13
IS = 3 A,

VGS = 0,
See Figure 13,

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GS

=

,

VDS = 28 V,

=

VDS = 28 V,
di/dt = 100 A/µs,
SUB/GND connected to
SOURCE

µs,

30 ns
30 nC

70 ns

350 nC

3

TPIC1310

t

10

See

t

10

ns

See Figure 2

,

V

GS

nH

3-HALF H-BRIDGE GATE PROTECTED
POWER DMOS ARRAY

SLIS071 – DECEMBER 1997

resistive-load switching characteristics, TC = 25°C

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

t

d(on)

t

d(off)

t

r

t

f

Q
Q
Q
L

D

L

S

R

thermal resistance

R
R

NOTES: 5. Package mounted in intimate contact with infinite heatsink.

Turn-on delay time 70
Turn-off delay time
Rise time
Fall time
Total gate charge

g

Threshold gate-to-source charge

gs(th)

Gate-to-drain charge

gd

Internal drain inductance 5
Internal source inductance 5
Internal gate resistance 500 Ω

g

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

Junction-to-case thermal resistance, one output on See Note 5 7.5 9 °C/W

θJC

Junction-to-case thermal resistance, two outputs on See Notes 5 and 6 4.5 5.5 °C/W

θJC

6. Two outputs with equal power

VDD = 28 V,

=

en

Figure 2

VDS = 12 V,
ID = 3 A,
V

= 10 V

= 10 V,

See Figure 3 and Figure 12

ns,

RL = 9.3 Ω,

dis

=

ns,

200
140

55

1.6 2

0.5 0.62

0.25 0.31

nC

4

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