TEXAS INSTRUMENTS TPA0132 Technical data
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PWP PACKAGE
(TOP VIEW)
GND
VOLUME
LOUT+
LLINEIN
LHPIN
PV
DD
RIN
LOUT–
LIN
BYPASS
GND
GND
RLINEIN
SHUTDOWN
ROUT+
RHPIN
V
DD
PV
DD
CLK
ROUT–
SE/BTL
PC-BEEP
GND
2.8-W STEREO AUDIO POWER AMPLIFIER
WITH DC VOLUME CONTROL
FEATURES
• Compatible With PC 99 Desktop Line-Out Into
10-k Ω Load
• Compatible With PC 99 Portable Into 8- Ω Load
• Internal Gain Control, Which Eliminates
External Gain-Setting Resistors
• DC Volume Control From 20 dB to -40 dB
• 2.8-W/Ch Output Power Into a 3- Ω Load
• PC-Beep Input
• Depop Circuitry
• Stereo Input MUX
• Fully Differential Input
• Low Supply Current and Shutdown Current
• Surface-Mount Power Packaging 24-Pin
TSSOP PowerPAD™
TPA0132
SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
DESCRIPTION
The TPA0132 is a stereo audio power amplifier in a 24-pin TSSOP thermally enhanced package capable of
delivering 2.8 W of continuous RMS power per channel into 3- Ω loads.
This device minimizes the number of external components needed, which simplifies the design and frees up
board space for other features. When driving 1 W into 8- Ω speakers, the TPA0132 has less than 0.4% THD+N
across its specified frequency range. Included within this device is integrated depop circuitry that virtually
eliminates transients that cause noise in the speakers.
Amplifier gain is controlled by means of a dc voltage input on the VOLUME terminal. There are 31 discrete steps
covering the range of 20 dB (maximum volume setting) to -40 dB (minimum volume setting) in 2-dB steps. When
the VOLUME terminal exceeds 3.54 V, the device is muted. An internal input MUX allows two sets of stereo
inputs to the amplifier. In notebook applications, where internal speakers are driven as bridge-tied load (BTL) and
the line outputs (often headphone drive) are required to be single-ended (SE), the TPA0132 automatically
switches into SE mode when the SE/ BTL input is activated, and this effectively reduces the gain by 6 dB.
The TPA0132 consumes only 10 mA of supply current during normal operation. A shutdown mode is included
that reduces the supply current to 150 µA.
The PowerPAD package (PWP) delivers a level of thermal performance that was previously achievable only in
TO-220-type packages. Thermal impedances of approximately 35 ° C/W are readily realized in multilayer PCB
applications. This allows the TPA0132 to operate at full power into 8- Ω loads at ambient temperatures of 85 ° C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2004, Texas Instruments Incorporated
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ROUT+
-
+
-
+
R
MUX
32-Step
Volume
Control
PC
Beep
MUX
Control
Depop
Circuitry
Power
Management
-
+
-
+
L
MUX
32-Step
Volume
Control
RHPIN
RLINEIN
VOLUME
RIN
PC-BEEP
SE/BTL
LHPIN
LLINEIN
LIN
ROUT-
PV
DD
V
DD
BYPASS
SHUTDOWN
GND
LOUT+
LOUT-
32-Step
Volume
Control
32-Step
Volume
Control
TPA0132
SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
These devices have limited built-in ESD protection. The leads should be shorted together or the device
placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
(1) The PWP package is available taped and reeled. To order a taped
ORDERING INFORMATION
T
A
-40 ° C to 85 ° C TPA0132PWP
and reeled part, add the suffix R to the part number (e.g.,
TPA0132PWPR).
PACKAGED DEVICE
TSSOP (PWP)
FUNCTIONAL BLOCK DIAGRAM
(1)
2
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TPA0132
SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
Terminal Functions
TERMINAL
NAME NO.
BYPASS 11 Tap to voltage divider for internal mid-supply bias generator
CLK 17 I
GND I Ground connection for circuitry. Connected to thermal pad
1, 12
13, 24
LHPIN 6 I Left channel headphone input, selected when SE/ BTL is held high
LIN 10 I Common left input for fully differential input. AC ground for single-ended inputs.
LLINEIN 5 I Left channel line negative input, selected when SE/ BTL is held low
LOUT+ 4 O Left channel positive output in BTL mode and positive output in SE mode
LOUT- 9 O Left channel negative output in BTL mode and high-impedance in SE mode
PCB ENABLE 2 I the amplifier, regardless of its amplitude. If PCB ENABLE is floating or low, the amplifier continues to
PC-BEEP 14 I
PV
DD
7, 18 I Power supply for output stage
RHPIN 20 I Right channel headphone input, selected when SE/ BTL is held high
RIN 8 I Common right input for fully differential input. AC ground for single-ended inputs.
RLINEIN 23 I Right channel line input, selected when SE/ BTL is held low
ROUT+ 21 O Right channel positive output in BTL mode and positive output in SE mode
ROUT- 16 O Right channel negative output in BTL mode and high-impedance in SE mode
SE/ BTL 15 I
SHUTDOWN 22 I
V
DD
19 I
VOLUME 3 I of 20 dB to -40 dB for dc levels of 0.15 V to 3.54 V. When the dc level is over 3.54 V, the device is
Thermal Pad Connect to ground. Must be soldered down in all applications to properly secure device on PC board.
I/O DESCRIPTION
If a 47-nF capacitor is attached, the TPA0132 generates an internal clock. An external clock can
override the internal clock input to this terminal.
If this terminal is high, the detection circuitry for PC-BEEP is overridden and passes PC-BEEP through
operate normally.
The input for PC-Beep mode. PC-BEEP is enabled when a > 1.5-V (peak-to-peak) square wave is
input to PC-BEEP or PCB ENABLE is high.
Input and output MUX control. When this terminal is held high, the LHPIN or RHPIN and SE output is
selected. When this terminal is held low, the LLINEIN or RLINEIN and BTL output are selected.
When held low, this terminal places the entire device, except PC-BEEP detect circuitry, in shutdown
mode.
Analog V
performance.
input supply. This terminal needs to be isolated from PV
DD
to achieve highest
DD
VOLUME detects the dc level at the terminal and sets the gain for 31 discrete steps covering a range
muted.
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Input voltage, V
DD
I
Continuous total power dissipation Internally limited (see Dissipation Rating Table)
Operating free-air temperature range, T
Operating junction temperature range, T
Storage temperature range, T
stg
A
J
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260 ° C
(1) Stresses beyond those listed under "absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
-0.3 V to V
-40 ° C to 85 ° C
-40 ° C to 150 ° C
-65 ° C to 85 ° C
6 V
0.3 V
DD
3
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TPA0132
SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
PACKAGE TA≤ 25 ° C DERATING FACTOR TA= 70 ° C TA= 85 ° C
PWP 2.7 W
(1) See the Texas Instruments document, PowerPAD Thermally Enhanced Package Application Report
(SLMA002), for more information on the PowerPAD™ package. The thermal data was measured on
a PCB layout based on the information in the section entitled Texas Instruments Recommended
Board for PowerPAD™ on page 33 of the before mentioned document.
RECOMMENDED OPERATING CONDITIONS
Supply voltage, V
High-level input voltage, V
Low-level input voltage, V
Operating free-air temperature, T
DD
IH
IL
A
DISSIPATION RATING TABLE
(1)
SE/ BTL 0.8 × V
SHUTDOWN 2 V
PCB ENABLE 0.6 × V
SE/ BTL 0.6 × V
SHUTDOWN 0.8 V
PCB ENABLE 0.4 × V
21.8 mW/ ° C 1.7 W 1.4 W
MIN MAX UNIT
4.5 5.5 V
DD
DD
DD
DD
-40 85 ° C
ELECTRICAL CHARACTERISTICS
at specified free-air temperature, V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
|V
| Output offset voltage (measured differentially) VI= 0 V, AV= 6 dB 35 mV
OO
PSRR Power supply rejection ratio V
|IIH|
|IIL| V
I
DD
I
DD(SD)
High-level input current - SHUTDOWN, SE/ BTL, VOLUME V
High-level input current - PCB ENABLE V
Low-level input current - SHUTDOWN, SE/ BTL, VOLUME,
PCB ENABLE
Supply current mA
Supply current, shutdown mode SHUTDOWN = 0 V, SE/ BTL = 0 V 150 300 µA
= 5 V, TA= 25 ° C (unless otherwise noted)
DD
= 4.9 V to 5.1 V 67 dB
DD
= 5.5 V, VI= V
DD
= 5.5 V, VI= V
DD
= 5.5 V, VI= 0 V 900 nA
DD
DD
DD
BTL mode, SHUTDOWN = 2 V,
SE/ BTL = 0.6 × V
DD
SE mode, SHUTDOWN = 2 V,
SE/ BTL = 0.8 × V
DD
OPERATING CHARACTERISTICS
V
= 5 V, TA= 25 ° C, RL= 4 Ω , Gain = 2 V/V, BTL mode (unless otherwise noted)
DD
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
P
Output power RL= 3 Ω , f = 1 kHz
O
THD+N Total harmonic distortion plus noise PO= 1 W, f = 20 Hz to 15 kHz 0.4%
B
V
Maximum output power bandwidth THD = 5% >15 kHz
OM
Supply ripple rejection ratio dB
Noise output voltage µV
n
f = 1 kHz,
C
= 0.47 µF
(BYP)
C
= 0.47 µF,
(BYP)
f = 20 Hz to 20 kHz
THD = 10% 2.8 W
THD = 1% 2.3 W
BTL mode -65
SE mode -60
BTL mode 42
SE mode 44
900 nA
125 µA
10 15
5 7.5
RMS
4
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0.01%
-40 -30 -20 -10 0
THD+N -Total Harmonic Distortion + Noise
A - V oltage Gain - dB
1%
0.1%
10 20
V
PO = 1 W for A
V
≥ 6 dB
V
O
= 1 V
RMS
for A
V
≤ 4 dB
RL = 8 Ω
BTL
0.1%
0.01%
0.5 0.75 1 1.25 1.5 1.75 2
1%
10%
2.25 2.5 2.75 3
PO - Output Power - W
AV = 20 to 0 dB
f = 1 kHz
BTL
THD+N -Total Harmonic Distortion + Noise
RL = 8 Ω
RL = 3 Ω
RL = 4 Ω
SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
TYPICAL CHARACTERISTICS
Table of Graphs
vs Output power 1, 4, 6, 8, 10
THD+N Total harmonic distortion plus noise
V
n
Output noise voltage vs Frequency 13
Supply ripple rejection ratio vs Frequency 14, 15
Crosstalk vs Frequency 16, 17, 18
Shutdown attenuation vs Frequency 19
SNR Signal-to-noise ratio vs Frequency 20
Closed loop response 21, 22
P
O
P
D
Z
i
Output power vs Load resistance 23, 24
Power dissipation
Input impedance vs Gain 28
vs Voltage gain 2
vs Frequency 3, 5, 7, 9, 11
vs Output voltage 12
vs Output power 25, 26
vs Ambient temperature 27
TPA0132
FIGURE
TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE
vs vs
OUTPUT POWER VOLTAGE GAIN
Figure 1. Figure 2.
5
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0.1%
0.01%
0.01 0.1
1%
10%
1 10
f = 20 Hz
f = 1 kHz
PO - Output Power - W
RL = 3 Ω
AV = 20 to 0 dB
BTL
THD+N -Total Harmonic Distortion + Noise
f = 20 kHz
0.01%
10%
20 100 1k 10k 20k
THD+N -Total Harmonic Distortion + Noise
f - Frequency - Hz
1%
0.1%
RL = 3 Ω
AV = 20 to 0 dB
BTL
PO = 1.75 W
PO = 0.5 W
PO = 1 W
0.1%
0.01%
20 100
1%
10%
1k 10k
f - Frequency - Hz
RL = 4 Ω
AV = 20 to 0 dB
BTL
THD+N -Total Harmonic Distortion + Noise
P
O
= 0.25 W
20k
P
O
= 1 W
P
O
= 1.5 W
0.1%
0.01%
0.01 0.1
1%
10%
1 10
f = 20 Hz
f = 1 kHz
PO - Output Power - W
THD+N -Total Harmonic Distortion + Noise
f = 20 kHz
RL = 4 Ω
AV = 20 to 0 dB
BTL
TPA0132
SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMOINIC DISTORTION PLUS NOISE
vs vs
FREQUENCY OUTPUT POWER
Figure 3. Figure 4.
TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE
vs vs
FREQUENCY OUTPUT POWER
6
Figure 5. Figure 6.
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0.1%
0.01%
0.01 0.1
1%
10%
1 10
f = 20 Hz
f = 1 kHz
PO - Output Power - W
THD+N -Total Harmonic Distortion + Noise
f = 20 kHz
RL = 8 Ω
AV = 20 to 0 dB
BTL
0.01%
10%
20 100 1k 10k 20k
THD+N -Total Harmonic Distortion + Noise
f - Frequency - Hz
1%
0.1%
PO = 0.25 W
P
O
= 0.5 W
PO = 1 W
RL = 8 Ω
AV = 20 to 0 dB
BTL
0.1%
0.01%
20
1%
10%
10k
f - Frequency - Hz
THD+N -Total Harmonic Distortion + Noise
PO = 25 mW
20k
RL = 32 Ω
AV = 14 to 0 dB
SE
PO = 50 mW
PO = 75 mW
100 1k
0.001%
0.1%
0.01%
0.01 0.1
1%
10%
1
f = 20 Hz
f = 1 kHz
PO - Output Power - W
THD+N -Total Harmonic Distortion + Noise
f = 20 kHz
RL = 32 Ω
AV = 14 to 0 dB
SE
TPA0132
SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE
vs vs
FREQUENCY OUTPUT POWER
Figure 7. Figure 8.
TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE
vs vs
FREQUENCY OUTPUT POWER
Figure 9. Figure 10.
7
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THD+N -Total Harmonic Distortion + Noise
f = 20 kHz
VO - Output Voltage - V
RMS
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
0.001%
0.01%
0.1%
1%
10%
RL = 10 kΩ
AV = 14 to 0 dB
SE
f = 1 kHz
f = 20 Hz
0.001%
10%
20 100 1k 10k 20k
THD+N -Total Harmonic Distortion + Noise
f - Frequency - Hz
1%
0.1%
VO = 1 V
RMS
0.01%
RL = 10 kΩ
AV = 14 to 0 dB
SE
120
0
20 100
140
160
1k 10k
BW − Bandwidth − Hz
VDD = 5 V
BW = 22 Hz to 22 kHz
RL = 4 Ω
AV = 20 dB
20k
AV = 6 dB
− Output Noise Voltage − VµV
n
RMS
20
40
60
80
100
-100
-120
20 100
-80
1k 10k
RL = 8 Ω
C
(BYP)
= 0.47 µF
BTL
Supply Ripple Rejection Ratio - dB
A
V
= 6 dB
-60
-40
-20
0
f - Frequency - Hz
20k
A
V
= 20 dB
TPA0132
SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
TOTAL HARMONIC DISTORTION PLUS NOISE TOTAL HARMONIC DISTORTION PLUS NOISE
vs vs
FREQUENCY OUTPUT VOLTAGE
Figure 11. Figure 12.
OUTPUT NOISE VOLTAGE SUPPLY RIPPLE REJECTION RATIO
vs vs
BANDWIDTH FREQUENCY
8
Figure 13. Figure 14.
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-100
-120
20 100
-80
1k 10k
RL = 32 Ω
C
(BYP)
= 0.47 µF
SE
A
V
= 6 dB
-60
-40
-20
0
f - Frequency - Hz
20k
A
V
= 14 dB
Supply Ripple Rejection Ratio - dB
-120
-80
20 100 1k 10k 20k
Crosstalk - dB
f - Frequency - Hz
-90
-100
-110
PO = 1 W
RL = 8 Ω
AV = 20 dB
BTL
-70
-60
Left to Right
Right to Left
-50
-40
-120
-40
20 100 1k 10k 20k
Crosstalk - dB
f - Frequency - Hz
-60
-80
-100
VO = 1 V
RMS
RL = 10 kΩ
AV = 6 dB
SE
-20
0
Left to Right
Right to Left
−120
−80
20 100 1k 10k 20k
Crosstalk − dB
f − Frequency − Hz
−90
−100
−110
PO = 1 W
RL = 8 Ω
AV = 6 dB
BTL
−70
−60
Left to Right
Right to Left
−50
−40
TPA0132
SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
SUPPLY RIPPLE REJECTION RATIO CROSSTALK
vs vs
FREQUENCY FREQUENCY
Figure 15. Figure 16.
CROSSTALK CROSSTALK
vs vs
FREQUENCY FREQUENCY
Figure 17. Figure 18.
9
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-120
-40
20 100 1k 10k 20k
Shutdown Attenuation - dB
f - Frequency - Hz
-60
-80
-100
-20
0
VI = 1 V
RMS
RL = 8 Ω, BTL
RL = 32 Ω, SE
RL = 10 kΩ, SE
80
110
20 100 1k 10k 20k
SNR − Signal-To-Noise Ratio − dB
f − Frequency − Hz
105
100
95
115
120
85
90
PO = 1 W
RL = 8 Ω
BTL
AV = 20 dB
AV = 6 dB
-10
20
10 100 1k 10k 100k
Gain - dB
f - Frequency - Hz
15
10
5
25
30
-5
0
180°
90°
0°
-90°
-180°
1M
Phase
RL = 8 Ω
AV = 20 dB
BTL
Gain
Phase
-10
20
10 100 1k 10k 100k
Gain - dB
f - Frequency - Hz
15
10
5
25
30
-5
0
180°
90°
0°
-90°
-180°
1M
RL = 8 Ω
AV = 6 dB
BTL
Gain
Phase
Phase
TPA0132
SLOS223E – MAY 1999 – REVISED SEPTEMBER 2004
SHUTDOWN ATTENUATION SIGNAL-TO-NOISE RATIO
vs vs
FREQUENCY FREQUENCY
Figure 19. Figure 20.
CLOSED LOOP RESPONSE CLOSED LOOP RESPONSE
10
Figure 21. Figure 22.
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