Texas Instruments TP3067BN, TP3067BDWR, TP3067BDW, TP13067BN, TP13067BDW Datasheet

TP3064B, TP3067B, TP13064B, TP13067B

MONOLITHIC SERIAL INTERFACE

COMBINED PCM CODEC AND FILTER

SCTS031D – MAY 1990 –REVISED JULY 1996

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Complete PCM Codec and Filtering
Systems Include:
– Transmit High-Pass and Low-Pass

Filtering

– Receive Low-Pass Filter With (sin x)/x

Correction

– Active RC Noise Filters
– µ-Law or A-Law Compatible Coder and

Decoder
– Internal Precision Voltage Reference
– Serial I/O Interface
– Internal Autozero Circuitry

D

µ-Law – TP13064B and TP3064B

D

A-Law – TP13067B and TP3067B

D

±5-V Operation

D

Low Operating Power...70 mW Typ

D

Power-Down Standby Mode...3mW Typ

D

Automatic Power Down

D

TTL- or CMOS-Compatible Digital Interface

D

Maximizes Line Interface Card Circuit
Density

D

Improved Versions of National
Semiconductor TP3064, TP3067, TP3064-X,
and TP3067-X

description

The TP3064B, TP3067B, TP13064B, and
TP13067B each comprise a single-chip pulse­code-modulation encoder and decoder (PCM
codec), and PCM line filter. They also provide
band-pass filtering of the analog signals prior to
the encoding, and low-pass filtering after the
decoding of voice signals and call-progress tones.
All the functions required to interface a full-duplex
(2-wire) voice telephone circuit with a time-divi­sion-multiplexed (TDM) system are included
on-chip. These devices are pin-for-pin compatible
with the National Semiconductor TP3064 and
TP3067. Primary applications include:

• Line interface for digital transmission and

switching of T1 carrier, PABX (private
automated branch exchange), and central
office telephone systems

• Subscriber line concentrators

• Digital-encryption systems

• Digital voice-band data-storage systems

• Digital signal processing

These devices are designed to perform the transmit encoding (A/D conversion) and receive decoding (D/A
conversion) as well as the transmit and receive filtering functions in a PCM system, and are intended to be used
at the analog termination of a PCM line or trunk. They require a transmit master clock and a receive master clock
that may be asynchronous (1.536 MHz, 1.544 MHz, or 2.048 MHz), transmit and receive data clocks that are
synchronous with the master clock (but can vary from 64 kHz to 2.048 MHz), and transmit and receive
frame-sync pulses. The TP3064B and TP13064B contain patented circuitry to achieve low transmit channel
idle noise and are not recommended for applications in which the composite signals on the transmit side are
below –55 dBm0.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the CMOS gates.

Copyright  1996, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

VPO+

ANLG GND

VPO–

VPI

VFRO

V

CC

FSR

DR

BCLKR/CLKSEL

MCLKR/PDN

V

BB

VFXI+
VFXI–
GSX
ANLG LOOP
TSX
FSX
DX
BCLKX
MCLKX

DW OR N PACKAGE

(TOP VIEW)

TP3064B, TP3067B, TP13064B, TP13067B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER

SCTS031D – MAY 1990 –REVISED JULY 1996

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

The TP3064B and TP3067B are characterized for operation from 0°C to 70°C. The TP13064B and TP13067B
are characterized for operation from –40°C to 85°C.

functional block diagram

R2

16

FSX

11 10 12 9 147

MCLKX MCLKR/

PDN

BCLKX BCLKR/

CLKSEL

FSR

TSX

15

Timing and Control

DR

8

CLK

Receive

Regulator

S/H

DAC

RC Active

Filter

13

DX

OE

Transmit

Regulator

A/D

Control

Logic

Comparator

Voltage

Reference

Autozero

Logic

S/H

DAC

Switched­Capacitor

Band-Pass Filter

RC

Active Filter

3

VPO–

+

–

VFXI+

19

R1

18

VFXI–

Analog

Input

Switched­Capacitor

Low-Pass Filter

VPO+

1

R

R3

R4

R

4 VPI

5 VFRO

ANLG
LOOP

GSX

17

+

–

+

–

VBBANLG GNDV

CC

620 2

–5 V5 V

TP3064B, TP3067B, TP13064B, TP13067B

MONOLITHIC SERIAL INTERFACE

COMBINED PCM CODEC AND FILTER

SCTS031D – MAY 1990 –REVISED JULY 1996

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

DESCRIPTION

ANLG GND 2 Analog ground. All signals are referenced to ANLG GND.
ANLG LOOP 16 Analog loopback control input. Must be set to logic low for normal operation. When pulled to logic high, the transmit

filter input is disconnected from the output of the transmit preamplifier and connected to the VPO+ output of the
receive power amplifier.

BCLKR/CLKSEL 9 The bit clock that shifts data into DR after the FSR leading edge. May vary from 64 kHz to 2.048 MHz. Alternately ,

can be a logic input that selects either 1.536 MHz/1.544 MHz or 2.048 MHz for master clock in synchronous mode.
BCLKX is used for both transmit and receive directions (see Table 1).

BCLKX 12 The bit clock that shifts out the PCM data on DX. May vary from 64 kHz to 2.048 MHz, but must be synchronous

with MCLKX
DR 8 Receive data input. PCM data is shifted into DR following the FSR leading edge.
DX 13 The 3-state PCM data output that is enabled by FSX
FSR 7 Receive frame-sync pulse input that enables BCLKR to shift PCM data in DR. FSR is an 8-kHz pulse train (see

Figures 1 and 2 for timing details).
FSX 14 Transmit frame-sync pulse that enables BCLKX to shift out the PCM data on DX. FSX is an 8-kHz pulse train (see

Figures 1 and 2 for timing details).
GSX 17 Analog output of the transmit input amplifier. GSX is used to externally set gain.
MCLKR/PDN 10 Receive master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be synchronous with MCLKX, but

should be synchronous for best performance. When MCLKR is connected continuously low, MCLKX is selected

for all internal timing. When MCLKR is connected continuously high, the device is powered down.
MCLKX 11 Transmit master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be asynchronous with MCLKR
TSX 15 Open-drain output that pulses low during the encoder time slot
V

BB

20 Negative power supply. VBB = –5 V ± 5%

V

CC

6 Positive power supply. VCC = 5 V ± 5%
VFRO 5 Analog output of the receive filter
VFXI+ 19 Noninverting input of the transmit input amplifier
VFXI– 18 Inverting input of the transmit input amplifier
VPI 4 Inverting input to the receive power amplifier. Also powers down both amplifiers when connected to VBB.
VPO+ 1 The noninverted output of the receive power amplifier
VPO– 3 The inverted output of the receive power amplifier

TP3064B, TP3067B, TP13064B, TP13067B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER

SCTS031D – MAY 1990 –REVISED JULY 1996

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†

Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply voltage, V

BB

(see Note 1) –7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range at any analog input or output V

CC

+ 0.3 V to VBB – 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range at any digital input or output V

CC

+ 0.3 V to GND – 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range: TP3064B, TP3067B 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TP13064B, TP13067B –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package 260°C. . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltages are with respect to GND.

DISSIPATION RATING TABLE

PACKAGE

TA ≤ 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

TA = 70°C

POWER RATING

TA = 85°C

POWER RATING

DW 1025 mW 8.2 mW/°C 656 mW 533 mW

N 1150 mW 9.2 mW/°C 736 mW 598 mW

recommended operating conditions (see Note 2)

MIN NOM MAX UNIT

Supply voltage, V

CC

4.75 5 5.25 V

Supply voltage, V

BB

–4.75 –5 –5.25 V

High-level input voltage, V

IH

2.2 V

Low-level input voltage, V

IL

0.6 V

Common-mode input voltage range, V

ICR

†

±2.5 V

Load resistance at GSX, R

L

10 kΩ

Load capacitance at GSX, C

L

50 pF

p

p

TP3064B, TP3067B 0 70

°

Operating free-air temperature, T

A

TP13064B, TP13067B –40 85

°C

†

Measure with CMRR > 60 dB.

NOTE 2: T o avoid possible damage to these CMOS devices and resulting reliability problems, the power-up procedure described in the device

power-up sequence paragraphs later in this document should be followed.

TP3064B, TP3067B, TP13064B, TP13067B

MONOLITHIC SERIAL INTERFACE

COMBINED PCM CODEC AND FILTER

SCTS031D – MAY 1990 –REVISED JULY 1996

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

electrical characteristics over power supply variations and recommended free-air temperature
range (unless otherwise noted)

supply current

TP306xB TP1306xB

PARAMETER

TEST CONDITIONS

MIN TYP†MAX MIN TYP†MAX

UNIT

pp

Power down

0.5 1 0.5 1.2

ICCSupply current from V

CC

Active

No load

6 10 6 11

mA

pp

Power down

0.5 1 0.5 1.2

IBBSupply current from V

BB

Active

No load

6 10 6 11

mA

†

All typical values are at VCC = 5 V, VBB = –5 V , and TA = 25°C.

electrical characteristics at VCC = 5 V ± 5%, VBB = –5 V ± 5%, GND at 0 V , TA = 25°C (unless otherwise
noted)

digital interface

PARAMETER TEST CONDITIONS MIN MAX UNIT

V

OH

High-level output voltage DX IH = –3.2 mA 2.4 V

p

DX IL = 3.2 mA 0.4

VOLLow-level output voltage

TSX IL = 3.2 mA, Drain open 0.4

V

I

IH

High-level input current VI = VIH to V

CC

±10 µA

I

IL

Low-level input current All digital inputs VI = GND to V

IL

±10 µA

I

OZ

Output current in high-impedance state DX VO = GND to V

CC

±10 µA

analog interface with transmit amplifier input

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

I

I

Input current VFXI+ or VFXI– VI = –2.5 V to 2.5 V ±200 nA

r

i

Input resistance VFXI+ or VFXI– VI = –2.5 V to 2.5 V 10 MΩ

r

o

Output resistance Closed loop, Unit gain 1 3 Ω
Output dynamic range GSX RL ≥ 10 kΩ ±2.8 V

A

V

Open-loop voltage amplification VFXI+ to GSX 5000

B

I

Unity-gain bandwidth GSX 1 2 MHz

V

IO

Input offset voltage VFXI+ or VFXI– ±20 mV
CMRR Common-mode rejection ratio 60 dB
k

SVR

Supply-voltage rejection ratio 60 dB

†

All typical values are at VCC = 5 V, VBB = –5 V , and TA = 25°C.

analog interface with receive filter

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

Output resistance VFRO 1 3 Ω
Load resistance VFRO = ±2.5 V 600 Ω
Load capacitance VFRO to GND 500 pF
Output dc offset voltage VFRO to GND ±200 mV

†

All typical values are at VCC = 5 V, VBB = –5 V , and TA = 25°C.

TP3064B, TP3067B, TP13064B, TP13067B
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER

SCTS031D – MAY 1990 –REVISED JULY 1996

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

analog interface with power amplifiers

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

I

I

Input current VPI = –1 V to 1 V ±100 nA

r

i

Input resistance VPI = –1 V to 1 V 10 MΩ

r

o

Output resistance VPO+ or VPO– Inverting unity gain 1 Ω

A

V

Voltage amplification VPO– or VPO+ VPO– = 1.77 Vrms, RL = 600 Ω –1

B

I

Unity-gain bandwidth VPO– Open loop 400 kHz

V

IO

Input offset voltage ±25 mV

pp

0 kHz to 4 kHz 60

k

SVR

Suppl

y-v

oltage rejection ratio of V

CC

or

V

BB

VPO– connected to VPI

4 kHz to 50 kHz 36

dB

R

L

Load resistance Connected from VPO+ to VPO– 600 Ω

C

L

Load capacitance 100 pF

†

All typical values are at VCC = 5 V, VBB = –5 V , and TA = 25°C.

TP3064B, TP3067B, TP13064B, TP13067B

MONOLITHIC SERIAL INTERFACE

COMBINED PCM CODEC AND FILTER

SCTS031D – MAY 1990 –REVISED JULY 1996

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

timing requirements

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

f

clock(M)

Frequency of master clock

MCLX

and

MCLKR

Depends on the device used and
BCLKX/CLKSEL

1.536

1.544

2.048

MHz

f

clock(B)

Frequency of bit clock, transmit BCLKX 64 2.048 MHz

t

r1

Rise time of master clock

MCLKX

and

MCLKR

Measured from 20% to 80% 50 ns

t

f1

Fall time of master clock

MCLKX

and

MCLKR

Measured from 20% to 80% 50 ns

t

r2

Rise time of bit clock, transmit BCLKX Measured from 20% to 80% 50 ns
t

f2

Fall time of bit clock, transmit BCLKX Measured from 20% to 80% 50 ns
t

w1

Pulse duration, MCLKX and MCLKR high 160 ns
t

w2

Pulse duration, MCLKX and MCLKR low 160 ns
t

su1

Setup time, BCLKX high (and FSX in long-frame

sync mode) before MCLKX↓

First bit clock after the leading edge
of FSX

100 ns

t

w3

Pulse duration, BCLKX and BCLKR high VIH = 2.2 V 160 ns
t

w4

Pulse duration, BCLKX and BCLKR low VIL = 0.6 V 160 ns
t

h1

Hold time, frame sync low after bit clock low (long

frame only)

0 ns

t

h2

Hold time, BCLKX high after frame sync↑ (short

frame only)

0 ns

t

su2

Setup time, frame sync high before bit clock↓ (long

frame only)

80 ns

t

d1

Delay time, BCLKX high to data valid Load = 150 pF plus 2 LSTTL loads‡ 0 140 ns
t

d2

Delay time, BCLKX high to TSX low Load = 150 pF plus 2 LSTTL loads‡ 140 ns
t

d3

Delay time, BCLKX (or 8 clock FSX in long frame

only) low to data output disabled

50 165 ns

t

d4

Delay time, FSX or BCLKX high to data valid (long

frame only)

CL = 0 pF to 150 pF 20 165 ns

t

su3

Setup time, DR valid before BCLKR↓ 50 ns
t

h3

Hold time, DR valid after BCLKR or BCLKX↓ 50 ns
t

su4

Setup time, FSR or FSX high before BCLKR or

BCLKX↓

Short-frame sync pulse (1- or 2-bit
clock periods long) (see Note 3)

50 ns

t

h4

Hold time, FSX or FSR high after BCLKX or

BCLKR↓

Short-frame sync pulse (1- or 2-bit
clock periods long) (see Note 3)

100 ns

t

h5

Hold time, frame sync high after bit clock↓

Long-frame sync pulse (from 3- to
8-bit clock periods long)

100 ns

t

w5

Pulse duration of the frame sync pulse (low level) 64 kbps operating mode 160 ns

†

All typical values are at VCC = 5 V, VBB = –5 V , and TA = 25°C.

‡

Nominal input value for an LSTTL load is 18 kΩ.

NOTE 3: For short-frame sync timing, FSR and FSX must go high while their respective bit clocks are high.