TEXAS INSTRUMENTS TP3064A, TP3067A, TP13064A, TP13067A Technical data

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D

Complete PCM Codec and Filtering
Systems Include:
– Transmit High-Pass and Low-Pass

Filtering

– Receive Low-Pass Filter With (sin x)/x

Correction

– Active RC Noise Filters
– µ-Law or A-Law Compatible Coder and

Decoder
– Internal Precision Voltage Reference
– Serial I/O Interface
– Internal Autozero Circuitry

description

The TP3064A, TP3067A, TP13064A, and
TP13067A are comprised of a single-chip PCM
codec (pulse-code-modulated encoder and de­coder) and PCM line filter. These devices provide
all the functions required to interface a full-duplex
(2-wire) voice telephone circuit with a TDM
(time-division-multiplexed) system. These de­vices are pin-for-pin compatible with the National
Semiconductor TP3064A and TP3067A, respec­tively. Primary applications include:

• Line interface for digital transmission and

switching of T1 carrier, PABX, and central
office telephone systems

• Subscriber line concentrators

• Digital-encryption systems

• Digital voice-band data-storage systems

• Digital signal processing

TP3064A, TP3067A, TP13064A, TP13067A

MONOLITHIC SERIAL INTERFACE

COMBINED PCM CODEC AND FILTER

SCTS025C – SEPTEMBER 1992 –REVISED JUL Y 1996

D

µ-Law – TP3064B and TP13064B

D

A-Law – TP3067B and TP13067B

D

±5-V Operation

D

Low Operating Power...70 mW Typ

D

Power-Down Standby Mode...3 mW Typ

D

Automatic Power Down

D

TTL- or CMOS-Compatible Digital Interface

D

Maximizes Line Interface Card Circuit
Density

D

Improved Versions of National
Semiconductor TP3064, TP3067, TP3064-X,
TP3067-X

DW OR N PACKAGE

(TOP VIEW)

VPO+

ANLG GND

VPO–

VPI

VFRO

V

CC

FSR

DR

BCLKR/CLKSEL

MCLKR/PDN

1
2
3
4
5
6
7
8
9
10

V

20

BB

VFXI+

19

VFXI–

18

GSX

17

ANLG LOOP

16

TSX

15

FSX

14

DX

13

BCLKX

12

MCLKX

11

These devices are designed to perform the transmit encoding (A/D conversion) and receive decoding (D/A
conversion) as well as the transmit and receive filtering functions in a PCM system. They are intended to be
used at the analog termination of a PCM line or trunk. The devices require two transmit and receive master
clocks that may be asynchronous (1.536 MHz, 1.544 MHz, or 2.048 MHz), transmit and receive data clocks that
are synchronous with the master clock (but can vary from 64 kHz to 2.048 MHz), and transmit and receive
frame-sync pulses. The TP3064A, TP3067A, TP13064A, and TP13067A provide the band-pass filtering of the
analog signals prior to encoding and after decoding of voice and call progress tones. The TP3067A and
TP13067A contain patented circuitry to achieve low transmit channel idle noise and are not recommended for
applications in which the composite signals on the transmit side are below –55 dBm0.

The TP3064A and TP3067A are characterized for operation from 0°C to 70°C. The TP13064A and TP13067A
are characterized for operation from –40°C to 85°C.

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the CMOS gates.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1996, Texas Instruments Incorporated

1

TP3064A, TP3067A, TP13064A, TP13067A
MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER

SCTS025C – SEPTEMBER 1992 –REVISED JUL Y 1996

functional block diagram

VFXI–

VFXI+

VPO+

VPO–

Analog

Input

R1

18

19

1

3

R3

R4

4 VPI

5 VFRO

R2

–

+

R

–

+

R

–

+

RC

Active Filter

Voltage

Reference

RC Active

Filter

Switched­Capacitor

Band-Pass Filter

Comparator

Switched­Capacitor

Low-Pass Filter

Autozero

Logic

S/H

DAC

A/D

Control

Logic

S/H

DAC

Transmit

Regulator

OE

Receive

Regulator

CLK

17
16

13

GSX

ANLG
LOOP

8

DX

DR

–5 V5 V

620 2

V

ANLG GNDV

CC

BB

Timing and Control

11 10 12 9 147

MCLKX MCLKR/

PDN

BCLKX BCLKR/

CLKSEL

FSR

FSX

15

TSX

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

DESCRIPTION

TP3064A, TP3067A, TP13064A, TP13067A

MONOLITHIC SERIAL INTERFACE

COMBINED PCM CODEC AND FILTER

SCTS025C – SEPTEMBER 1992 –REVISED JUL Y 1996

Terminal Functions

TERMINAL

NAME NO.

ANLG GND 2 Analog ground. All signals are referenced to ANLG GND.
ANLG LOOP 16 Analog loopback control input. Must be set to logic low for normal operation. When pulled to logic high, the transmit

BCLKR/CLKSEL 9 The bit clock that shifts data into DR after the FSR leading edge. May vary from 64 kHz to 2.048 MHz. Alternately,

BCLKX 12 The bit clock that shifts out the PCM data on DX. BCLKX can vary from 64 kHz to 2.048 MHz, but must be synchronous

DR 8 Receive data input. PCM data is shifted into DR following the FSR leading edge.
DX 13 The 3-state PCM data output that is enabled by FSX.
FSR 7 Receive frame sync pulse input that enables BCLKR to shift PCM data in DR. FSR is an 8-kHz pulse train (see Figures

FSX 14 Transmit frame sync pulse that enables BCLKX to shift out the PCM data on DX. FSX is an 8-kHz pulse train (see

GSX 17 Analog output of the transmit input amplifier. GSX is used to externally set gain.
MCLKR/PDN 10 Receive master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be synchronous with MCLKX, but should

MCLKX 11 Transmit master clock (must be 1.536 MHz, 1.544 MHz, or 2.048 MHz). May be asynchronous with MCLKR
TSX 15 Open-drain output that pulses low during the encoder time slot
V

BB

V

CC

VFRO 5 Analog output of the receive filter
VFXI+ 19 Noninverting input of the transmit input amplifier
VFXI– 18 Inverting input of the transmit input amplifier
VPI 4 Inverting input to the receive power amplifier. Also powers down both amplifiers when connected to V
VPO+ 1 The noninverted output of the receive power amplifier
VPO– 3 The inverted output of the receive power amplifier

filter input is disconnected from the output of the transmit preamplifier and connected to VPO+ of the receive power
amplifier.

can be a logic input that selects either 1.536 MHz/1.544 MHz or 2.048 MHz for master clock in synchronous mode.
BCLKX is used for both transmit and receive directions (see Table 1).

with MCLKX.

1 and 2 for timing details).

Figures 1 and 2 for timing details).

be synchronous for best performance. When MCLKR is connected continuously low, MCLKX is selected for all internal
timing. When MCLKR is connected continuously high, the device is powered down.

20 Negative power supply. VBB = –5 V ± 5%

6 Positive power supply. VCC = 5 V ± 5%

BB

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

TP3064A, TP3067A, TP13064A, TP13067A

Operating free-air temperature, T

°C

MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER

SCTS025C – SEPTEMBER 1992 –REVISED JUL Y 1996

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V
Supply voltage, V
Voltage range at any analog input or output V
Voltage range at any digital input or output V

(see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

BB

CC

CC

+ 0.3 V to VBB – 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

+ 0.3 V to GND – 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Continuous total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Operating free-air temperature range, T

: TP3064A, TP3067A 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . .

A

TP13064A, TP13067A –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package 260°C. . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTE 1: All voltages are with respect to GND.

DISSIPATION RATING TABLE

PACKAGE

DW 1025 mW 8.2 mW/°C 656 mW 533 mW

N 1150 mW 9.2 mW/°C 736 mW 598 mW

TA ≤ 25°C

POWER RATING

DERATING FACTOR

ABOVE TA = 25°C

TA = 70°C

POWER RATING

TA = 85°C

POWER RATING

recommended operating conditions (see Note 2)

MIN NOM MAX UNIT

Supply voltage, V
Supply voltage, V
High-level input voltage, V
Low-level input voltage, V
Common-mode input voltage range, V
Load resistance at GSX, R
Load capacitance at GSX, C

p

‡

Measure with CMRR > 60 dB.

NOTE 2: T o avoid possible damage to these CMOS devices and resulting reliability problems, the power-up procedure described in the device

CC
BB

IH

IL

L

L

p

power-up sequence paragraphs later in this document should be followed.

A

ICR

‡

TP3064A, TP3067A 0 70
TP13064A, TP13067A –40 85

4.75 5 5.25 V

–4.75 –5 –5.25 V

2.2 V

0.6 V

±2.5 V

10 kΩ

50 pF

°

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PARAMETER

TEST CONDITIONS

UNIT

ICCSupply current from V

No load

mA

IBBSupply current from V

No load

mA

VOLLow-level output voltage

V

TP3064A, TP3067A, TP13064A, TP13067A

MONOLITHIC SERIAL INTERFACE

COMBINED PCM CODEC AND FILTER

SCTS025C – SEPTEMBER 1992 –REVISED JUL Y 1996

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)

supply current

TP306xA TP1306xA

MIN TYP†MAX MIN TYP†MAX

pp

pp

†

All typical values are at VCC = 5 V, VBB = –5 V, and TA = 25°C.

CC

BB

Power down
Active
Power down
Active

electrical characteristics at VCC = 5 V ± 5%, VBB = –5 V ± 5%, GND at 0 V , TA = 25°C (unless otherwise
noted)

digital interface

PARAMETER TEST CONDITIONS MIN MAX UNIT

V

I
I
I

High-level output voltage DX IH = –3.2 mA 2.4 V

OH

p

High-level input current VI = VIH to V

IH

Low-level input current All digital inputs VI = GND to V

IL

Output current in high-impedance state DX VO = GND to V

OZ

DX IL = 3.2 mA 0.4
TSX IL = 3.2 mA, Drain open 0.4

0.5 1 0.5 1.2
6 10 6 11

0.5 1 0.5 1.2
6 10 6 11

CC

IL

CC

±10 µA
±10 µA
±10 µA

analog interface with transmit amplifier input

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

I

I

r

i

r

o

A

V

B

I

V

IO

CMRR Common-mode rejection ratio 60 dB
k

SVR

†

All typical values are at VCC = 5 V, VBB = –5 V, and TA = 25°C.

Input current VFXI+ or VFXI– VI = –2.5 V to 2.5 V ±200 nA
Input resistance VFXI+ or VFXI– VI = –2.5 V to 2.5 V 10 MΩ
Output resistance Closed loop, Unit gain 1 3 Ω
Output dynamic range GSX RL ≥ 10 kΩ ±2.8 V
Open-loop voltage amplification VFXI+ to GSX 5000
Unity-gain bandwidth GSX 1 2 MHz
Input offset voltage VFXI+ or VFXI– ±20 mV

Supply-voltage rejection ratio 60 dB

analog interface with receive filter

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

Output resistance VFRO 1 3 Ω
Load resistance VFRO = ±2.5 V 600 Ω
Load capacitance VFRO to GND 500 pF
Output dc offset voltage VFRO to GND ±200 mV

†

All typical values are at VCC = 5 V, VBB = –5 V, and TA = 25°C.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

TP3064A, TP3067A, TP13064A, TP13067A

k

Suppl

oltage rejection ratio of V

or V

VPO– connected to VPI

dB

MONOLITHIC SERIAL INTERFACE
COMBINED PCM CODEC AND FILTER

SCTS025C – SEPTEMBER 1992 –REVISED JUL Y 1996

analog interface with power amplifiers

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

I

Input current VPI = –1 V to 1 V ±100 nA

I

r

Input resistance VPI = –1 V to 1 V 10 MΩ

i

r

Output resistance VPO+ or VPO– Inverting unity gain 1 Ω

o

A

Voltage amplification VPO– or VPO+ VPO– = 1.77 Vrms, RL = 600 Ω –1

V

B

Unity-gain bandwidth VPO– Open loop 400 kHz

I

V

Input offset voltage ±25 mV

IO

pp

SVR

R

L

C

L

†

All typical values are at VCC = 5 V, VBB = –5 V, and TA = 25°C.

y-v

Load resistance Connected from VPO+ to VPO– 600 Ω
Load capacitance 100 pF

CC

BB

0 kHz to 4 kHz 60
4 kHz to 50 kHz 36

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265