Texas Instruments TNETX4090 User Manual

ThunderSWITCH II

D

Single-Chip 100-/1000-Mbit/s Device

D

Integrated Physical Coding Sublayer (PCS)
Logic Provides Direct Interface to Gigabit
Transceivers

D

Integrated Address-Lookup Engine and
Table Memory for 2-K Addresses

D

Supports IEEE Std 802.1Q Virtual-LAN
(VLAN) Tagging Scheme

D

Provides Data Path for Network
Management Information [No External
Media-Access Control (MAC) Required]

D

Full-Duplex IEEE Std 802.3 Flow Control

D

Half-Duplex Back-Pressure Flow Control

D

Fully Nonblocking Architecture Using
High-Bandwidth Rambus Memory

D

Simple Expansion Via the Gigabit Interface
for Higher-Density Port Solutions

TNETX4090



9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999

D

Port Trunking/Load Sharing for
High-Bandwidth Interswitch Links

D

Supports Pretag Extended Port Awareness

D

EEPROM Interface for Autoconfiguration
(No CPU Required for Nonmanaged Switch)

D

Provides Direct Input/Output (DIO) Interface
for Configuration and Statistics Information

D

Supports On-Chip Per-Port Storage for
Etherstat and Remote Monitoring (RMON)
Management Information Bases (MIBs)

D

Fabricated in 2.5-/3.3-V Low-Voltage
Technology

D

Supports Ring-Cascade Mode

D

Supports Spanning Tree

D

Packaged in 352-Terminal Ball Grid Array
Package

description

The TNETX4090 is a 9-port 100-/1000-Mbit/s nonblocking Ethernet switch with an on-chip address-lookup
engine. The TNETX4090 provides a low-cost, high-performance switch solution. The TNETX4090 is a fully
manageable desktop switch solution achieved by combining the TNETX4090 with physical interfaces and
high-bandwidth rambus-based packet memory and a CPU. The TNETX4090 also provides an interface capable
of receiving and transmitting simple-network management protocol (SNMP) and bridge protocol data units
(BPDU) (spanning tree) frames.

The TNETX4090 provides eight 10-/100-Mbit/s interfaces and one 100-/1000-Mbit/s interface. In half-duplex
mode, all ports support back-pressure flow control to reduce the risk of data loss for a long burst of activity . In
the full-duplex mode of operation, the device uses IEEE Std 802.3 frame-based flow control. With full-duplex
capability , ports 0–7 support 200-Mbit/s aggregate bandwidth connections. Port 8 supports 2 Gbit/s to desktops,
high-speed servers, hubs, or other switches in the full-duplex mode. The physical coding sublayer (PCS)
function is integrated on chip to provide a direct 10-bit interface to the gigabit Ethernet transceiver. The
TNETX4090 also supports port trunking/load sharing on the 10-/100-Mbit ports. This can be used to group ports
on interswitch links to increase the effective bandwidth between the systems. In the ring-cascade mode, port 8
can be used to connect multiple devices in a ring topology , which provides a low-cost, high-port-density desktop
switch. Pretagging and extended port awareness allow the TNETX4090 to be used as a front end to a router
or crossbar switch to build a cost-effective, high-density, high-performance system.

The internal address-lookup engine (IALE) supports up to 2-K unicast/multicast and broadcast addresses and
up to 64 IEEE Std 802.1Q VLANs. For interoperability, each port can be programmed as an access port or
non-access port to recognize VLAN tags and transmit frames with VLAN tags to other systems that support
VLAN tagging. The IALE performs destination- and source-address comparisons and forwards unknown
source- and destination-address packets to ports specified via programmable masks.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TI, ThunderSWITCH, and ThunderSWITCH II are trademarks of Texas Instruments Incorporated.
Ethernet and Etherstat are trademarks of Xerox Corporation.
Secure Fast Switching is a trademark of Cabletron Systems, Inc.
Port-trunking and load-sharing algorithms were contributed by Cabletron Systems, Inc. and are derived from, and compatible with, Secure Fast
Switching.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1998, Texas Instruments Incorporated

1

TNETX4090
ThunderSWITCH II



9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999

description (continued)

MII

10/100

MAC

Switching Engine

(Queue Manager)

Rambus

Controller

MII

10/100

MAC

DRAM

MII

10/100

MAC

Local Packet Switching Memory

MII

10/100

MAC

VLAN 802.1Q

Address-Lookup Engine

2048 CAM

10/100

MAC

and

MII

MII

10/100

MAC

10/100

MAC

100/1000

MAC

GMII/PMA

MII

MII

10/100

MAC

Hardware

RMON

and

Etherstat

MIB

EEPROM

I/F

CPU I/F

With
DMA

100-M

Management

MAC

MDIO

I/F

LED

I/F

JTAG

I/F

Figure 1. TNETX4090 Block Diagram

Statistics for the Etherstat, SNMP, and remote-monitoring management information base (RMON MIB) are
independently collected for each of the nine ports. Access to the statistics counters is provided via the direct
input/output (DIO) interface. Management frames can be received and transmitted via the DIO interface,
creating a complete network management solution. Figure 1 is a block diagram of the TNETX4090.

The TNETX4090 memory solution combines low cost and extremely high bandwidth, using 600-Mbit/pin/s
concurrent RDRAM. The packet memory has been implemented to maximize efficiency with the RDRAM
architecture. Data is buffered internally and transferred to/from packet memory in 128-byte bursts. Extremely
high-memory bandwidth is maintained, allowing all ports to be active without bottlenecking at the memory buffer .

The TNETX4090 is fabricated with a 2.5-V technology . The inputs are 3.3-V tolerant and the outputs are capable
of directly interfacing to TTL levels. This provides the customer with a broad choice of interfacing device options.

Signal names and their terminal assignments are sorted alphabetically in Table 1.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ThunderSWITCH II

Description 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Terminal Functions 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DIO Interface Description 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receiving/Transmitting Management Frames 27. . . . . . . . . . .

State of DIO Signal Terminals During Hardware Reset 28. . .

IEEE Std 802.1Q VLAN Tags on the NM Port 28. . . . . . . . . . .

Frame Format on the NM Port 28. . . . . . . . . . . . . . . . . . . . . . . .

Full-Duplex NM Port 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

NM Bandwidth and Priority 31. . . . . . . . . . . . . . . . . . . . . . . . . . .

Interrupt Processing 31. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

PHY Management Interface 31. . . . . . . . . . . . . . . . . . . . . . . . . . .

MAC Interface 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receive Control 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Giant (Long) Frames 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Short Frames 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receive Filtering of Frames 32. . . . . . . . . . . . . . . . . . . . . . . . . .

Data Transmission 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transmit Control 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Adaptive Performance Optimization (APO) 33. . . . . . . . . . . . .

Interframe Gap Enforcement 33. . . . . . . . . . . . . . . . . . . . . . . . .

Backoff 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Receive Versus Transmit Priority 33. . . . . . . . . . . . . . . . . . . . .

10-/100-Mbit/s MII (ports 0–7) 34. . . . . . . . . . . . . . . . . . . . . . . .

Speed, Duplex, and Flow-Control Negotiation 34. . . . . . . . . .

100-/1000-Mbit/s PHY Interface (Port 8) 36. . . . . . . . . . . . . . . . .

Speed, Duplex, and Flow-Control Negotiation 36. . . . . . . . . .

Full-Duplex Hardware Flow Control 37. . . . . . . . . . . . . . . . . . .

Pretagging and Extended Port Awareness 38. . . . . . . . . . . . .

Ring-Cascade Topology 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

EEPROM Interface 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Interaction of EEPROM Load With the SIO Register 43. . . . .

Summary of EEPROM Load Outcomes 43. . . . . . . . . . . . . . . .

Compatibility With Future Device Revisions 44. . . . . . . . . . . .

LED Interface 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Lamp Test 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Multi-LED Display 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

TNETX4090



9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999

Contents

PCS Duplex LED 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RDRAM Interface 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JTAG Interface 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

HIGHZ Instruction 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RACBIST Instruction 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Frame Routing 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

VLAN Support 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Address Maintenance 49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Port Trunking/Load Sharing 54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Port-Trunking Example 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Extended Port Awareness 55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Flow Control 56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Other Flow-Control Mechanisms 57. . . . . . . . . . . . . . . . . . . . . . . . .

System Test Capabilities 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RDRAM 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Writing RDRAM 57. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reading RDRAM 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Internal Wrap Test 58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Duplex Wrap Test 59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Absolute Maximum Ratings 60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Recommended Operating Conditions 60. . . . . . . . . . . . . . . . . . . . .

Electrical Characteristics 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Timing Requirements 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JTAG Interface 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Control Signals 61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Physical Medium Attachment Interface (Port 8) 62. . . . . . . . . . . .

Receive 62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Transmit 63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

GMII (Port 8) 64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

MII (Ports 0–8) 66. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

RDRAM Interface 68. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DIO Interface 69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

EEPROM Interface 71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

LED Interface 72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Parameter Measurement Information 73. . . . . . . . . . . . . . . . . . . . . .

Mechanical Data 76. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

TNETX4090
ThunderSWITCH II



9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999

26 24 22 20 18 16 14 12 10 8 6 4 225 23 21 19 17 15 13 11 9 7 5 3 1

GGP PACKAGE

(BOTTOM VIEW)

A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ThunderSWITCH II



9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

TNETX4090

SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999

Table 1. Signal-to-Ball Mapping (Signal Names Sorted Alphabetically)

SIGNAL

NAME

DBUS_CTL
DBUS_DATA0
DBUS_DATA1
DBUS_DATA2
DBUS_DATA3
DBUS_DATA4
DBUS_DATA5
DBUS_DATA6
DBUS_DATA7
DBUS_DATA8
DBUS_EN
DCCTRL
DRX_CLK
DTX_CLK
DVREF
ECLK
EDIO
FLOW
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

BALL

NO.

Y26
AC26
AA24
AB26

Y24

V24

U25

U26

T26

R25

T25

P24

V26

V25
AA26

L26

M26

AF8

A1

A2
A13
A14
A25
A26

AF13
AF14

B1

B3
B24
B26

C2
C25

N1
N26

P1
P25
P26
R23
R24
R26
T24
U23

W23
W24
W25
W26

Y23
Y25

AA23
AA25
AB25

AD2

AD25

AE1
AE3

AE24
AE26

AF1
AF2

AF25

SIGNAL

NAME

GND
GNDa
L08_DPLX
LED_CLK
LED_DATA
M00-COL
M00_CRS
M00_LINK
M00_RCLK
M00_RENEG
M00_RXD0
M00_RXD1
M00_RXD2
M00_RXD3
M00_RXDV
M00_RXER
M00_TCLK
M00_TXD0
M00_TXD1
M00_TXD2
M00_TXD3
M00_TXEN
M00_TXER
M01_COL
M01_CRS
M01_LINK
M01_RCLK
M01_RENEG
M01_RXD0
M01_RXD1
M01_RXD2
M01_RXD3
M01_RXDV
M01_RXER
M01_TCLK
M01_TXD0
M01_TXD1
M01_TXD2
M01_TXD3
M01_TXEN
M01_TXER
M02_COL
M02_CRS
M02_LINK
M02_RCLK
M02_RENEG
M02_RXD0
M02_RXD1
M02_RXD2
M02_RXD3
M02_RXDV
M02_RXER
M02_TCLK
M02_TXD0
M02_TXD1
M02_TXD2
M02_TXD3
M02_TXEN
M02_TXER
M03_COL

BALL

NO.

AF26

U24
AE18
AD19
AE19

C21

B21

B19

A21

C26

A20

B20

C20

D20

D19

C19

B23

A23

A22

B22

C22

D22

D21

D16

C16

B14

B16

D26

A15

B15

C15

D15

A16

C14

C17

A19

A18

B18

C18

B17

A17

C11

B11

A9

A11

D1
A10
B10
C10
D10

C9

B9
C13
A12
B12
C12
D12
B13
D11

A6

SIGNAL

NAME

M03_CRS
M03_LINK
M03_RCLK
M03_RENEG
M03_RXD0
M03_RXD1
M03_RXD2
M03_RXD3
M03_RXDV
M03_RXER
M03_TCLK
M03_TXD0
M03_TXD1
M03_TXD2
M03_TXD3
M03_TXEN
M03_TXER
M04_COL
M04_CRS
M04_LINK
M04_RCLK
M04_RENEG
M04_RXD0
M04_RXD1
M04_RXD2
M04_RXD3
M04_RXDV
M04_RXER
M04_TCLK
M04_TXD0
M04_TXD1
M04_TXD2
M04_TXD3
M04_TXEN
M04_TXER
M05_COL
M05_CRS
M05_LINK
M05_RCLK
M05_RENEG
M05_RXD0
M05_RXD1
M05_RXD2
M05_RXD3
M05_RXDV
M05_RXER
M05_TCLK
M05_TXD0
M05_TXD1
M05_TXD2
M05_TXD3
M05_TXEN
M05_TXER
M06_COL
M06_CRS
M06_LINK
M06_RCLK
M06_RENEG
M06_RXD0
M06_RXD1

BALL

NO.

B6
A4
C6
C1
A5
B5
C5
D5
C4
B4
A8
A7
B7
C7
D7
B8
C8
H2
H1
L3
J3
F3
J1
K1
K2
K3
J2
L4
F1
G1
G2
G3
G4
H4
H3
N2
P3
T2
P2
F2
R1
R2
R3
R4
T4
T3

L2
M1
M2
M3
M4

L1
N3

V1
W3

AA1

W2

AA3

Y1

Y2

SIGNAL

NAME

M06_RXD2
M06_RXD3
M06_RXDV
M06_RXER
M06_TCLK
M06_TXD0
M06_TXD1
M06_TXD2
M06_TXD3
M06_TXEN
M06_TXER
M07_COL
M07_CRS
M07_LINK
M07_RCLK
M07_RENEG
M07_RXD0
M07_RXD1
M07_RXD2
M07_RXD3
M07_RXDV
M07_RXER
M07_TCLK
M07_TXD0
M07_TXD1
M07_TXD2
M07_TXD3
M07_TXEN
M07_TXER
M08_COL
M08_CRS
M08_EWRAP
M08_GTCLK
M08_LINK
M08_LREF
M08_MII
M08_PMA
M08_RCLK
M08_RFCLK
M08_RXD0
M08_RXD1
M08_RXD2
M08_RXD3
M08_RXD4
M08_RXD5
M08_RXD6
M08_RXD7
M08_RXDV
M08_RXER
M08_TXD0
M08_TXD1
M08_TXD2
M08_TXD3
M08_TXD4
M08_TXD5
M08_TXD6
M08_TXD7
M08_TXEN
M08_TXER
MDCLK

BALL

NO.

Y3
Y4
W1

AA2

T1
U1
U2
U3
U4
V3
V2

AC6
AD6
AF3
AE6
AD1
AF7
AE7
AD7
AC7
AC8
AD8
AD4
AF5
AE5
AD5
AC5
AE4

AF4
AD12
AC12
AE13
AF17
AE17
AF12
AC17
AD17
AE12
AD13

AF9

AE9

AD9
AF10
AE10
AD10

AF11
AE11
AD11
AC11
AF16
AE16
AD16
AC16
AF15
AE15
AD15
AC15
AE14
AD14

K26

SIGNAL

NAME

MDIO
MRESET
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

BALL

NO.

K25
K24

A3
A24
C23

D2

D3

D6
D24
D25

E1

E2

E3

E4
E23
E24
E25
E26

F4
F23
F24
F25
F26
G23
G24
G25
G26
H24
H25
H26

J24
J25

J26
K23
N23
N24
N25
AA4
AB1
AB2
AB3
AB4

AB23
AB24

AC1
AC2

AC3
AC24
AC25
AD18
AD26

AE8
AF6

AF18

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

TNETX4090
ThunderSWITCH II



9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999

Table 2. Signal-to-Ball Mapping (Signal Names Sorted Alphabetically) (Continued)

SIGNAL

NAME

RESET
SAD0
SAD1
SCS
SDATA0
SDATA1
SDATA2
SDATA3
SDATA4
SDATA5
SDATA6
SDATA7

BALL

NO.

M23
AF22
AE22
AD22
AF20
AE20
AD20
AC20
AF21
AE21
AD21
AC21

SIGNAL

NAME

SDMA
SINT
SRDY
SRNW
SRXRDY
STXRDY
TCLK
TDI
TDO
TMS
TRST
V

DD(2.5)

BALL

NO.

AF24
AF19
AF23
AC22
AE23
AD23

L24

M24

L23

M25

L25

B2

SIGNAL

V

DD(2.5)

V

DD(2.5)

V

DD(2.5)

V

DD(2.5)

V

DD(2.5)

V

DD(2.5)

V

DD(2.5)

V

DD(2.5)

V

DD(2.5)

V

DD(2.5)

V

DD(2.5)

V

DD(2.5)

NAME

BALL

NO.

B25

C3

C24

D4

D9
D14
D18
D23

J4

J23

N4
P23

SIGNAL

V

DD(2.5)

V

DD(2.5)

V

DD(2.5)

V

DD(2.5)

V

DD(2.5)

V

DD(2.5)

V

DD(2.5)

V

DD(2.5)

V

DD(2.5)

V

DD(2.5)

V

DD(2.5)

V

DD(3.3)

NAME

BALL

NO.

V4
V23
AC4
AC9

AC13
AC18
AC23

AD3

AD24

AE2

AE25

D8

SIGNAL

V

DD(3.3)

V

DD(3.3)

V

DD(3.3)

V

DD(3.3)

V

DD(3.3)

V

DD(3.3)

V

DD(3.3)

V

DD(3.3)

V

DD(3.3)

VDDa

NAME

(2.5)

BALL

NO.

D13
D17
H23

K4
P4

W4
AC10
AC14
AC19

T23

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I/O

DESCRIPTION

I/O

DESCRIPTION

ThunderSWITCH II



9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999

TNETX4090

Terminal Functions

JTAG interface

TERMINAL

NAME NO.

TCLK L24

TDI M24

TDO L23

TMS M25

TRST L25

†

Internal resistors are provided to pull signals to known values. The system designers should determine if additional pullups or pulldowns are
required in their systems.

INTERNAL

RESISTOR

I Pullup

I Pullup

O None

I Pullup

I Pullup

†

T est clock. Clocks state information and test data into and out of the TNETX4090 during operation
of the test port.

T est data input. Serially shifts test data and test instructions into the TNETX4090 during operation
of the test port. An internal pullup resistor is provided on TDI to ensure JTAG compliance.

T est data out. Serially shifts test data and test instructions out of the TNETX4090 during operation
of the test port.

T est mode select. Controls the state of the test-port controller. An internal pullup resistor is provided
on TMS to ensure JTAG compliance.

T est reset. Asynchronously resets the test-port controller . An internal pullup resistor is provided on
TRST

to ensure JTAG compliance.

control logic interface

TERMINAL

NAME NO.

RESET

FLOW

M23 I

AF8 O

Device reset. Asserted for a minimum of 100 µs after power supplies and clocks have stabilized. The system clock
must be operational during reset.

Flow control. When flow control is activated (flow in SysControl = 1) and the number of free external memory
buffers is below the threshold indicated in FlowThreshold, FLOW is asserted.

100-/1000-Mbit/s MAC interface [gigabit media-independent interface (GMII) (port 8)]

TERMINAL

NAME

M08_PMA

M08_MII

†

Internal resistors are provided to pull signals to known values. The system designers should determine if additional pullups or pulldowns are
required in their systems.

INTERNAL

I/O

RESISTOR

I Pullup

I Pullup

†

PMA mode. PMA mode can be selected by either pulling M08_PMA low externally, or by setting the
reqpma bit in the PortxControl register. If M08_PMA
either an MII or GMII interface, as determined by the value of the M08_MII

MII or GMII selection. The value of this terminal is ignored if M08_PMA = 0. 100-Mbit/s MII mode can
be selected by either pulling M08_MII
register. If M08_MII

is allowed to float high, the port is configured as a GMII interface.

DESCRIPTION

is allowed to float high, the port is configured as

terminal.

low externally, or by setting the req100 bit in the PortxControl

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

7

TNETX4090
ThunderSWITCH II



9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999

Terminal Functions (Continued)

100-/1000-Mbit/s MAC interface (GMII mode)

TERMINAL

NAME

M08_COL

M08_CRS
M08_EWRAP
M08_GTCLK

M08_LINK

M08_LREF O None

M08_RCLK
M08_RFCLK
M08_RXD7

M08_RXD6
M08_RXD5
M08_RXD4
M08_RXD3
M08_RXD2
M08_RXD1
M08_RXD0

M08_RXDV
M08_RXER

M08_TXD7
M08_TXD6
M08_TXD5
M08_TXD4
M08_TXD3
M08_TXD2
M08_TXD1
M08_TXD0

M08_TXEN

M08_TXER

†

Internal resistors are provided to pull signals to known values. The system designers should determine if additional pullups or pulldowns are
required in their systems.

INTERNAL

I/O

RESISTOR

I Pulldown

I Pulldown Carrier sense. M08_CRS indicates a frame carrier signal is being received.
O None Enable wrap. M08_EWRAP reflects the state of the loopback bit in the PCS8Control register.
O None Transmit clock. Transmit clock output to attached physical layer (PHY) device.

I Pulldown

I Pullup Receive clock. Receive clock source from the attached PHY.

I Pullup

I Pullup

I Pulldown

I Pulldown Receive error. M08_RXER indicates reception of a coding error on received data.

O None

O None

O None

†

Collision sense. Assertion of M08_COL during half-duplex operation indicates network collision.
Additionally, during full-duplex operation, transmission of new frames does not commence if this
terminal is asserted.

Connection status. M08_LINK indicates the presence of port connection.

– If M08_LINK = 0, there is no link.
– If M08_LINK = 1, the link is OK.

Renegotiate. M08_LREF indicates to the attached PHY device that this device wishes to negotiate
a new configuration.

– Following a 0-to-1 transition of neg in PortxControl, M08_LREF is asserted low, and
remains low until M08_LINK goes low. If M08_LINK was already low, M08_LREF
activated for at least one cycle.
– M08_LREF
of M08_LINK.

Reference clock. Reference clock, used as the clock source for the transmit side of this port and
to generate M08_GTCLK.

Receive data. Byte receive data from the attached PHY. When M08_RXDV is asserted, these
signals carry receive data. Data on these signals is synchronous to M08_RCLK.

Receive data valid. M08_RXDV indicates data on M08_RXD7–M08_RXD0 is valid. This signal is
synchronous to M08_RCLK.

Transmit data. Byte transmit data. When M08_TXEN is asserted, these signals carry transmit data.
Data on these signals is synchronous to M08_GTCLK.

Transmit enable. M08_TXEN indicates valid transmit data on M08_TXD7–M08_TXD0. This signal
is synchronous to M08_GTCLK.

Transmit error. M08_TXER allows coding errors to be propagated between the media-access
control (MAC) and the attached PHY . It is asserted at the end of an under-running frame, enabling
the device to force a coding error.

is asserted low for as long as initd in SysControl = 0, regardless of the state

DESCRIPTION

is still

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ThunderSWITCH II

Terminal Functions (Continued)

100-/1000-Mbit/s MAC interface [physical media attachment (PMA) mode]

TERMINAL

NAME

M08_COL
M08_CRS
M08_EWRAP
M08_GTCLK

M08_LINK

M08_LREF O None

M08_RCLK

M08_RFCLK

M08_RXD7
M08_RXD6
M08_RXD5
M08_RXD4
M08_RXD3
M08_RXD2
M08_RXD1
M08_RXD0

M08_RXDV

M08_RXER

M08_TXD7
M08_TXD6
M08_TXD5
M08_TXD4
M08_TXD3
M08_TXD2
M08_TXD1
M08_TXD0

M08_TXEN

M08_TXER

INTERNAL

I/O

RESISTOR

I Pulldown

I Pulldown Unused. This terminal can be left unconnected.
O None
O None Transmit clock. Transmit clock output to attached SERDES device.

I Pulldown

I Pullup

I Pullup

I Pullup

I Pulldown

I Pulldown

O None

O None

O None

Receive byte clock 1. M08_COL is used to input receive byte clock 1 from the attached SERDES
device.

Enable wrap. Output to attached SERDES device used to enable loopback testing of that device.
M08_EWRAP is asserted when loopback in PCSxControl = 1.

Signal detect. This can be connected to the signal detect output from the external SERDES device.

– If M08_LINK = 0, there is no signal.
– If M08_LINK = 1, signal is present.

Lock to reference. M08_LREF is asserted low during hard reset or when lckref in PortxControl = 1.
It is used by the external SERDES device to lock to its reference clock.

Receive byte clock 0. M08_RCLK is used to input receive byte clock 0 from the attached SERDES
device.

Reference clock. Reference clock, used as the clock source for the transmit side of this port and
to generate M08_GTCLK. M08_RFCLK provides the clock source for the entire internal PCS
sublayer.

Receive data. Least significant eight bits of the 10-bit receive code group. Even-numbered code
groups are latched with M08_COL, and odd-numbered code groups are latched with M08_RCLK.

Receive data valid. M08_RXDV is used to receive the 9th bit of the 10-bit PMA code groups.
Even-numbered code groups are latched with M08_COL, and odd-numbered code groups are
latched with M08_RCLK.

Receive error. M08_RXER is used to receive the 10th bit of the 10-bit PMA code groups.
Even-numbered code groups are latched with M08_COL, and odd-numbered code groups are
latched with M08_RCLK.

Transmit data. Least significant eight bits of the 10-bit transmit code group. Data on these signals
is synchronous to M08_GTCLK.

Transmit enable. M08_TXEN is used to transmit the 9th bit of the 10-bit PMA code groups. Data
on this signal is synchronous to M08_GTCLK.

Transmit error . M08_TXER is used to transmit the 10th bit of the 10-bit PMA code groups. Data on
this signal is synchronous to M08_GTCLK.



9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999

DESCRIPTION

TNETX4090

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9

TNETX4090
ThunderSWITCH II



9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999

Terminal Functions (Continued)

100-/1000-Mbit/s MAC interface [media-independent interface (MII) mode]

TERMINAL

NAME

M08_COL

M08_CRS
M08_EWRAP
M08_GTCLK

M08_LINK

M08_LREF O None

M08_RCLK
M08_RFCLK
M08_RXD7

M08_RXD6

M08_RXD5 I/O

M08_RXD4 I/O

M08_RXD3
M08_RXD2
M08_RXD1
M08_RXD0

M08_RXDV
M08_RXER

M08_TXD7
M08_TXD6
M08_TXD5
M08_TXD4

M08_TXD3
M08_TXD2
M08_TXD1
M08_TXD0

†

Not a true bidirectional terminal. It can only be actively pulled down.

INTERNAL

I/O

RESISTOR

Collision sense. Assertion of M08_COL during half-duplex operation indicates network collision.

I Pulldown

I Pulldown Carrier sense. M08_CRS indicates a frame carrier signal is being received.
O None Enable wrap. M08_EWRAP reflects the state of the loopback bit in the PCS8Control register.
O None Unused. This terminal can be left unconnected.

I Pulldown

I Pullup Receive clock. Receive clock source from the attached PHY or PMI device.

I Pullup Transmit clock. Transmit clock from the attached PHY or PMI device.

I Pullup Unused. These terminals can be left unconnected.

†

Pullup

†

Pullup

I Pullup

I Pulldown

I Pulldown Receive error. Indicates reception of a coding error on received data.

O None Unused. These terminals can be left unconnected, but are driven low.

O None

Additionally, during full-duplex operation, transmission of new frames does not commence if this
terminal is asserted.

Connection status. M08_LINK indicates the presence of port connection.

– If M08_LINK = 0, there is no link.
– If M08_LINK = 1, the link is OK.

Renegotiate. M08_LREF indicates to the attached PHY device that this device wishes to negotiate
a new configuration.

– Following a 0-to-1 transition of neg in PortxControl, M08_LREF is asserted low, and
remains low until M08_LINK goes low. If M08_LINK was already low, M08_LREF
activated for at least one cycle.
– M08_LREF
of M08_LINK.

IEEE Std 802.3x pause frame support selection

– If pulled low either internally or by the attached PHY or PMI device, M08_RXD5 causes the
port to not support pause frames.
– If not pulled low, the port does not support pause frames.

Duplex selection [force half duplex (active low)]

– If pulled low either internally or by the attached PHY or PMI device, the port operates in
half-duplex mode.
– If not pulled low, the port operates in full-duplex mode.

Receive data. Nibble-wide receive data from the attached PHY or PMI device. When M08_RXDV
is asserted, these signals carry receive data. Data on these signals is synchronous to M08_RCLK.

Receive data valid. M08_RXDV indicates data on M08_RXD3–M08_RXD0 is valid. This signal is
synchronous to M08_RCLK.

Transmit data. Nibble-wide transmit data. When M08_TXEN is asserted, these signals carry
transmit data. Data on these signals is synchronous to M08_RFCLK.

is asserted low for as long as initd in SysControl = 0, regardless of the state

DESCRIPTION

is still

10

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I/O

DESCRIPTION

ThunderSWITCH II

Terminal Functions (Continued)

100-/1000-Mbit/s MAC interface [media-independent interface (MII) mode] (continued)

TERMINAL

NAME

M08_TXEN

M08_TXER

10-/100-Mbit/s MAC interface (MII mode) (ports 0–7)

TERMINAL

NAME NO.

M00_COL
M01_COL
M02_COL
M03_COL
M04_COL
M05_COL
M06_COL
M07_COL

M00_CRS
M01_CRS
M02_CRS
M03_CRS
M04_CRS
M05_CRS
M06_CRS
M07_CRS

M00_LINK
M01_LINK
M02_LINK
M03_LINK
M04_LINK
M05_LINK
M06_LINK
M07_LINK

M00_RCLK
M01_RCLK
M02_RCLK
M03_RCLK
M04_RCLK
M05_RCLK
M06_RCLK
M07_RCLK

INTERNAL

I/O

RESISTOR

O None

O None

C21
D16
C11

A6
H2
N2
V1

AC6
B21

C16
B11

B6
H1
P3

W3

AD6
B19

B14

A9
A4

L3

T2
AA1
AF3

A21
B16
A11

C6

J3

P2

W2

AE6

I Pulldown

I Pulldown Carrier sense. Indicates a frame-carrier signal is being received.

I Pulldown

I Pullup Receive clock. Receive clock source from the attached PHY device.

Transmit enable. M08_TXEN indicates valid transmit data on M08_TXD3–M08_TXD0. This signal
is synchronous to M08_RFCLK.

Transmit error. M08_TXER allows coding errors to be propagated between the MAC and the
attached PHY. It is asserted at the end of an under-running frame, enabling the device to force a
coding error.

INTERNAL
RESISTOR

Collision sense. Assertion of Mxx_COL indicates network collision. In full-duplex mode, the
port does not start transmitting a new frame if this signal is active; the value of this terminal
is ignored at all other times.

Connection status. Indicates the presence of port connection:

An internal pullup resistor is provided.



9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999

DESCRIPTION

– If Mxx_LINK = 0, there is no link.
– If Mxx_LINK = 1, the link is OK.

TNETX4090

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

11

TNETX4090

I/O

DESCRIPTION

ThunderSWITCH II



9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999

Terminal Functions (Continued)

10-/100-Mbit/s MAC interface (MII mode) (ports 0–7) (continued)

TERMINAL

NAME NO.

M00_RENEG
M01_RENEG
M02_RENEG
M03_RENEG
M04_RENEG
M05_RENEG
M06_RENEG

M00_RXDV
M01_RXDV
M02_RXDV
M03_RXDV
M04_RXDV
M05_RXDV
M06_RXDV
M07_RXDV

M00_RXD3
M00_RXD2
M00_RXD1
M00_RXD0
M01_RXD3
M01_RXD2
M01_RXD1
M01_RXD0
M02_RXD3
M02_RXD2
M02_RXD1
M02_RXD0
M03_RXD3
M03_RXD2
M03_RXD1
M03_RXD0
M04_RXD3
M04_RXD2
M04_RXD1
M04_RXD0
M05_RXD3
M05_RXD2
M05_RXD1
M05_RXD0
M06_RXD3
M06_RXD2
M06_RXD1
M06_RXD0
M07_RXD3
M07_RXD2
M07_RXD1
M07_RXD0

C26
D26

D1
C1
F3
F2

AA3
D19

A16

C9
C4

J2

T4

W1

AC8
D20

C20
B20
A20
D15
C15
B15
A15
D10
C10
B10
A10

D5
C5
B5
A5
K3
K2
K1

J1
R4
R3
R2
R1
Y4
Y3
Y2
Y1

AC7
AD7
AE7
AF7

INTERNAL
RESISTOR

O None

I Pulldown

I Pullup

Renegotiate. Indicates to the attached PHY device that this port wishes to renegotiate a new
configuration.

Receive data valid. Indicates data on Mxx_RXD7–Mxx_RxD0. is valid. This signal is
synchronous to Mxx_RCLK.

Receive data. Nibble receive data from the attached PHY device. Data on these signals is
synchronous to Mxx_RCLK. When Mxx_RXDV and Mxx_RXER are low, these terminals are
sampled the cycle before Mxx_LINK goes high to configure the port, based on capabilities
negotiated by the attached PHY device as follows:

– Mxx_RXD0 indicates full-duplex mode when high; half duplex when low, and sets
duplex in PortxStatus.
– Mxx_RXD1 indicates IEEE Std 802.3 pause frame support when high; no pause
when low, and sets pause in PortxStatus.
– Mxx_RXD2 indicates 100 Mbit/s when high; 10 Mbit/s when low, and sets speed in
PortxStatus.
– Mxx_RXD3 is unused and is ignored.

12

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I/O

DESCRIPTION

ThunderSWITCH II

Terminal Functions (Continued)

10-/100-Mbit/s MAC interface (MII mode) (ports 0–7) (continued)

TERMINAL

NAME NO.

M00_RXER
M01_RXER
M02_RXER
M03_RXER
M04_RXER
M05_RXER
M06_RXER
M07_RXER

M00_TCLK
M01_TCLK
M02_TCLK
M03_TCLK
M04_TCLK
M05_TCLK
M06_TCLK
M07_TCLK

M00_TXD3
M00_TXD2
M00_TXD1
M00_TXD0
M01_TXD3
M01_TXD2
M01_TXD1
M01_TXD0
M02_TXD3
M02_TXD2
M02_TXD1
M02_TXD0
M03_TXD3
M03_TXD2
M03_TXD1
M03_TXD0
M04_TXD3
M04_TXD2
M04_TXD1
M04_TXD0
M05_TXD3
M05_TXD2
M05_TXD1
M05_TXD0
M06_TXD3
M06_TXD2
M06_TXD1
M06_TXD0
M07_TXD3
M07_TXD2
M07_TXD1
M07_TXD0

C19
C14

B9
B4

L4

T3
AA2
AD8

B23
C17
C13

A8

F1

L2

T1
AD4

C22
B22
A22
A23
C18
B18
A18
A19
D12
C12
B12
A12

D7
C7
B7
A7
G4
G3
G2
G1
M4
M3
M2
M1
U4
U3
U2

U1
AC5
AD5
AE5
AF5

INTERNAL
RESISTOR

I Pulldown Receive error. Indicates reception of a coding error on received data.

I Pullup Transmit clock. Transmit clock source from the attached PHY or PMI device.

Transmit data. Byte transmit data. When Mxx_TXEN is asserted, these signals carry
transmit data. Data on these signals is synchronous to Mxx_TCLK. When Mxx_TXEN,
Mxx_TXER, and Mxx_LINK are all low, these terminals indicate the desired capabilities for
autonegotiation as follows:

O None



9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999

– Mxx_TXD0 indicates full-duplex capability when high; half duplex when low, as
determined by reqhd in PortxControl.
– Mxx_TXD1 indicates IEEE Std 802.3 pause frame support when high; no pause
when low, as determined by reqnp in PortxControl.
– Mxx_TXD2 indicates 100 Mbit/s when high; 10 Mbit/s when low, as determined by
req10 in PortxControl.
– Mxx_TXD3 is unused and is 0.

TNETX4090

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

13

TNETX4090

I/O

DESCRIPTION

I/O

DESCRIPTION

ThunderSWITCH II



9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999

Terminal Functions (Continued)

10-/100-Mbit/s MAC interface (MII mode) (ports 0–7) (continued)

TERMINAL

NAME NO.

M00_TXEN
M01_TXEN
M02_TXEN
M03_TXEN
M04_TXEN
M05_TXEN
M06_TXEN
M07_TXEN

M00_TXER
M01_TXER
M02_TXER
M03_TXER
M04_TXER
M05_TXER
M06_TXER
M07_TXER

D22
B17
B13

B8
H4
L1
V3

AE4
D21

A17
D11

C8
H3
N3
V2

AF4

INTERNAL
RESISTOR

O None

O None

Transmit enable. Indicates valid transmit data on Mxx_TXDn. This signal is synchronous to
Mxx_TCLK.

Transmit error . Allows coding errors to be propagated across the MII. Mxx_TXER is asserted
at the end of an under-running frame, enabling the TNETX4090 to force a coding error.

MII management interface

TERMINAL

NAME NO.

MDCLK

MDIO

MRESET

K26 O Pullup

K25 I/O Pullup

K24 O Pullup

INTERNAL
RESISTOR

Serial MII management data clock. Disabled [high-impedance (Z) state] through the use of the
serial input/output (SIO) register. An internal pullup resistor is provided.

Serial MII management data input/output. Disabled [high-impedance (Z) state] through the use
of the SIO register. An internal pullup resistor is provided.

Serial MII management reset. Disabled [high-impedance (Z) state] through the use of the SIO
register. An internal pullup resistor is provided.

14

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I/O

DESCRIPTION

ThunderSWITCH II

Terminal Functions (Continued)

RDRAM interface

TERMINAL

NAME NO.

DBUS_CTL

DBUS_DATA0
DBUS_DATA1
DBUS_DATA2
DBUS_DATA3
DBUS_DATA4
DBUS_DATA5
DBUS_DATA6
DBUS_DATA7
DBUS_DATA8

DBUS_EN

DCCTRL

DRX_CLK

DTX_CLK
DVREF

NOTE 1: RSL is a low-voltage swing, active-low signaling technology.

Y26 O None

AC26

AA24
AB26

Y24
V24
U25
U26
T26
R25

T25 O None

P24 I None

V26 O None

V25 I None

AA26 I None Reference voltage. Logic threshold reference voltage for RSL signals.

INTERNAL
RESISTOR

I/O None

Bus control. Controls signal-to-frame packets, transmits part of the operation code,
initiates data transfers, and terminates data transfers. This is a rambus signal logic (RSL)
signal (see Note 1).

Bus data. Signal lines for request, write-data, and read-data packets. The request packet
contains the address, operation codes, and other control information. These are RSL
signals (see Note 1).

Bus enable. Controls signal-to-transfer column addresses for random-access
(nonsequential) transactions. This is an RSL signal (see Note 1).

Current control program. Connected to the current control resistor whose other terminal
is connected to the termination voltage.

Receive clock. This signal is derived from DTX_CLK. This is an RSL signal (see Note 1).
It is connected directly to DTX_CLK in the TNETX4090.

Transmit clock. This is an RSL signal (see Note 1). The primary internal clock is derived
from this signal.



9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

TNETX4090

SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

15

TNETX4090

I/O

DESCRIPTION

I/O

DESCRIPTION

ThunderSWITCH II



9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999

Terminal Functions (Continued)

DIO interface

TERMINAL

NAME NO.

SAD0
SAD1

SCS
SDATA0

SDATA1
SDATA2
SDATA3
SDATA4
SDATA5
SDATA6
SDATA7

SDMA

SINT

SRDY

SRNW

SRXRDY

STXRDY

AF22
AE22

AD22 I Pullup
AF20

AE20
AD20
AC20
AF21
AE21
AD21
AC21

AF24 I Pullup

AF19 O None

AF23 O Pullup

AC22 I Pullup

AE23 O None

AD23 O None

INTERNAL
RESISTOR

I Pullup

I/O Pullup DIO data bus. Byte-wide bidirectional DIO port. External pullup resistors are required.

DIO address bus. Selects the internal host registers provided SDMA is high. Internal pullup
resistors are provided.

DIO chip select. When low, SCS indicates a DIO port access is valid. An internal pullup resistor
is provided.

DIO DMA select. When low, SDMA modifies the behavior of the DIO interface to allow it to
operate efficiently with an external direct memory access (DMA) controller . SAD0 and SAD1 are
not used to select the internal host register for the access. Instead, the DIO address to access
internal registers is provided by the DMAAddress register, and one of two host register
addresses is selected according to dmainc in SysControl. An internal pullup resistor is provided.

Interrupt. Interrupt to the attached microprocessor. The interrupt type can be found in the Int
register.

DIO ready. When low during reads, SRDY indicates to the host when data is valid to be read.
When low during writes, SRDY
for one clock cycle before placing the output in high impedance after SCS
internal pullup resistor is provided.

DIO read not write

An internal pullup resistor is provided.
Network management (NM) port, receive ready. When high, SRXRDY indicates that the NM

port’s receive buffers are completely empty and the NM port is able to receive a frame of any
size up to 1535 bytes in length.

Network management (NM) port, transmit ready. When high, STXRDY indicates that at least
one buffer of frame data is available to be read by the management CPU. It outputs a 1 if any
of the end-of-frame (eof), start-of-frame (sof), or interior-of-frame (iof) bits in NMTxControl is set
to 1, otherwise, it outputs 0.

indicates when data has been received. SRDY is driven high

is taken high. An

– When high, read operation is selected.
– When low, write operation is selected.

EEPROM interface

TERMINAL

NAME NO.

ECLK
EDIO

16

L26 O None EEPROM data clock. An internal pullup resistor is provided.

M26 I/O Pullup EEPROM data input/output. An internal pullup resistor is provided.

INTERNAL
RESISTOR

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I/O

DESCRIPTION

I/O

DESCRIPTION

DESCRIPTION

ThunderSWITCH II

Terminal Functions (Continued)

LED interface

TERMINAL

NAME NO.

LED_CLK
LED_DATA

AD19 O None LED clock. Serial shift clock for the LED status data.
AE19 O None LED data. Serial LED status data.

100-/1000-Mbit/s port PCS LED interface

TERMINAL

NAME NO.

L08_DPLX AE18 None

power supply

TERMINAL

NAME NO.

A1, A2, A13, A14, A25, A26,

AF13, AF14, B1, B3, B24,

B26, C2, C25, N1, N26, P1,

P25, P26, R23, R24, R26,

GND

GNDa

V

DD(2.5)

V

DD(3.3)

VDDa

T24, U23, W23, W24, W25,

W26, Y23, Y25, AA23, AA25,

AB25, AD2, AD25, AE1, AE3,

AE24, AE26, AF1, AF2,

AF25, AF26

B2, B25, C3, C24, D4, D9,

D14, D18, D23, J4, J23, N4,

P23, V4, V23, AC4, AC9,

AC13, AC18, AC23, AD3,

AD24, AE2, AE25

D8, D13, D17, H23, K4, P4,

W4, AC10, AC14, AC19

(2.5)

INTERNAL
RESISTOR

INTERNAL
RESISTOR

Duplex LED. When in PMA mode, this terminal is low if the port is configured for full-duplex
operation. It is high at all other times.

Ground. The 0-V reference for the TNETX4090.

U24 Ground. The 0-V reference for the analog functions within the rambus ASIC cell (RAC).

2.5-V supply voltage. Power for the core.

3.3-V supply voltage. Power for the I/Os.

T23 2.5-V supply voltage. Power for the analog functions within the RAC.

TNETX4090



9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

17

TNETX4090
ThunderSWITCH II



9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999

DIO interface description

The DIO is a general-purpose interface that is used with a range of microprocessor or computer system
interfaces. The interface is backward compatible with the existing TI ThunderSWITCH products. The DIO
provides new signals to support external DMA controllers for improved performance.

This interface configures the switch using the attached CPU, and to access statistics registers (see Table 2).
DIO accesses the NM port to allow frame data to be transferred between the CPU and the switch to support
spanning tree, SNMP, and RMON. The CPU reads and writes packets directly under software control or an
external DMA controller can be used to improve performance. See

Guide

, literature number SPAU003, for description of registers.

Table 2. DIO Internal Register Address Map

TNETX4090 Programmer’s Reference

BYTE 3 BYTE 2 BYTE 1 BYTE 0

Port1Control Port0Control 0x0000
Port3Control Port2Control 0x0004
Port5Control Port4Control 0x0008
Port7Control Port6Control 0x000C

Reserved Port8Control 0x0010

Reserved 0x0014–0x003C

Reserved UnkVLANPort MirrorPort UplinkPort 0x0040

Reserved AgingThreshold 0x0044

Reserved 0x0048–0x004C

NLearnPorts 0x0050

TxBlockPorts 0x0054

RxUniBlockPorts 0x0058

RxMultiBlockPorts 0x005C

UnkUniPorts 0x0060

UnkMultiPorts 0x0064

UnkSrcPorts 0x0068

NewVLANIntPorts 0x006C

Reserved 0x0070–0x007C
TrunkMap3 TrunkMap2 TrunkMap1 TrunkMap0 0x0080
TrunkMap7 TrunkMap6 TrunkMap5 TrunkMap4 0x0084

Trunk3Ports Trunk2Ports Trunk1Ports Trunk0Ports 0x0088

Reserved RingPorts 0x008C

Reserved 0x0090–0x009C

DevCode Reserved SIO Revision 0x00A0

DevNode[23:16] DevNode[31:24] DevNode[39:32] DevNode[47:40] 0x00A4

Reserved DevNode[7:0] DevNode[15:8] 0x00A8

MCastLimit 0x00DC

RamStatus RamControl Reserved 0x00E0

Reserved 0x00E4

PauseTime100 PauseTime10 0x00E8

PauseTime1000 Reserved 0x00EC

Reserved FlowThreshold 0x00F0

Reserved LEDControl 0x00F4

DIO

ADDRESS

18

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ThunderSWITCH II



9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

TNETX4090

SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999

Table 2. DIO Internal Register Address Map (Continued)

BYTE 3 BYTE 2 BYTE 1 BYTE 0

SysControl StatControl 0x00F8

Reserved (for EEPROM CRC) 0x00FC

VLAN0Ports 0x0100
VLAN1Ports 0x0104
VLAN2Ports 0x0108
VLAN3Ports 0x010C
VLAN4Ports 0x0110
VLAN5Ports 0x0114
VLAN6Ports 0x0118
VLAN7Ports 0x011C
VLAN8Ports 0x0120

VLAN9Ports 0x0124
VLAN10Ports 0x0128
VLAN11Ports 0x012C
VLAN12Ports 0x0130
VLAN13Ports 0x0134
VLAN14Ports 0x0138
VLAN15Ports 0x013C
VLAN16Ports 0x0140
VLAN17Ports 0x0144
VLAN18Ports 0x0148
VLAN19Ports 0x014C
VLAN20Ports 0x0150
VLAN21Ports 0x0154
VLAN22Ports 0x0158
VLAN23Ports 0x015C
VLAN24Ports 0x0160
VLAN25Ports 0x0164
VLAN26Ports 0x0168
VLAN27Ports 0x016C
VLAN28Ports 0x0170
VLAN29Ports 0x0174
VLAN30Ports 0x0178
VLAN31Ports 0x017C
VLAN32Ports 0x0180
VLAN33Ports 0x0184
VLAN34Ports 0x0188
VLAN35Ports 0x018C
VLAN36Ports 0x0190
VLAN37Ports 0x0194
VLAN38Ports 0x0198
VLAN39Ports 0x019C

DIO

ADDRESS

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TNETX4090
ThunderSWITCH II



9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999

Table 2. DIO Internal Register Address Map (Continued)

BYTE 3 BYTE 2 BYTE 1 BYTE 0

VLAN40Ports 0x01A0
VLAN41Ports 0x01A4
VLAN42Ports 0x01A8
VLAN43Ports 0x01AC
VLAN44Ports 0x01B0
VLAN45Ports 0x01B4
VLAN46Ports 0x01B8
VLAN47Ports 0x01BC
VLAN48Ports 0x01C0
VLAN49Ports 0x01C4
VLAN50Ports 0x01C8
VLAN51Ports 0x01CC
VLAN52Ports 0x01D0
VLAN53Ports 0x01D4
VLAN54Ports 0x01D8
VLAN55Ports 0x01DC
VLAN56Ports 0x01E0
VLAN57Ports 0x01E4
VLAN58Ports 0x01E8
VLAN59Ports 0x01EC
VLAN60Ports 0x01F0
VLAN61Ports 0x01F4
VLAN62Ports 0x01F8
VLAN63Ports 0x01FC

Reserved 0x0200–0x02FC
VLAN1QID VLAN0QID 0x0300
VLAN3QID VLAN2QID 0x0304
VLAN5QID VLAN4QID 0x0308
VLAN7QID VLAN6QID 0x030C
VLAN9QID VLAN8QID 0x0310

VLAN11QID VLAN10QID 0x0314
VLAN13QID VLAN12QID 0x0318
VLAN15QID VLAN14QID 0x031C
VLAN17QID VLAN16QID 0x0320
VLAN19QID VLAN18QID 0x0324
VLAN21QID VLAN20QID 0x0328
VLAN23QID VLAN22QID 0x032C
VLAN25QID VLAN24QID 0x0330
VLAN27QID VLAN26QID 0x0334
VLAN29QID VLAN28QID 0x0338
VLAN31QID VLAN30QID 0x033C
VLAN33QID VLAN32QID 0x0340
VLAN35QID VLAN34QID 0x0344

DIO

ADDRESS

20

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ThunderSWITCH II



9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

TNETX4090

SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999

Table 2. DIO Internal Register Address Map (Continued)

BYTE 3 BYTE 2 BYTE 1 BYTE 0

VLAN37QID VLAN36QID 0x0348
VLAN39QID VLAN38QID 0x034C
VLAN41QID VLAN40QID 0x0350
VLAN43QID VLAN42QID 0x0354
VLAN45QID VLAN44QID 0x0358
VLAN47QID VLAN46QID 0x035C
VLAN49QID VLAN48QID 0x0360
VLAN51QID VLAN50QID 0x0364
VLAN53QID VLAN52QID 0x0368
VLAN55QID VLAN54QID 0x036C
VLAN57QID VLAN56QID 0x0370
VLAN59QID VLAN58QID 0x0374
VLAN61QID VLAN60QID 0x0378
VLAN63QID VLAN62QID 0x037C

Port1QTag Port0QTag 0x0380
Port3QTag Port2QT ag 0x0384
Port5QTag Port4QT ag 0x0388
Port7QTag Port6QT ag 0x038C

Reserved Port8QTag 0x0390

Reserved 0x0394–0x03FC
Port1Status Port0Status 0x0400
Port3Status Port2Status 0x0404
Port5Status Port4Status 0x0408
Port7Status Port6Status 0x040C

Reserved Port8Status 0x0410

Reserved 0x0414–0x043C

FindNode[23:16] FindNode[31:24] FindNode[39:32] FindNode[47:40] 0x0440

FindVLAN FindControl FindNode[7:0] FindNode[15:8] 0x0444

FindPort 0x0448

NewNode[23:16] NewNode[31:24] NewNode[39:32] NewNode[47:40] 0x044C

Reserved NewNode[7:0] NewNode[15:8] 0x0450

NewVLAN NewPort 0x0454

AddNode[23:16] AddNode[31:24] AddNode[39:32] AddNode[47:40] 0x0458

AddVLAN AddDelControl AddNode[7:0] AddNode[15:8] 0x045C

AddPort 0x0460

AgedNode[23:16] AgedNode[31:24] AgedNode[39:32] AgedNode[47:40] 0x0464

AgedVLAN AgedPort AgedNode[7:0] AgedNode[15:8] 0x0468

DelNode[23:16] DelNode[31:24] DelNode[39:32] DelNode[47:40] 0x046C

DelVLAN DelPort DelNode[7:0] DelNode[15:8] 0x0470

AgingCounter NumNodes 0x0474

Reserved 0x0478–0x0540

XMultiGroup17 0x0544
XMultiGroup18 0x0548

DIO

ADDRESS

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TNETX4090
ThunderSWITCH II



9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999

Table 2. DIO Internal Register Address Map (Continued)

BYTE 3 BYTE 2 BYTE 1 BYTE 0

XMultiGroup19 0x054C
XMultiGroup20 0x0550
XMultiGroup21 0x0554
XMultiGroup22 0x0558
XMultiGroup23 0x055C
XMultiGroup24 0x0560
XMultiGroup25 0x0564
XMultiGroup26 0x0568
XMultiGroup27 0x056C
XMultiGroup28 0x0570
XMultiGroup29 0x0574
XMultiGroup30 0x0578
XMultiGroup31 0x057C
XMultiGroup32 0x0580
XMultiGroup33 0x0584
XMultiGroup34 0x0588
XMultiGroup35 0x058C
XMultiGroup36 0x0590
XMultiGroup37 0x0594
XMultiGroup38 0x0598
XMultiGroup39 0x059C
XMultiGroup40 0x05A0
XMultiGroup41 0x05A4
XMultiGroup42 0x05A8
XMultiGroup43 0x05AC
XMultiGroup44 0x05B0
XMultiGroup45 0x05B4
XMultiGroup46 0x05B8
XMultiGroup47 0x05BC
XMultiGroup48 0x05C0
XMultiGroup49 0x05C4
XMultiGroup50 0x05C8
XMultiGroup51 0x05CC
XMultiGroup52 0x05D0
XMultiGroup53 0x05D4
XMultiGroup54 0x05D8
XMultiGroup55 0x05DC
XMultiGroup56 0x05E0
XMultiGroup57 0x05E4
XMultiGroup58 0x05E8
XMultiGroup59 0x05EC
XMultiGroup60 0x05F0

DIO

ADDRESS

22

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ThunderSWITCH II



9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

TNETX4090

SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999

Table 2. DIO Internal Register Address Map (Continued)

BYTE 3 BYTE 2 BYTE 1 BYTE 0

XMultiGroup61 0x05F4
XMultiGroup62 0x05F8
XMultiGroup63 0x05FC

Reserved 0x0600–0x060C

PCS8Status PCS8Control 0x0700

Reserved 0x0704

PCS8ANLinkP PCS8ANAdvert 0x0708

PCS8ANNxt PCS8ANExp 0x070C

Reserved PCS8ANLinkPNxt 0x0710

Reserved 0x0714–0x0718

PCS8ExStatus Reserved 0x071C

Reserved 0x0720–0x07FC

Reserved DMAAddress 0x0800
Reserved Int 0x0804
Reserved IntEnable 0x0808

SysTest FreeStackLength 0x080C

RAMAddress 0x0810

Reserved RAMData 0x0814
Reserved NMRxControl 0x0818
Reserved NMTxControl 0x081C

Reserved NMData 0x0820

Reserved 0x0824–0x0FFC

Manufacturing test registers (internal use only) 0x1000–0x10FF

Reserved 0x1900–0x3FFC

Hardware reset 0x4000–0x5FFC

DIO

ADDRESS

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

23

TNETX4090
ThunderSWITCH II



9-PORT 100-/1000-MBIT/S ETHERNET SWITCH

SPWS044E – DECEMBER 1997 – REVISED AUGUST 1999

DIO interface description (continued)

T able 3 and T able 4 list the least significant byte address for the port-specific statistics. Each statistic is four bytes
long. To determine the address of a particular statistic, replace the xx in the head column with the characters
from the tail address. Table 3 has two tail columns: one for even-numbered ports and the other for
odd-numbered ports. See the
a detailed description of the statistic registers.

Example:

Port 7 head = 0x83xx
64-octet frames tail = A8 (odd-numbered port)
Port 7 octet frames statistic = 0x83A8

TNETX4090 Programmer’s Reference Guide,

literature number SPAU003, for

24

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